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[NFC][MC] Use MCRegister in Machine{Sink|Pipeliner}.cpp 

Differential Revision: https://reviews.llvm.org/D89328
This commit is contained in:
Mircea Trofin 2020-10-13 09:29:15 -07:00
parent efd84a5f5d
commit c8fcffe775
3 changed files with 23 additions and 22 deletions
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2
llvm/include/llvm/CodeGen/MachinePipeliner.h
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@ -304,7 +304,7 @@ private:
void checkValidNodeOrder(const NodeSetType &Circuits) const; void checkValidNodeOrder(const NodeSetType &Circuits) const;
bool schedulePipeline(SMSchedule &Schedule); bool schedulePipeline(SMSchedule &Schedule);
bool computeDelta(MachineInstr &MI, unsigned &Delta); bool computeDelta(MachineInstr &MI, unsigned &Delta);
MachineInstr *findDefInLoop(unsigned Reg); MachineInstr *findDefInLoop(Register Reg);
bool canUseLastOffsetValue(MachineInstr *MI, unsigned &BasePos, bool canUseLastOffsetValue(MachineInstr *MI, unsigned &BasePos,
unsigned &OffsetPos, unsigned &NewBase, unsigned &OffsetPos, unsigned &NewBase,
int64_t &NewOffset); int64_t &NewOffset);

8
llvm/lib/CodeGen/MachinePipeliner.cpp
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@ -1632,7 +1632,8 @@ static void computeLiveOuts(MachineFunction &MF, RegPressureTracker &RPTracker,
if (Register::isVirtualRegister(Reg)) if (Register::isVirtualRegister(Reg))
Uses.insert(Reg); Uses.insert(Reg);
else if (MRI.isAllocatable(Reg)) else if (MRI.isAllocatable(Reg))
for (MCRegUnitIterator Units(Reg, TRI); Units.isValid(); ++Units) for (MCRegUnitIterator Units(Reg.asMCReg(), TRI); Units.isValid();
++Units)
Uses.insert(*Units); Uses.insert(*Units);
} }
} }
@ -1645,7 +1646,8 @@ static void computeLiveOuts(MachineFunction &MF, RegPressureTracker &RPTracker,
LiveOutRegs.push_back(RegisterMaskPair(Reg, LiveOutRegs.push_back(RegisterMaskPair(Reg,
LaneBitmask::getNone())); LaneBitmask::getNone()));
} else if (MRI.isAllocatable(Reg)) { } else if (MRI.isAllocatable(Reg)) {
for (MCRegUnitIterator Units(Reg, TRI); Units.isValid(); ++Units) for (MCRegUnitIterator Units(Reg.asMCReg(), TRI); Units.isValid();
++Units)
if (!Uses.count(*Units)) if (!Uses.count(*Units))
LiveOutRegs.push_back(RegisterMaskPair(*Units, LiveOutRegs.push_back(RegisterMaskPair(*Units,
LaneBitmask::getNone())); LaneBitmask::getNone()));
@ -2270,7 +2272,7 @@ void SwingSchedulerDAG::applyInstrChange(MachineInstr *MI,
/// Return the instruction in the loop that defines the register. /// Return the instruction in the loop that defines the register.
/// If the definition is a Phi, then follow the Phi operand to /// If the definition is a Phi, then follow the Phi operand to
/// the instruction in the loop. /// the instruction in the loop.
MachineInstr *SwingSchedulerDAG::findDefInLoop(unsigned Reg) { MachineInstr *SwingSchedulerDAG::findDefInLoop(Register Reg) {
SmallPtrSet<MachineInstr *, 8> Visited; SmallPtrSet<MachineInstr *, 8> Visited;
MachineInstr *Def = MRI.getVRegDef(Reg); MachineInstr *Def = MRI.getVRegDef(Reg);
while (Def->isPHI()) { while (Def->isPHI()) {

35
llvm/lib/CodeGen/MachineSink.cpp
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@ -184,12 +184,12 @@ namespace {
/// to the copy source. /// to the copy source.
void SalvageUnsunkDebugUsersOfCopy(MachineInstr &, void SalvageUnsunkDebugUsersOfCopy(MachineInstr &,
MachineBasicBlock *TargetBlock); MachineBasicBlock *TargetBlock);
bool AllUsesDominatedByBlock(unsigned Reg, MachineBasicBlock *MBB, bool AllUsesDominatedByBlock(Register Reg, MachineBasicBlock *MBB,
MachineBasicBlock *DefMBB, MachineBasicBlock *DefMBB, bool &BreakPHIEdge,
bool &BreakPHIEdge, bool &LocalUse) const; bool &LocalUse) const;
MachineBasicBlock *FindSuccToSinkTo(MachineInstr &MI, MachineBasicBlock *MBB, MachineBasicBlock *FindSuccToSinkTo(MachineInstr &MI, MachineBasicBlock *MBB,
bool &BreakPHIEdge, AllSuccsCache &AllSuccessors); bool &BreakPHIEdge, AllSuccsCache &AllSuccessors);
bool isProfitableToSinkTo(unsigned Reg, MachineInstr &MI, bool isProfitableToSinkTo(Register Reg, MachineInstr &MI,
MachineBasicBlock *MBB, MachineBasicBlock *MBB,
MachineBasicBlock *SuccToSinkTo, MachineBasicBlock *SuccToSinkTo,
AllSuccsCache &AllSuccessors); AllSuccsCache &AllSuccessors);
@ -253,12 +253,11 @@ bool MachineSinking::PerformTrivialForwardCoalescing(MachineInstr &MI,
/// occur in blocks dominated by the specified block. If any use is in the /// occur in blocks dominated by the specified block. If any use is in the
/// definition block, then return false since it is never legal to move def /// definition block, then return false since it is never legal to move def
/// after uses. /// after uses.
bool bool MachineSinking::AllUsesDominatedByBlock(Register Reg,
MachineSinking::AllUsesDominatedByBlock(unsigned Reg, MachineBasicBlock *MBB,
MachineBasicBlock *MBB, MachineBasicBlock *DefMBB,
MachineBasicBlock *DefMBB, bool &BreakPHIEdge,
bool &BreakPHIEdge, bool &LocalUse) const {
bool &LocalUse) const {
assert(Register::isVirtualRegister(Reg) && "Only makes sense for vregs"); assert(Register::isVirtualRegister(Reg) && "Only makes sense for vregs");
// Ignore debug uses because debug info doesn't affect the code. // Ignore debug uses because debug info doesn't affect the code.
@ -560,7 +559,7 @@ bool MachineSinking::PostponeSplitCriticalEdge(MachineInstr &MI,
} }
/// isProfitableToSinkTo - Return true if it is profitable to sink MI. /// isProfitableToSinkTo - Return true if it is profitable to sink MI.
bool MachineSinking::isProfitableToSinkTo(unsigned Reg, MachineInstr &MI, bool MachineSinking::isProfitableToSinkTo(Register Reg, MachineInstr &MI,
MachineBasicBlock *MBB, MachineBasicBlock *MBB,
MachineBasicBlock *SuccToSinkTo, MachineBasicBlock *SuccToSinkTo,
AllSuccsCache &AllSuccessors) { AllSuccsCache &AllSuccessors) {
@ -1312,9 +1311,9 @@ static bool hasRegisterDependency(MachineInstr *MI,
return HasRegDependency; return HasRegDependency;
} }
static SmallSet<unsigned, 4> getRegUnits(unsigned Reg, static SmallSet<MCRegister, 4> getRegUnits(MCRegister Reg,
const TargetRegisterInfo *TRI) { const TargetRegisterInfo *TRI) {
SmallSet<unsigned, 4> RegUnits; SmallSet<MCRegister, 4> RegUnits;
for (auto RI = MCRegUnitIterator(Reg, TRI); RI.isValid(); ++RI) for (auto RI = MCRegUnitIterator(Reg, TRI); RI.isValid(); ++RI)
RegUnits.insert(*RI); RegUnits.insert(*RI);
return RegUnits; return RegUnits;
@ -1364,8 +1363,8 @@ bool PostRAMachineSinking::tryToSinkCopy(MachineBasicBlock &CurBB,
continue; continue;
// Record debug use of each reg unit. // Record debug use of each reg unit.
SmallSet<unsigned, 4> Units = getRegUnits(MO.getReg(), TRI); SmallSet<MCRegister, 4> Units = getRegUnits(MO.getReg(), TRI);
for (unsigned Reg : Units) for (MCRegister Reg : Units)
SeenDbgInstrs[Reg].push_back(MI); SeenDbgInstrs[Reg].push_back(MI);
} }
continue; continue;
@ -1414,8 +1413,8 @@ bool PostRAMachineSinking::tryToSinkCopy(MachineBasicBlock &CurBB,
if (!MO.isReg() || !MO.isDef()) if (!MO.isReg() || !MO.isDef())
continue; continue;
SmallSet<unsigned, 4> Units = getRegUnits(MO.getReg(), TRI); SmallSet<MCRegister, 4> Units = getRegUnits(MO.getReg(), TRI);
for (unsigned Reg : Units) for (MCRegister Reg : Units)
for (auto *MI : SeenDbgInstrs.lookup(Reg)) for (auto *MI : SeenDbgInstrs.lookup(Reg))
DbgValsToSinkSet.insert(MI); DbgValsToSinkSet.insert(MI);
} }