forked from OSchip/llvm-project
[X86][tablgen] Set ShouldBeEmitted to false when isAsmParserOnly is true. NFCI
In fact, an instruction can not be emitted to disassemble table when `isAsmParserOnly` is true, so `isAsmParserOnly=true` implies `ShouldBeEmitted=false`. We check `isAsmParserOnly` in X86FoldTablesEmitter.cpp at a early stage b/c none of them is foldable.
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@ -344,9 +344,7 @@ public:
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RegRec->getValueAsBit("hasNoTrackPrefix") !=
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MemRec->getValueAsBit("hasNoTrackPrefix") ||
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RegRec->getValueAsBit("EVEX_W1_VEX_W0") !=
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MemRec->getValueAsBit("EVEX_W1_VEX_W0") ||
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RegRec->getValueAsBit("isAsmParserOnly") !=
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MemRec->getValueAsBit("isAsmParserOnly"))
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MemRec->getValueAsBit("EVEX_W1_VEX_W0"))
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return false;
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// Make sure the sizes of the operands of both instructions suit each other.
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@ -556,10 +554,10 @@ void X86FoldTablesEmitter::run(formatted_raw_ostream &OS) {
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Target.getInstructionsByEnumValue();
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for (const CodeGenInstruction *Inst : NumberedInstructions) {
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if (!Inst->TheDef->getNameInit() || !Inst->TheDef->isSubClassOf("X86Inst"))
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continue;
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const Record *Rec = Inst->TheDef;
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if (!Rec->getNameInit() || !Rec->isSubClassOf("X86Inst") ||
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Rec->getValueAsBit("isAsmParserOnly"))
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continue;
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// - Do not proceed if the instruction is marked as notMemoryFoldable.
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// - Instructions including RST register class operands are not relevant
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@ -76,7 +76,9 @@ static uint8_t byteFromRec(const Record* rec, StringRef name) {
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}
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RecognizableInstrBase::RecognizableInstrBase(const CodeGenInstruction &insn)
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: Rec(insn.TheDef), ShouldBeEmitted(Rec->isSubClassOf("X86Inst")) {
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: Rec(insn.TheDef),
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ShouldBeEmitted(Rec->isSubClassOf("X86Inst") &&
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!Rec->getValueAsBit("isAsmParserOnly")) {
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if (!ShouldBeEmitted)
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return;
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@ -134,10 +136,6 @@ void RecognizableInstr::processInstr(DisassemblerTables &tables,
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const CodeGenInstruction &insn,
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InstrUID uid)
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{
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// Ignore "asm parser only" instructions.
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if (insn.TheDef->getValueAsBit("isAsmParserOnly"))
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return;
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RecognizableInstr recogInstr(tables, insn, uid);
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if (recogInstr.shouldBeEmitted()) {
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