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[IR,TableGen] Add support for vec3 intrinsic arguments 

Add generic support for vec3 types, and in particular define
llvm_v3f32_ty which will be used by AMDGPU's
llvm.amdgcn.image.bvh.intersect.ray intrinsic.

Differential Revision: https://reviews.llvm.org/D114956
This commit is contained in:
Jay Foad 2021-12-02 12:25:00 +00:00
parent bc7dacf589
commit c8e84c7a5f
3 changed files with 10 additions and 2 deletions
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1
llvm/include/llvm/IR/Intrinsics.td
View File

@ -319,6 +319,7 @@ def llvm_v4bf16_ty : LLVMType<v4bf16>; // 4 x bfloat (__bf16)
def llvm_v8bf16_ty : LLVMType<v8bf16>; // 8 x bfloat (__bf16) def llvm_v8bf16_ty : LLVMType<v8bf16>; // 8 x bfloat (__bf16)
def llvm_v1f32_ty : LLVMType<v1f32>; // 1 x float def llvm_v1f32_ty : LLVMType<v1f32>; // 1 x float
def llvm_v2f32_ty : LLVMType<v2f32>; // 2 x float def llvm_v2f32_ty : LLVMType<v2f32>; // 2 x float
def llvm_v3f32_ty : LLVMType<v3f32>; // 3 x float
def llvm_v4f32_ty : LLVMType<v4f32>; // 4 x float def llvm_v4f32_ty : LLVMType<v4f32>; // 4 x float
def llvm_v8f32_ty : LLVMType<v8f32>; // 8 x float def llvm_v8f32_ty : LLVMType<v8f32>; // 8 x float
def llvm_v16f32_ty : LLVMType<v16f32>; // 16 x float def llvm_v16f32_ty : LLVMType<v16f32>; // 16 x float

7
llvm/lib/IR/Function.cpp
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@ -980,7 +980,8 @@ enum IIT_Info {
IIT_STRUCT9 = 49, IIT_STRUCT9 = 49,
IIT_V256 = 50, IIT_V256 = 50,
IIT_AMX = 51, IIT_AMX = 51,
IIT_PPCF128 = 52 IIT_PPCF128 = 52,
IIT_V3 = 53,
}; };
static void DecodeIITType(unsigned &NextElt, ArrayRef<unsigned char> Infos, static void DecodeIITType(unsigned &NextElt, ArrayRef<unsigned char> Infos,
@ -1056,6 +1057,10 @@ static void DecodeIITType(unsigned &NextElt, ArrayRef<unsigned char> Infos,
OutputTable.push_back(IITDescriptor::getVector(2, IsScalableVector)); OutputTable.push_back(IITDescriptor::getVector(2, IsScalableVector));
DecodeIITType(NextElt, Infos, Info, OutputTable); DecodeIITType(NextElt, Infos, Info, OutputTable);
return; return;
case IIT_V3:
OutputTable.push_back(IITDescriptor::getVector(3, IsScalableVector));
DecodeIITType(NextElt, Infos, Info, OutputTable);
return;
case IIT_V4: case IIT_V4:
OutputTable.push_back(IITDescriptor::getVector(4, IsScalableVector)); OutputTable.push_back(IITDescriptor::getVector(4, IsScalableVector));
DecodeIITType(NextElt, Infos, Info, OutputTable); DecodeIITType(NextElt, Infos, Info, OutputTable);

4
llvm/utils/TableGen/IntrinsicEmitter.cpp
View File

@ -250,7 +250,8 @@ enum IIT_Info {
IIT_STRUCT9 = 49, IIT_STRUCT9 = 49,
IIT_V256 = 50, IIT_V256 = 50,
IIT_AMX = 51, IIT_AMX = 51,
IIT_PPCF128 = 52 IIT_PPCF128 = 52,
IIT_V3 = 53,
}; };
static void EncodeFixedValueType(MVT::SimpleValueType VT, static void EncodeFixedValueType(MVT::SimpleValueType VT,
@ -384,6 +385,7 @@ static void EncodeFixedType(Record *R, std::vector<unsigned char> &ArgCodes,
default: PrintFatalError("unhandled vector type width in intrinsic!"); default: PrintFatalError("unhandled vector type width in intrinsic!");
case 1: Sig.push_back(IIT_V1); break; case 1: Sig.push_back(IIT_V1); break;
case 2: Sig.push_back(IIT_V2); break; case 2: Sig.push_back(IIT_V2); break;
case 3: Sig.push_back(IIT_V3); break;
case 4: Sig.push_back(IIT_V4); break; case 4: Sig.push_back(IIT_V4); break;
case 8: Sig.push_back(IIT_V8); break; case 8: Sig.push_back(IIT_V8); break;
case 16: Sig.push_back(IIT_V16); break; case 16: Sig.push_back(IIT_V16); break;