forked from OSchip/llvm-project
Add support for emitting both signed- and zero-extend loads. Fix
SimplifyAddress to handle either a 12-bit unsigned offset or the ARM +/-imm8 offsets (addressing mode 3). This enables a load followed by an integer extend to be folded into a single load. For example: ldrb r1, [r0] ldrb r1, [r0] uxtb r2, r1 => mov r3, r2 mov r3, r1 llvm-svn: 144488
This commit is contained in:
Chad Rosier
parent
4784df7161
commit
c8cfd3a8fb
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@ -148,6 +148,8 @@ class ARMFastISel : public FastISel {
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virtual bool TargetSelectInstruction(const Instruction *I);
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virtual unsigned TargetMaterializeConstant(const Constant *C);
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virtual unsigned TargetMaterializeAlloca(const AllocaInst *AI);
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virtual bool TryToFoldLoad(MachineInstr *MI, unsigned OpNo,
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const LoadInst *LI);
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#include "ARMGenFastISel.inc"
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@ -177,10 +179,12 @@ class ARMFastISel : public FastISel {
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bool isLoadTypeLegal(Type *Ty, MVT &VT);
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bool ARMEmitCmp(const Value *Src1Value, const Value *Src2Value,
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bool isZExt);
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bool ARMEmitLoad(EVT VT, unsigned &ResultReg, Address &Addr);
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bool ARMEmitLoad(EVT VT, unsigned &ResultReg, Address &Addr, bool isZExt,
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bool allocReg);
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bool ARMEmitStore(EVT VT, unsigned SrcReg, Address &Addr);
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bool ARMComputeAddress(const Value *Obj, Address &Addr);
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void ARMSimplifyAddress(Address &Addr, EVT VT);
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void ARMSimplifyAddress(Address &Addr, EVT VT, bool useAM3);
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unsigned ARMEmitIntExt(EVT SrcVT, unsigned SrcReg, EVT DestVT, bool isZExt);
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unsigned ARMMaterializeFP(const ConstantFP *CFP, EVT VT);
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unsigned ARMMaterializeInt(const Constant *C, EVT VT);
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@ -213,7 +217,7 @@ class ARMFastISel : public FastISel {
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const MachineInstrBuilder &AddOptionalDefs(const MachineInstrBuilder &MIB);
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void AddLoadStoreOperands(EVT VT, Address &Addr,
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const MachineInstrBuilder &MIB,
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unsigned Flags);
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unsigned Flags, bool useAM3);
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};
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} // end anonymous namespace
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@ -724,7 +728,7 @@ bool ARMFastISel::isLoadTypeLegal(Type *Ty, MVT &VT) {
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// If this is a type than can be sign or zero-extended to a basic operation
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// go ahead and accept it now.
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if (VT == MVT::i8 || VT == MVT::i16)
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if (VT == MVT::i1 || VT == MVT::i8 || VT == MVT::i16)
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return true;
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return false;
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@ -853,7 +857,7 @@ bool ARMFastISel::ARMComputeAddress(const Value *Obj, Address &Addr) {
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return Addr.Base.Reg != 0;
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}
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void ARMFastISel::ARMSimplifyAddress(Address &Addr, EVT VT) {
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void ARMFastISel::ARMSimplifyAddress(Address &Addr, EVT VT, bool useAM3) {
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assert(VT.isSimple() && "Non-simple types are invalid here!");
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@ -861,21 +865,18 @@ void ARMFastISel::ARMSimplifyAddress(Address &Addr, EVT VT) {
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switch (VT.getSimpleVT().SimpleTy) {
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default:
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assert(false && "Unhandled load/store type!");
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case MVT::i16:
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if (isThumb2)
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// Integer loads/stores handle 12-bit offsets.
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needsLowering = ((Addr.Offset & 0xfff) != Addr.Offset);
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else
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// ARM i16 integer loads/stores handle +/-imm8 offsets.
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// FIXME: Negative offsets require special handling.
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if (Addr.Offset > 255 || Addr.Offset < 0)
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needsLowering = true;
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break;
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case MVT::i1:
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case MVT::i8:
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case MVT::i16:
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case MVT::i32:
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// Integer loads/stores handle 12-bit offsets.
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needsLowering = ((Addr.Offset & 0xfff) != Addr.Offset);
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if (!useAM3)
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// Integer loads/stores handle 12-bit offsets.
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needsLowering = ((Addr.Offset & 0xfff) != Addr.Offset);
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else
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// ARM halfword and signed byte load/stores use +/-imm8 offsets.
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// FIXME: Negative offsets require special handling.
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needsLowering = (Addr.Offset > 255 || Addr.Offset < 0);
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break;
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case MVT::f32:
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case MVT::f64:
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@ -911,7 +912,7 @@ void ARMFastISel::ARMSimplifyAddress(Address &Addr, EVT VT) {
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void ARMFastISel::AddLoadStoreOperands(EVT VT, Address &Addr,
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const MachineInstrBuilder &MIB,
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unsigned Flags) {
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unsigned Flags, bool useAM3) {
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// addrmode5 output depends on the selection dag addressing dividing the
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// offset by 4 that it then later multiplies. Do this here as well.
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if (VT.getSimpleVT().SimpleTy == MVT::f32 ||
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@ -931,8 +932,8 @@ void ARMFastISel::AddLoadStoreOperands(EVT VT, Address &Addr,
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// Now add the rest of the operands.
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MIB.addFrameIndex(FI);
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// ARM halfword load/stores need an additional operand.
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if (!isThumb2 && VT.getSimpleVT().SimpleTy == MVT::i16) MIB.addReg(0);
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// ARM halfword and signed byte load/stores need an additional operand.
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if (useAM3) MIB.addReg(0);
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MIB.addImm(Addr.Offset);
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MIB.addMemOperand(MMO);
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@ -940,29 +941,39 @@ void ARMFastISel::AddLoadStoreOperands(EVT VT, Address &Addr,
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// Now add the rest of the operands.
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MIB.addReg(Addr.Base.Reg);
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// ARM halfword load/stores need an additional operand.
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if (!isThumb2 && VT.getSimpleVT().SimpleTy == MVT::i16) MIB.addReg(0);
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// ARM halfword and signed byte load/stores need an additional operand.
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if (useAM3) MIB.addReg(0);
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MIB.addImm(Addr.Offset);
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}
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AddOptionalDefs(MIB);
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}
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bool ARMFastISel::ARMEmitLoad(EVT VT, unsigned &ResultReg, Address &Addr) {
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bool ARMFastISel::ARMEmitLoad(EVT VT, unsigned &ResultReg, Address &Addr,
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bool isZExt = true, bool allocReg = true) {
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assert(VT.isSimple() && "Non-simple types are invalid here!");
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unsigned Opc;
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TargetRegisterClass *RC;
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bool useAM3 = false;
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TargetRegisterClass *RC;
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switch (VT.getSimpleVT().SimpleTy) {
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// This is mostly going to be Neon/vector support.
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default: return false;
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case MVT::i1:
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case MVT::i8:
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Opc = isThumb2 ? ARM::t2LDRBi12 : ARM::LDRBi12;
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if (isZExt) {
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Opc = isThumb2 ? ARM::t2LDRBi12 : ARM::LDRBi12;
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} else {
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Opc = isThumb2 ? ARM::t2LDRSBi12 : ARM::LDRSB;
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if (!isThumb2) useAM3 = true;
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}
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RC = ARM::GPRRegisterClass;
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break;
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case MVT::i16:
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Opc = isThumb2 ? ARM::t2LDRHi12 : ARM::LDRH;
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if (isZExt)
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Opc = isThumb2 ? ARM::t2LDRHi12 : ARM::LDRH;
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else
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Opc = isThumb2 ? ARM::t2LDRSHi12 : ARM::LDRSH;
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if (!isThumb2) useAM3 = true;
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RC = ARM::GPRRegisterClass;
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break;
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case MVT::i32:
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@ -979,13 +990,15 @@ bool ARMFastISel::ARMEmitLoad(EVT VT, unsigned &ResultReg, Address &Addr) {
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break;
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}
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// Simplify this down to something we can handle.
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ARMSimplifyAddress(Addr, VT);
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ARMSimplifyAddress(Addr, VT, useAM3);
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// Create the base instruction, then add the operands.
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ResultReg = createResultReg(RC);
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if (allocReg)
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ResultReg = createResultReg(RC);
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assert (ResultReg > 255 && "Expected an allocated virtual register.");
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MachineInstrBuilder MIB = BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL,
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TII.get(Opc), ResultReg);
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AddLoadStoreOperands(VT, Addr, MIB, MachineMemOperand::MOLoad);
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AddLoadStoreOperands(VT, Addr, MIB, MachineMemOperand::MOLoad, useAM3);
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return true;
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}
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@ -1011,6 +1024,7 @@ bool ARMFastISel::SelectLoad(const Instruction *I) {
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bool ARMFastISel::ARMEmitStore(EVT VT, unsigned SrcReg, Address &Addr) {
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unsigned StrOpc;
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bool useAM3 = false;
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switch (VT.getSimpleVT().SimpleTy) {
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// This is mostly going to be Neon/vector support.
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default: return false;
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@ -1028,6 +1042,7 @@ bool ARMFastISel::ARMEmitStore(EVT VT, unsigned SrcReg, Address &Addr) {
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break;
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case MVT::i16:
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StrOpc = isThumb2 ? ARM::t2STRHi12 : ARM::STRH;
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if (!isThumb2) useAM3 = true;
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break;
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case MVT::i32:
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StrOpc = isThumb2 ? ARM::t2STRi12 : ARM::STRi12;
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@ -1042,13 +1057,13 @@ bool ARMFastISel::ARMEmitStore(EVT VT, unsigned SrcReg, Address &Addr) {
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break;
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}
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// Simplify this down to something we can handle.
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ARMSimplifyAddress(Addr, VT);
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ARMSimplifyAddress(Addr, VT, useAM3);
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// Create the base instruction, then add the operands.
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MachineInstrBuilder MIB = BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL,
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TII.get(StrOpc))
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.addReg(SrcReg, getKillRegState(true));
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AddLoadStoreOperands(VT, Addr, MIB, MachineMemOperand::MOStore);
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AddLoadStoreOperands(VT, Addr, MIB, MachineMemOperand::MOStore, useAM3);
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return true;
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}
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@ -2231,8 +2246,6 @@ unsigned ARMFastISel::ARMEmitIntExt(EVT SrcVT, unsigned SrcReg, EVT DestVT,
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bool ARMFastISel::SelectIntExt(const Instruction *I) {
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// On ARM, in general, integer casts don't involve legal types; this code
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// handles promotable integers.
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// FIXME: We could save an instruction in many cases by special-casing
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// load instructions.
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Type *DestTy = I->getType();
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Value *Src = I->getOperand(0);
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Type *SrcTy = Src->getType();
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@ -2300,6 +2313,52 @@ bool ARMFastISel::TargetSelectInstruction(const Instruction *I) {
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return false;
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}
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/// TryToFoldLoad - The specified machine instr operand is a vreg, and that
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/// vreg is being provided by the specified load instruction. If possible,
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/// try to fold the load as an operand to the instruction, returning true if
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/// successful.
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bool ARMFastISel::TryToFoldLoad(MachineInstr *MI, unsigned OpNo,
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const LoadInst *LI) {
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// Verify we have a legal type before going any further.
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MVT VT;
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if (!isLoadTypeLegal(LI->getType(), VT))
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return false;
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// Combine load followed by zero- or sign-extend.
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// ldrb r1, [r0] ldrb r1, [r0]
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// uxtb r2, r1 =>
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// mov r3, r2 mov r3, r1
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bool isZExt = true;
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switch(MI->getOpcode()) {
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default: return false;
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case ARM::SXTH:
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case ARM::t2SXTH:
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isZExt = false;
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case ARM::UXTH:
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case ARM::t2UXTH:
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if (VT != MVT::i16)
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return false;
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break;
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case ARM::SXTB:
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case ARM::t2SXTB:
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isZExt = false;
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case ARM::UXTB:
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case ARM::t2UXTB:
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if (VT != MVT::i8)
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return false;
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break;
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}
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// See if we can handle this address.
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Address Addr;
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if (!ARMComputeAddress(LI->getOperand(0), Addr)) return false;
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unsigned ResultReg = MI->getOperand(0).getReg();
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if (!ARMEmitLoad(VT, ResultReg, Addr, isZExt, false))
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return false;
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MI->eraseFromParent();
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return true;
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}
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namespace llvm {
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llvm::FastISel *ARM::createFastISel(FunctionLoweringInfo &funcInfo) {
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// Completely untested on non-darwin.
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@ -0,0 +1,80 @@
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; RUN: llc < %s -O0 -fast-isel-abort -relocation-model=dynamic-no-pic -mtriple=armv7-apple-darwin | FileCheck %s --check-prefix=ARM
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; RUN: llc < %s -O0 -fast-isel-abort -relocation-model=dynamic-no-pic -mtriple=thumbv7-apple-darwin | FileCheck %s --check-prefix=THUMB
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@a = global i8 1, align 1
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@b = global i16 2, align 2
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define void @t1() nounwind uwtable ssp {
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; ARM: t1
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; ARM: ldrb
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; ARM-NOT: uxtb
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; THUMB: t1
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; THUMB: ldrb
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; THUMB-NOT: uxtb
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%1 = load i8* @a, align 1
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call void @foo1(i8 zeroext %1)
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ret void
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}
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define void @t2() nounwind uwtable ssp {
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; ARM: t2
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; ARM: ldrh
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; ARM-NOT: uxth
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; THUMB: t2
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; THUMB: ldrh
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; THUMB-NOT: uxth
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%1 = load i16* @b, align 2
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call void @foo2(i16 zeroext %1)
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ret void
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}
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declare void @foo1(i8 zeroext)
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declare void @foo2(i16 zeroext)
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define i32 @t3() nounwind uwtable ssp {
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; ARM: t3
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; ARM: ldrb
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; ARM-NOT: uxtb
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; THUMB: t3
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; THUMB: ldrb
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; THUMB-NOT: uxtb
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%1 = load i8* @a, align 1
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%2 = zext i8 %1 to i32
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ret i32 %2
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}
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define i32 @t4() nounwind uwtable ssp {
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; ARM: t4
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; ARM: ldrh
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; ARM-NOT: uxth
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; THUMB: t4
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; THUMB: ldrh
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; THUMB-NOT: uxth
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%1 = load i16* @b, align 2
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%2 = zext i16 %1 to i32
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ret i32 %2
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}
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define i32 @t5() nounwind uwtable ssp {
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; ARM: t5
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; ARM: ldrsh
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; ARM-NOT: sxth
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; THUMB: t5
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; THUMB: ldrsh
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; THUMB-NOT: sxth
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%1 = load i16* @b, align 2
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%2 = sext i16 %1 to i32
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ret i32 %2
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}
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define i32 @t6() nounwind uwtable ssp {
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; ARM: t6
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; ARM: ldrsb
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; ARM-NOT: sxtb
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; THUMB: t6
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; THUMB: ldrsb
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; THUMB-NOT: sxtb
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%1 = load i8* @a, align 2
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%2 = sext i8 %1 to i32
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ret i32 %2
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}
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