forked from OSchip/llvm-project
[X86] Remove unused intrinsic handlers. NFC
llvm-svn: 351032
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075fcc1151
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@ -21508,13 +21508,9 @@ SDValue X86TargetLowering::LowerINTRINSIC_WO_CHAIN(SDValue Op,
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}
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return DAG.getNode(IntrData->Opc0, dl, Op.getValueType(), Op.getOperand(1));
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}
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case INTR_TYPE_2OP:
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case INTR_TYPE_2OP_IMM8: {
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case INTR_TYPE_2OP: {
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SDValue Src2 = Op.getOperand(2);
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if (IntrData->Type == INTR_TYPE_2OP_IMM8)
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Src2 = DAG.getNode(ISD::TRUNCATE, dl, MVT::i8, Src2);
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// We specify 2 possible opcodes for intrinsics with rounding modes.
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// First, we check if the intrinsic may have non-default rounding mode,
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// (IntrData->Opc1 != 0), then we check the rounding mode operand.
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@ -21746,38 +21742,6 @@ SDValue X86TargetLowering::LowerINTRINSIC_WO_CHAIN(SDValue Op,
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// Swap Src1 and Src2 in the node creation
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return DAG.getNode(IntrData->Opc0, dl, VT,Src2, Src1);
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}
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case FMA_OP_MASKZ:
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case FMA_OP_MASK: {
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SDValue Src1 = Op.getOperand(1);
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SDValue Src2 = Op.getOperand(2);
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SDValue Src3 = Op.getOperand(3);
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SDValue Mask = Op.getOperand(4);
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MVT VT = Op.getSimpleValueType();
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SDValue PassThru = SDValue();
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// set PassThru element
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if (IntrData->Type == FMA_OP_MASKZ)
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PassThru = getZeroVector(VT, Subtarget, DAG, dl);
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else
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PassThru = Src1;
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// We specify 2 possible opcodes for intrinsics with rounding modes.
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// First, we check if the intrinsic may have non-default rounding mode,
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// (IntrData->Opc1 != 0), then we check the rounding mode operand.
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unsigned IntrWithRoundingModeOpcode = IntrData->Opc1;
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if (IntrWithRoundingModeOpcode != 0) {
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SDValue Rnd = Op.getOperand(5);
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if (!isRoundModeCurDirection(Rnd))
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return getVectorMaskingNode(DAG.getNode(IntrWithRoundingModeOpcode,
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dl, Op.getValueType(),
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Src1, Src2, Src3, Rnd),
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Mask, PassThru, Subtarget, DAG);
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}
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return getVectorMaskingNode(DAG.getNode(IntrData->Opc0,
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dl, Op.getValueType(),
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Src1, Src2, Src3),
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Mask, PassThru, Subtarget, DAG);
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}
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case IFMA_OP:
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// NOTE: We need to swizzle the operands to pass the multiply operands
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// first.
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@ -22,13 +22,12 @@ namespace llvm {
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enum IntrinsicType : uint16_t {
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GATHER, SCATTER, PREFETCH, RDSEED, RDRAND, RDPMC, RDTSC, XTEST, XGETBV, ADX, FPCLASSS,
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INTR_TYPE_1OP, INTR_TYPE_2OP, INTR_TYPE_3OP, INTR_TYPE_4OP,
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INTR_TYPE_2OP_IMM8, INTR_TYPE_3OP_IMM8,
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INTR_TYPE_3OP_IMM8,
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CMP_MASK_CC,CMP_MASK_SCALAR_CC, VSHIFT, COMI, COMI_RM,
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CVTPD2PS, CVTPD2PS_MASK, CVTPD2PS_RND_MASK,
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INTR_TYPE_1OP_MASK, INTR_TYPE_1OP_MASK_RM,
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INTR_TYPE_2OP_MASK, INTR_TYPE_2OP_MASK_RM,
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INTR_TYPE_3OP_MASK,
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FMA_OP_MASK, FMA_OP_MASKZ, FMA_OP_SCALAR,
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IFMA_OP, VPERM_2OP, INTR_TYPE_SCALAR_MASK,
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INTR_TYPE_SCALAR_MASK_RM, INTR_TYPE_3OP_SCALAR_MASK,
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COMPRESS_EXPAND_IN_REG,
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