forked from OSchip/llvm-project
[AArch64][GlobalISel] Fold in G_ANYEXT/G_ZEXT into TB(N)Z
This is similar to the code in getTestBitOperand in AArch64ISelLowering. Instead of implementing all of the TB(N)Z optimizations at once, this patch implements the simplest case first. The way that this is set up should make it fairly easy to add the rest as we go along. The idea here is that after determining that we can use a TB(N)Z, we can continue looking through instructions and perform further folding. In this case, when we have a G_ZEXT or G_ANYEXT where the extended bits are not used, we can fold it into the TB(N)Z. Differential Revision: https://reviews.llvm.org/D73673
This commit is contained in:
Jessica Paquette
parent
6170272ab9
commit
c8c987d310
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@ -990,6 +990,27 @@ static void changeFCMPPredToAArch64CC(CmpInst::Predicate P,
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}
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}
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}
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}
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/// Return a register which can be used as a bit to test in a TB(N)Z.
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static Register getTestBitReg(Register Reg, MachineRegisterInfo &MRI) {
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assert(Reg.isValid() && "Expected valid register!");
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while (MachineInstr *MI = getDefIgnoringCopies(Reg, MRI)) {
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unsigned Opc = MI->getOpcode();
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Register NextReg;
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// (tbz (any_ext x), b) -> (tbz x, b) if we don't use the extended bits.
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if (Opc == TargetOpcode::G_ANYEXT || Opc == TargetOpcode::G_ZEXT)
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NextReg = MI->getOperand(1).getReg();
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// Did we find something worth folding?
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if (!NextReg.isValid() || !MRI.hasOneUse(NextReg))
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break;
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// NextReg is worth folding. Keep looking.
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Reg = NextReg;
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}
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return Reg;
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}
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bool AArch64InstructionSelector::tryOptAndIntoCompareBranch(
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bool AArch64InstructionSelector::tryOptAndIntoCompareBranch(
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MachineInstr *AndInst, int64_t CmpConstant, const CmpInst::Predicate &Pred,
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MachineInstr *AndInst, int64_t CmpConstant, const CmpInst::Predicate &Pred,
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MachineBasicBlock *DstMBB, MachineIRBuilder &MIB) const {
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MachineBasicBlock *DstMBB, MachineIRBuilder &MIB) const {
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@ -1018,7 +1039,6 @@ bool AArch64InstructionSelector::tryOptAndIntoCompareBranch(
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return false;
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return false;
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MachineRegisterInfo &MRI = *MIB.getMRI();
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MachineRegisterInfo &MRI = *MIB.getMRI();
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Register TestReg = AndInst->getOperand(1).getReg();
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// Only support EQ and NE. If we have LT, then it *is* possible to fold, but
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// Only support EQ and NE. If we have LT, then it *is* possible to fold, but
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// we don't want to do this. When we have an AND and LT, we need a TST/ANDS,
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// we don't want to do this. When we have an AND and LT, we need a TST/ANDS,
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@ -1034,7 +1054,11 @@ bool AArch64InstructionSelector::tryOptAndIntoCompareBranch(
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getConstantVRegValWithLookThrough(AndInst->getOperand(2).getReg(), MRI);
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getConstantVRegValWithLookThrough(AndInst->getOperand(2).getReg(), MRI);
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if (!MaybeBit || !isPowerOf2_64(MaybeBit->Value))
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if (!MaybeBit || !isPowerOf2_64(MaybeBit->Value))
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return false;
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return false;
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// Try to optimize the TB(N)Z.
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uint64_t Bit = Log2_64(static_cast<uint64_t>(MaybeBit->Value));
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uint64_t Bit = Log2_64(static_cast<uint64_t>(MaybeBit->Value));
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Register TestReg = AndInst->getOperand(1).getReg();
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TestReg = getTestBitReg(TestReg, MRI);
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// Choose the correct TB(N)Z opcode to use.
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// Choose the correct TB(N)Z opcode to use.
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unsigned Opc = 0;
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unsigned Opc = 0;
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@ -0,0 +1,136 @@
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# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
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# RUN: llc -mtriple aarch64-unknown-unknown -run-pass=instruction-select -verify-machineinstrs %s -o - | FileCheck %s
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#
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# Check that we can continue matching when we are in a situation where we will
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# emit a TB(N)Z.
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...
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---
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name: fold_zext
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alignment: 4
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legalized: true
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regBankSelected: true
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tracksRegLiveness: true
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body: |
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; CHECK-LABEL: name: fold_zext
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; CHECK: bb.0:
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; CHECK: successors: %bb.0(0x40000000), %bb.1(0x40000000)
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; CHECK: liveins: $x0
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; CHECK: %copy:gpr32 = COPY $w0
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; CHECK: TBNZW %copy, 3, %bb.1
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; CHECK: B %bb.0
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; CHECK: bb.1:
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; CHECK: RET_ReallyLR
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bb.0:
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successors: %bb.0, %bb.1
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liveins: $x0
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%copy:gpr(s32) = COPY $w0
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%bit:gpr(s64) = G_CONSTANT i64 8
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%zero:gpr(s64) = G_CONSTANT i64 0
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%fold_me:gpr(s64) = G_ZEXT %copy(s32)
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%and:gpr(s64) = G_AND %fold_me, %bit
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%cmp:gpr(s32) = G_ICMP intpred(ne), %and(s64), %zero
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%cmp_trunc:gpr(s1) = G_TRUNC %cmp(s32)
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G_BRCOND %cmp_trunc(s1), %bb.1
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G_BR %bb.0
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bb.1:
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RET_ReallyLR
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...
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---
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name: fold_anyext
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alignment: 4
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legalized: true
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regBankSelected: true
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tracksRegLiveness: true
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body: |
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; CHECK-LABEL: name: fold_anyext
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; CHECK: bb.0:
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; CHECK: successors: %bb.0(0x40000000), %bb.1(0x40000000)
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; CHECK: liveins: $x0
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; CHECK: %copy:gpr32 = COPY $w0
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; CHECK: TBNZW %copy, 3, %bb.1
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; CHECK: B %bb.0
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; CHECK: bb.1:
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; CHECK: RET_ReallyLR
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bb.0:
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successors: %bb.0, %bb.1
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liveins: $x0
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%copy:gpr(s32) = COPY $w0
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%bit:gpr(s64) = G_CONSTANT i64 8
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%zero:gpr(s64) = G_CONSTANT i64 0
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%fold_me:gpr(s64) = G_ANYEXT %copy(s32)
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%and:gpr(s64) = G_AND %fold_me, %bit
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%cmp:gpr(s32) = G_ICMP intpred(ne), %and(s64), %zero
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%cmp_trunc:gpr(s1) = G_TRUNC %cmp(s32)
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G_BRCOND %cmp_trunc(s1), %bb.1
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G_BR %bb.0
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bb.1:
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RET_ReallyLR
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...
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---
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name: fold_multiple
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alignment: 4
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legalized: true
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regBankSelected: true
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tracksRegLiveness: true
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body: |
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; CHECK-LABEL: name: fold_multiple
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; CHECK: bb.0:
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; CHECK: successors: %bb.0(0x40000000), %bb.1(0x40000000)
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; CHECK: liveins: $h0
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; CHECK: [[SUBREG_TO_REG:%[0-9]+]]:fpr32 = SUBREG_TO_REG 0, $h0, %subreg.hsub
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; CHECK: %copy:gpr32all = COPY [[SUBREG_TO_REG]]
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; CHECK: [[COPY:%[0-9]+]]:gpr32 = COPY %copy
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; CHECK: TBNZW [[COPY]], 3, %bb.1
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; CHECK: B %bb.0
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; CHECK: bb.1:
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; CHECK: RET_ReallyLR
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bb.0:
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successors: %bb.0, %bb.1
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liveins: $h0
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%copy:gpr(s16) = COPY $h0
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%bit:gpr(s64) = G_CONSTANT i64 8
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%zero:gpr(s64) = G_CONSTANT i64 0
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%ext1:gpr(s32) = G_ZEXT %copy(s16)
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%ext2:gpr(s64) = G_ANYEXT %ext1(s32)
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%and:gpr(s64) = G_AND %ext2, %bit
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%cmp:gpr(s32) = G_ICMP intpred(ne), %and(s64), %zero
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%cmp_trunc:gpr(s1) = G_TRUNC %cmp(s32)
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G_BRCOND %cmp_trunc(s1), %bb.1
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G_BR %bb.0
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bb.1:
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RET_ReallyLR
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...
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---
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name: dont_fold_more_than_one_use
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alignment: 4
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legalized: true
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regBankSelected: true
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tracksRegLiveness: true
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body: |
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; CHECK-LABEL: name: dont_fold_more_than_one_use
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; CHECK: bb.0:
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; CHECK: successors: %bb.0(0x40000000), %bb.1(0x40000000)
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; CHECK: liveins: $x0
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; CHECK: %copy:gpr32 = COPY $w0
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; CHECK: [[SUBREG_TO_REG:%[0-9]+]]:gpr64 = SUBREG_TO_REG 0, %copy, %subreg.sub_32
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; CHECK: %zext:gpr64 = UBFMXri [[SUBREG_TO_REG]], 0, 31
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; CHECK: TBNZW %copy, 3, %bb.1
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; CHECK: B %bb.0
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; CHECK: bb.1:
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; CHECK: $x0 = COPY %zext
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; CHECK: RET_ReallyLR implicit $x0
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bb.0:
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successors: %bb.0, %bb.1
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liveins: $x0
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%copy:gpr(s32) = COPY $w0
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%bit:gpr(s64) = G_CONSTANT i64 8
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%zero:gpr(s64) = G_CONSTANT i64 0
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%zext:gpr(s64) = G_ZEXT %copy(s32)
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%and:gpr(s64) = G_AND %zext, %bit
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%cmp:gpr(s32) = G_ICMP intpred(ne), %and(s64), %zero
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%cmp_trunc:gpr(s1) = G_TRUNC %cmp(s32)
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G_BRCOND %cmp_trunc(s1), %bb.1
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G_BR %bb.0
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bb.1:
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$x0 = COPY %zext:gpr(s64)
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RET_ReallyLR implicit $x0
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