AArch64: Restrict macroop fusion heuristics to cyclone.

Even though this is just some hinting for the scheduler it doesn't make
sense to do that unless you know the target can perform the fusion.

llvm-svn: 242732
This commit is contained in:
Matthias Braun 2015-07-20 23:11:42 +00:00
parent 0058b82c02
commit c8b67e656b
1 changed files with 33 additions and 31 deletions

View File

@ -1445,38 +1445,40 @@ bool AArch64InstrInfo::shouldClusterLoads(MachineInstr *FirstLdSt,
bool AArch64InstrInfo::shouldScheduleAdjacent(MachineInstr *First,
MachineInstr *Second) const {
// Cyclone can fuse CMN, CMP, TST followed by Bcc.
unsigned SecondOpcode = Second->getOpcode();
if (SecondOpcode == AArch64::Bcc) {
switch (First->getOpcode()) {
default:
return false;
case AArch64::SUBSWri:
case AArch64::ADDSWri:
case AArch64::ANDSWri:
case AArch64::SUBSXri:
case AArch64::ADDSXri:
case AArch64::ANDSXri:
return true;
if (Subtarget.isCyclone()) {
// Cyclone can fuse CMN, CMP, TST followed by Bcc.
unsigned SecondOpcode = Second->getOpcode();
if (SecondOpcode == AArch64::Bcc) {
switch (First->getOpcode()) {
default:
return false;
case AArch64::SUBSWri:
case AArch64::ADDSWri:
case AArch64::ANDSWri:
case AArch64::SUBSXri:
case AArch64::ADDSXri:
case AArch64::ANDSXri:
return true;
}
}
}
// Cyclone B0 also supports ALU operations followed by CBZ/CBNZ.
if (SecondOpcode == AArch64::CBNZW || SecondOpcode == AArch64::CBNZX ||
SecondOpcode == AArch64::CBZW || SecondOpcode == AArch64::CBZX) {
switch (First->getOpcode()) {
default:
return false;
case AArch64::ADDWri:
case AArch64::ADDXri:
case AArch64::ANDWri:
case AArch64::ANDXri:
case AArch64::EORWri:
case AArch64::EORXri:
case AArch64::ORRWri:
case AArch64::ORRXri:
case AArch64::SUBWri:
case AArch64::SUBXri:
return true;
// Cyclone B0 also supports ALU operations followed by CBZ/CBNZ.
if (SecondOpcode == AArch64::CBNZW || SecondOpcode == AArch64::CBNZX ||
SecondOpcode == AArch64::CBZW || SecondOpcode == AArch64::CBZX) {
switch (First->getOpcode()) {
default:
return false;
case AArch64::ADDWri:
case AArch64::ADDXri:
case AArch64::ANDWri:
case AArch64::ANDXri:
case AArch64::EORWri:
case AArch64::EORXri:
case AArch64::ORRWri:
case AArch64::ORRXri:
case AArch64::SUBWri:
case AArch64::SUBXri:
return true;
}
}
}
return false;