forked from OSchip/llvm-project
AArch64: Restrict macroop fusion heuristics to cyclone.
Even though this is just some hinting for the scheduler it doesn't make sense to do that unless you know the target can perform the fusion. llvm-svn: 242732
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@ -1445,38 +1445,40 @@ bool AArch64InstrInfo::shouldClusterLoads(MachineInstr *FirstLdSt,
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bool AArch64InstrInfo::shouldScheduleAdjacent(MachineInstr *First,
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MachineInstr *Second) const {
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// Cyclone can fuse CMN, CMP, TST followed by Bcc.
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unsigned SecondOpcode = Second->getOpcode();
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if (SecondOpcode == AArch64::Bcc) {
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switch (First->getOpcode()) {
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default:
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return false;
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case AArch64::SUBSWri:
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case AArch64::ADDSWri:
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case AArch64::ANDSWri:
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case AArch64::SUBSXri:
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case AArch64::ADDSXri:
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case AArch64::ANDSXri:
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return true;
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if (Subtarget.isCyclone()) {
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// Cyclone can fuse CMN, CMP, TST followed by Bcc.
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unsigned SecondOpcode = Second->getOpcode();
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if (SecondOpcode == AArch64::Bcc) {
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switch (First->getOpcode()) {
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default:
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return false;
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case AArch64::SUBSWri:
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case AArch64::ADDSWri:
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case AArch64::ANDSWri:
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case AArch64::SUBSXri:
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case AArch64::ADDSXri:
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case AArch64::ANDSXri:
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return true;
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}
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}
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}
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// Cyclone B0 also supports ALU operations followed by CBZ/CBNZ.
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if (SecondOpcode == AArch64::CBNZW || SecondOpcode == AArch64::CBNZX ||
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SecondOpcode == AArch64::CBZW || SecondOpcode == AArch64::CBZX) {
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switch (First->getOpcode()) {
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default:
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return false;
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case AArch64::ADDWri:
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case AArch64::ADDXri:
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case AArch64::ANDWri:
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case AArch64::ANDXri:
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case AArch64::EORWri:
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case AArch64::EORXri:
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case AArch64::ORRWri:
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case AArch64::ORRXri:
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case AArch64::SUBWri:
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case AArch64::SUBXri:
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return true;
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// Cyclone B0 also supports ALU operations followed by CBZ/CBNZ.
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if (SecondOpcode == AArch64::CBNZW || SecondOpcode == AArch64::CBNZX ||
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SecondOpcode == AArch64::CBZW || SecondOpcode == AArch64::CBZX) {
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switch (First->getOpcode()) {
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default:
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return false;
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case AArch64::ADDWri:
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case AArch64::ADDXri:
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case AArch64::ANDWri:
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case AArch64::ANDXri:
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case AArch64::EORWri:
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case AArch64::EORXri:
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case AArch64::ORRWri:
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case AArch64::ORRXri:
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case AArch64::SUBWri:
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case AArch64::SUBXri:
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return true;
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}
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}
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}
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return false;
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