forked from OSchip/llvm-project
[AArch64][GlobalISel] Ensure atomic loads always get assigned GPR destinations
The default register bank selection code for G_LOAD assumes that we ought to use a FPR when the load is casted to a float/double. For atomics, this isn't true; we should always use GPRs. Without this patch, we crash in the following example: https://godbolt.org/z/MThjas441 Also make the code a little more stylistically consistent while we're here. Also test some other weird cast combinations as well. Differential Revision: https://reviews.llvm.org/D109771
This commit is contained in:
Jessica Paquette
parent
e159d3cbfc
commit
c8b3d7d6d6
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@ -15,6 +15,7 @@
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#include "AArch64InstrInfo.h"
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#include "llvm/ADT/STLExtras.h"
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#include "llvm/ADT/SmallVector.h"
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#include "llvm/CodeGen/GlobalISel/GenericMachineInstrs.h"
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#include "llvm/CodeGen/GlobalISel/RegisterBank.h"
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#include "llvm/CodeGen/GlobalISel/RegisterBankInfo.h"
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#include "llvm/CodeGen/GlobalISel/Utils.h"
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@ -751,24 +752,33 @@ AArch64RegisterBankInfo::getInstrMapping(const MachineInstr &MI) const {
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// for the greedy mode the cost of the cross bank copy will
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// offset this number.
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// FIXME: Should be derived from the scheduling model.
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if (OpRegBankIdx[0] != PMI_FirstGPR)
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if (OpRegBankIdx[0] != PMI_FirstGPR) {
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Cost = 2;
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else
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// Check if that load feeds fp instructions.
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// In that case, we want the default mapping to be on FPR
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// instead of blind map every scalar to GPR.
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for (const MachineInstr &UseMI :
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MRI.use_nodbg_instructions(MI.getOperand(0).getReg())) {
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// If we have at least one direct use in a FP instruction,
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// assume this was a floating point load in the IR.
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// If it was not, we would have had a bitcast before
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// reaching that instruction.
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// Int->FP conversion operations are also captured in onlyDefinesFP().
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if (onlyUsesFP(UseMI, MRI, TRI) || onlyDefinesFP(UseMI, MRI, TRI)) {
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OpRegBankIdx[0] = PMI_FirstFPR;
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break;
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}
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}
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break;
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}
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if (cast<GLoad>(MI).isAtomic()) {
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// Atomics always use GPR destinations. Don't refine any further.
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OpRegBankIdx[0] = PMI_FirstGPR;
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break;
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}
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// Check if that load feeds fp instructions.
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// In that case, we want the default mapping to be on FPR
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// instead of blind map every scalar to GPR.
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if (any_of(MRI.use_nodbg_instructions(MI.getOperand(0).getReg()),
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[&](const MachineInstr &UseMI) {
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// If we have at least one direct use in a FP instruction,
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// assume this was a floating point load in the IR. If it was
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// not, we would have had a bitcast before reaching that
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// instruction.
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//
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// Int->FP conversion operations are also captured in
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// onlyDefinesFP().
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return onlyUsesFP(UseMI, MRI, TRI) ||
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onlyDefinesFP(UseMI, MRI, TRI);
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}))
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OpRegBankIdx[0] = PMI_FirstFPR;
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break;
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case TargetOpcode::G_STORE:
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// Check if that store is fed by fp instructions.
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@ -2825,4 +2825,115 @@ define { i16, i1 } @cmpxchg_i16(i16* %ptr, i16 %desired, i16 %new) {
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ret { i16, i1 } %res
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}
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define internal double @bitcast_to_double(i64* %ptr) {
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; CHECK-NOLSE-LABEL: bitcast_to_double:
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; CHECK-NOLSE: ; %bb.0:
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; CHECK-NOLSE-NEXT: ldar x8, [x0]
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; CHECK-NOLSE-NEXT: fmov d0, x8
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; CHECK-NOLSE-NEXT: ret
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;
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; CHECK-LSE-O1-LABEL: bitcast_to_double:
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; CHECK-LSE-O1: ; %bb.0:
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; CHECK-LSE-O1-NEXT: ldar x8, [x0]
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; CHECK-LSE-O1-NEXT: fmov d0, x8
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; CHECK-LSE-O1-NEXT: ret
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;
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; CHECK-LSE-O0-LABEL: bitcast_to_double:
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; CHECK-LSE-O0: ; %bb.0:
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; CHECK-LSE-O0-NEXT: ldar x8, [x0]
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; CHECK-LSE-O0-NEXT: fmov d0, x8
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; CHECK-LSE-O0-NEXT: ret
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%load = load atomic i64, i64* %ptr seq_cst, align 8
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%bitcast = bitcast i64 %load to double
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ret double %bitcast
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}
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define internal float @bitcast_to_float(i32* %ptr) {
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; CHECK-NOLSE-LABEL: bitcast_to_float:
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; CHECK-NOLSE: ; %bb.0:
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; CHECK-NOLSE-NEXT: ldar w8, [x0]
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; CHECK-NOLSE-NEXT: fmov s0, w8
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; CHECK-NOLSE-NEXT: ret
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;
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; CHECK-LSE-O1-LABEL: bitcast_to_float:
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; CHECK-LSE-O1: ; %bb.0:
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; CHECK-LSE-O1-NEXT: ldar w8, [x0]
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; CHECK-LSE-O1-NEXT: fmov s0, w8
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; CHECK-LSE-O1-NEXT: ret
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;
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; CHECK-LSE-O0-LABEL: bitcast_to_float:
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; CHECK-LSE-O0: ; %bb.0:
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; CHECK-LSE-O0-NEXT: ldar w8, [x0]
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; CHECK-LSE-O0-NEXT: fmov s0, w8
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; CHECK-LSE-O0-NEXT: ret
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%load = load atomic i32, i32* %ptr seq_cst, align 8
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%bitcast = bitcast i32 %load to float
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ret float %bitcast
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}
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define internal half @bitcast_to_half(i16* %ptr) {
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; CHECK-NOLSE-LABEL: bitcast_to_half:
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; CHECK-NOLSE: ; %bb.0:
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; CHECK-NOLSE-NEXT: ldarh w8, [x0]
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; CHECK-NOLSE-NEXT: fmov s0, w8
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; CHECK-NOLSE-NEXT: ; kill: def $h0 killed $h0 killed $s0
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; CHECK-NOLSE-NEXT: ret
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;
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; CHECK-LSE-O1-LABEL: bitcast_to_half:
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; CHECK-LSE-O1: ; %bb.0:
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; CHECK-LSE-O1-NEXT: ldarh w8, [x0]
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; CHECK-LSE-O1-NEXT: fmov s0, w8
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; CHECK-LSE-O1-NEXT: ; kill: def $h0 killed $h0 killed $s0
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; CHECK-LSE-O1-NEXT: ret
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;
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; CHECK-LSE-O0-LABEL: bitcast_to_half:
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; CHECK-LSE-O0: ; %bb.0:
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; CHECK-LSE-O0-NEXT: ldarh w8, [x0]
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; CHECK-LSE-O0-NEXT: fmov s0, w8
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; CHECK-LSE-O0-NEXT: ; kill: def $h0 killed $h0 killed $s0
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; CHECK-LSE-O0-NEXT: ret
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%load = load atomic i16, i16* %ptr seq_cst, align 8
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%bitcast = bitcast i16 %load to half
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ret half %bitcast
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}
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define internal i64* @inttoptr(i64* %ptr) {
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; CHECK-NOLSE-LABEL: inttoptr:
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; CHECK-NOLSE: ; %bb.0:
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; CHECK-NOLSE-NEXT: ldar x0, [x0]
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; CHECK-NOLSE-NEXT: ret
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;
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; CHECK-LSE-O1-LABEL: inttoptr:
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; CHECK-LSE-O1: ; %bb.0:
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; CHECK-LSE-O1-NEXT: ldar x0, [x0]
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; CHECK-LSE-O1-NEXT: ret
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;
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; CHECK-LSE-O0-LABEL: inttoptr:
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; CHECK-LSE-O0: ; %bb.0:
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; CHECK-LSE-O0-NEXT: ldar x0, [x0]
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; CHECK-LSE-O0-NEXT: ret
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%load = load atomic i64, i64* %ptr seq_cst, align 8
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%bitcast = inttoptr i64 %load to i64*
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ret i64* %bitcast
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}
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define internal i64* @load_ptr(i64** %ptr) {
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; CHECK-NOLSE-LABEL: load_ptr:
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; CHECK-NOLSE: ; %bb.0:
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; CHECK-NOLSE-NEXT: ldar x0, [x0]
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; CHECK-NOLSE-NEXT: ret
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;
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; CHECK-LSE-O1-LABEL: load_ptr:
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; CHECK-LSE-O1: ; %bb.0:
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; CHECK-LSE-O1-NEXT: ldar x0, [x0]
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; CHECK-LSE-O1-NEXT: ret
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;
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; CHECK-LSE-O0-LABEL: load_ptr:
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; CHECK-LSE-O0: ; %bb.0:
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; CHECK-LSE-O0-NEXT: ldar x0, [x0]
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; CHECK-LSE-O0-NEXT: ret
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%load = load atomic i64*, i64** %ptr seq_cst, align 8
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ret i64* %load
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}
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attributes #0 = { nounwind }
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