forked from OSchip/llvm-project
[ARM,MVE] Add intrinsics for FP rounding operations.
Summary: This adds the unpredicated forms of six different MVE intrinsics which all round a vector of floating-point numbers to integer values, leaving them still in FP format, differing only in rounding mode and exception settings. Five of them map to existing target-independent intrinsics in LLVM IR, such as @llvm.trunc and @llvm.rint. The sixth, mapping to the `vrintn` instruction, is done by inventing a target-specific intrinsic. (`vrintn` behaves the same as `vrintx` in terms of the output value: the side effects on the FPSCR flags are the only difference between the two. But ACLE specifies separate user-callable intrinsics for the two, so the side effects matter enough to make sure we generate the right one of the two instructions in each case.) Reviewers: dmgreen, miyuki, MarkMurrayARM, ostannard Reviewed By: miyuki Subscribers: kristof.beyls, hiraditya, cfe-commits, llvm-commits Tags: #clang, #llvm Differential Revision: https://reviews.llvm.org/D74333
This commit is contained in:
Simon Tatham
parent
df3ed6c0fe
commit
c8b3196e54
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@ -417,6 +417,21 @@ defm : float_int_conversions<f16, u16, fptoui, uitofp>;
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defm : float_int_conversions<f32, s32, fptosi, sitofp>;
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defm : float_int_conversions<f16, s16, fptosi, sitofp>;
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let params = T.Float in {
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def vrndq: Intrinsic<Vector, (args Vector:$a),
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(IRIntBase<"trunc", [Vector]> $a)>;
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def vrndmq: Intrinsic<Vector, (args Vector:$a),
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(IRIntBase<"floor", [Vector]> $a)>;
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def vrndpq: Intrinsic<Vector, (args Vector:$a),
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(IRIntBase<"ceil", [Vector]> $a)>;
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def vrndaq: Intrinsic<Vector, (args Vector:$a),
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(IRIntBase<"round", [Vector]> $a)>;
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def vrndxq: Intrinsic<Vector, (args Vector:$a),
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(IRIntBase<"rint", [Vector]> $a)>;
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def vrndnq: Intrinsic<Vector, (args Vector:$a),
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(IRInt<"vrintn", [Vector]> $a)>;
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}
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multiclass compare_with_pred<string condname, dag arguments,
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dag cmp, string suffix> {
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// Make the predicated and unpredicated versions of a single comparison.
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@ -0,0 +1,173 @@
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// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py
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// RUN: %clang_cc1 -triple thumbv8.1m.main-arm-none-eabi -target-feature +mve.fp -mfloat-abi hard -fallow-half-arguments-and-returns -O0 -disable-O0-optnone -S -emit-llvm -o - %s | opt -S -mem2reg | FileCheck %s
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// RUN: %clang_cc1 -triple thumbv8.1m.main-arm-none-eabi -target-feature +mve.fp -mfloat-abi hard -fallow-half-arguments-and-returns -O0 -disable-O0-optnone -DPOLYMORPHIC -S -emit-llvm -o - %s | opt -S -mem2reg -sroa -early-cse | FileCheck %s
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#include <arm_mve.h>
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// CHECK-LABEL: @test_vrndaq_f16(
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// CHECK-NEXT: entry:
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// CHECK-NEXT: [[TMP0:%.*]] = call <8 x half> @llvm.round.v8f16(<8 x half> [[A:%.*]])
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// CHECK-NEXT: ret <8 x half> [[TMP0]]
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//
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float16x8_t test_vrndaq_f16(float16x8_t a)
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{
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#ifdef POLYMORPHIC
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return vrndaq(a);
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#else /* POLYMORPHIC */
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return vrndaq_f16(a);
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#endif /* POLYMORPHIC */
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}
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// CHECK-LABEL: @test_vrndaq_f32(
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// CHECK-NEXT: entry:
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// CHECK-NEXT: [[TMP0:%.*]] = call <4 x float> @llvm.round.v4f32(<4 x float> [[A:%.*]])
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// CHECK-NEXT: ret <4 x float> [[TMP0]]
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//
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float32x4_t test_vrndaq_f32(float32x4_t a)
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{
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#ifdef POLYMORPHIC
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return vrndaq(a);
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#else /* POLYMORPHIC */
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return vrndaq_f32(a);
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#endif /* POLYMORPHIC */
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}
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// CHECK-LABEL: @test_vrndmq_f16(
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// CHECK-NEXT: entry:
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// CHECK-NEXT: [[TMP0:%.*]] = call <8 x half> @llvm.floor.v8f16(<8 x half> [[A:%.*]])
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// CHECK-NEXT: ret <8 x half> [[TMP0]]
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//
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float16x8_t test_vrndmq_f16(float16x8_t a)
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{
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#ifdef POLYMORPHIC
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return vrndmq(a);
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#else /* POLYMORPHIC */
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return vrndmq_f16(a);
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#endif /* POLYMORPHIC */
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}
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// CHECK-LABEL: @test_vrndmq_f32(
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// CHECK-NEXT: entry:
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// CHECK-NEXT: [[TMP0:%.*]] = call <4 x float> @llvm.floor.v4f32(<4 x float> [[A:%.*]])
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// CHECK-NEXT: ret <4 x float> [[TMP0]]
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//
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float32x4_t test_vrndmq_f32(float32x4_t a)
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{
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#ifdef POLYMORPHIC
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return vrndmq(a);
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#else /* POLYMORPHIC */
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return vrndmq_f32(a);
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#endif /* POLYMORPHIC */
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}
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// CHECK-LABEL: @test_vrndpq_f16(
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// CHECK-NEXT: entry:
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// CHECK-NEXT: [[TMP0:%.*]] = call <8 x half> @llvm.ceil.v8f16(<8 x half> [[A:%.*]])
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// CHECK-NEXT: ret <8 x half> [[TMP0]]
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//
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float16x8_t test_vrndpq_f16(float16x8_t a)
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{
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#ifdef POLYMORPHIC
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return vrndpq(a);
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#else /* POLYMORPHIC */
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return vrndpq_f16(a);
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#endif /* POLYMORPHIC */
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}
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// CHECK-LABEL: @test_vrndpq_f32(
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// CHECK-NEXT: entry:
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// CHECK-NEXT: [[TMP0:%.*]] = call <4 x float> @llvm.ceil.v4f32(<4 x float> [[A:%.*]])
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// CHECK-NEXT: ret <4 x float> [[TMP0]]
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//
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float32x4_t test_vrndpq_f32(float32x4_t a)
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{
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#ifdef POLYMORPHIC
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return vrndpq(a);
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#else /* POLYMORPHIC */
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return vrndpq_f32(a);
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#endif /* POLYMORPHIC */
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}
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// CHECK-LABEL: @test_vrndq_f16(
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// CHECK-NEXT: entry:
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// CHECK-NEXT: [[TMP0:%.*]] = call <8 x half> @llvm.trunc.v8f16(<8 x half> [[A:%.*]])
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// CHECK-NEXT: ret <8 x half> [[TMP0]]
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//
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float16x8_t test_vrndq_f16(float16x8_t a)
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{
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#ifdef POLYMORPHIC
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return vrndq(a);
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#else /* POLYMORPHIC */
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return vrndq_f16(a);
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#endif /* POLYMORPHIC */
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}
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// CHECK-LABEL: @test_vrndq_f32(
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// CHECK-NEXT: entry:
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// CHECK-NEXT: [[TMP0:%.*]] = call <4 x float> @llvm.trunc.v4f32(<4 x float> [[A:%.*]])
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// CHECK-NEXT: ret <4 x float> [[TMP0]]
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//
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float32x4_t test_vrndq_f32(float32x4_t a)
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{
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#ifdef POLYMORPHIC
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return vrndq(a);
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#else /* POLYMORPHIC */
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return vrndq_f32(a);
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#endif /* POLYMORPHIC */
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}
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// CHECK-LABEL: @test_vrndxq_f16(
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// CHECK-NEXT: entry:
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// CHECK-NEXT: [[TMP0:%.*]] = call <8 x half> @llvm.rint.v8f16(<8 x half> [[A:%.*]])
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// CHECK-NEXT: ret <8 x half> [[TMP0]]
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//
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float16x8_t test_vrndxq_f16(float16x8_t a)
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{
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#ifdef POLYMORPHIC
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return vrndxq(a);
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#else /* POLYMORPHIC */
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return vrndxq_f16(a);
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#endif /* POLYMORPHIC */
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}
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// CHECK-LABEL: @test_vrndxq_f32(
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// CHECK-NEXT: entry:
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// CHECK-NEXT: [[TMP0:%.*]] = call <4 x float> @llvm.rint.v4f32(<4 x float> [[A:%.*]])
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// CHECK-NEXT: ret <4 x float> [[TMP0]]
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//
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float32x4_t test_vrndxq_f32(float32x4_t a)
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{
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#ifdef POLYMORPHIC
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return vrndxq(a);
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#else /* POLYMORPHIC */
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return vrndxq_f32(a);
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#endif /* POLYMORPHIC */
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}
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// CHECK-LABEL: @test_vrndnq_f16(
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// CHECK-NEXT: entry:
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// CHECK-NEXT: [[TMP0:%.*]] = call <8 x half> @llvm.arm.mve.vrintn.v8f16(<8 x half> [[A:%.*]])
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// CHECK-NEXT: ret <8 x half> [[TMP0]]
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//
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float16x8_t test_vrndnq_f16(float16x8_t a)
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{
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#ifdef POLYMORPHIC
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return vrndnq(a);
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#else /* POLYMORPHIC */
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return vrndnq_f16(a);
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#endif /* POLYMORPHIC */
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}
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// CHECK-LABEL: @test_vrndnq_f32(
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// CHECK-NEXT: entry:
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// CHECK-NEXT: [[TMP0:%.*]] = call <4 x float> @llvm.arm.mve.vrintn.v4f32(<4 x float> [[A:%.*]])
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// CHECK-NEXT: ret <4 x float> [[TMP0]]
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//
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float32x4_t test_vrndnq_f32(float32x4_t a)
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{
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#ifdef POLYMORPHIC
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return vrndnq(a);
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#else /* POLYMORPHIC */
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return vrndnq_f32(a);
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#endif /* POLYMORPHIC */
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}
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@ -1158,4 +1158,8 @@ defm int_arm_mve_vcvt_fix: MVEMXPredicated<
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[llvm_anyvector_ty /* output */], [llvm_i32_ty],
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[llvm_anyvector_ty /* input vector */, llvm_i32_ty /* scale */],
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LLVMMatchType<0>, llvm_anyvector_ty>;
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def int_arm_mve_vrintn: Intrinsic<
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[llvm_anyvector_ty], [LLVMMatchType<0>], [IntrNoMem]>;
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} // end TargetPrefix
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@ -3179,6 +3179,10 @@ let Predicates = [HasMVEFloat] in {
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(v4f32 (MVE_VRINTf32P (v4f32 MQPR:$val1)))>;
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def : Pat<(v8f16 (fceil (v8f16 MQPR:$val1))),
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(v8f16 (MVE_VRINTf16P (v8f16 MQPR:$val1)))>;
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def : Pat<(v4f32 (int_arm_mve_vrintn (v4f32 MQPR:$val1))),
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(v4f32 (MVE_VRINTf32N (v4f32 MQPR:$val1)))>;
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def : Pat<(v8f16 (int_arm_mve_vrintn (v8f16 MQPR:$val1))),
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(v8f16 (MVE_VRINTf16N (v8f16 MQPR:$val1)))>;
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}
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class MVEFloatArithNeon<string iname, string suffix, bit size,
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@ -0,0 +1,25 @@
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; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc -mtriple=thumbv8.1m.main -mattr=+mve.fp -verify-machineinstrs -o - %s | FileCheck %s
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define arm_aapcs_vfpcc <8 x half> @test_vrndnq_f16(<8 x half> %a) {
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; CHECK-LABEL: test_vrndnq_f16:
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; CHECK: @ %bb.0: @ %entry
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; CHECK-NEXT: vrintn.f16 q0, q0
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; CHECK-NEXT: bx lr
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entry:
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%0 = tail call <8 x half> @llvm.arm.mve.vrintn.v8f16(<8 x half> %a)
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ret <8 x half> %0
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}
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define arm_aapcs_vfpcc <4 x float> @test_vrndnq_f32(<4 x float> %a) {
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; CHECK-LABEL: test_vrndnq_f32:
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; CHECK: @ %bb.0: @ %entry
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; CHECK-NEXT: vrintn.f32 q0, q0
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; CHECK-NEXT: bx lr
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entry:
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%0 = tail call <4 x float> @llvm.arm.mve.vrintn.v4f32(<4 x float> %a)
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ret <4 x float> %0
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}
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declare <8 x half> @llvm.arm.mve.vrintn.v8f16(<8 x half>)
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declare <4 x float> @llvm.arm.mve.vrintn.v4f32(<4 x float>)
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