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[CodeGen] ArrayRef'ize cond/pred in various TII APIs. NFC. 

llvm-svn: 239553
This commit is contained in:
Ahmed Bougacha 2015-06-11 19:30:37 +00:00
parent 7c6e6e49cc
commit c88bf54366
30 changed files with 94 additions and 126 deletions
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13
llvm/include/llvm/Target/TargetInstrInfo.h
View File

@ -405,7 +405,7 @@ public:
/// merging needs to be disabled. /// merging needs to be disabled.
virtual unsigned InsertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB, virtual unsigned InsertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB,
MachineBasicBlock *FBB, MachineBasicBlock *FBB,
const SmallVectorImpl<MachineOperand> &Cond, ArrayRef<MachineOperand> Cond,
DebugLoc DL) const { DebugLoc DL) const {
llvm_unreachable("Target didn't implement TargetInstrInfo::InsertBranch!"); llvm_unreachable("Target didn't implement TargetInstrInfo::InsertBranch!");
} }
@ -530,7 +530,7 @@ public:
/// @param TrueCycles Latency from TrueReg to select output. /// @param TrueCycles Latency from TrueReg to select output.
/// @param FalseCycles Latency from FalseReg to select output. /// @param FalseCycles Latency from FalseReg to select output.
virtual bool canInsertSelect(const MachineBasicBlock &MBB, virtual bool canInsertSelect(const MachineBasicBlock &MBB,
const SmallVectorImpl<MachineOperand> &Cond, ArrayRef<MachineOperand> Cond,
unsigned TrueReg, unsigned FalseReg, unsigned TrueReg, unsigned FalseReg,
int &CondCycles, int &CondCycles,
int &TrueCycles, int &FalseCycles) const { int &TrueCycles, int &FalseCycles) const {
@ -554,8 +554,7 @@ public:
/// @param FalseReg Virtual register to copy when Cons is false. /// @param FalseReg Virtual register to copy when Cons is false.
virtual void insertSelect(MachineBasicBlock &MBB, virtual void insertSelect(MachineBasicBlock &MBB,
MachineBasicBlock::iterator I, DebugLoc DL, MachineBasicBlock::iterator I, DebugLoc DL,
unsigned DstReg, unsigned DstReg, ArrayRef<MachineOperand> Cond,
const SmallVectorImpl<MachineOperand> &Cond,
unsigned TrueReg, unsigned FalseReg) const { unsigned TrueReg, unsigned FalseReg) const {
llvm_unreachable("Target didn't implement TargetInstrInfo::insertSelect!"); llvm_unreachable("Target didn't implement TargetInstrInfo::insertSelect!");
} }
@ -878,13 +877,13 @@ public:
/// It returns true if the operation was successful. /// It returns true if the operation was successful.
virtual virtual
bool PredicateInstruction(MachineInstr *MI, bool PredicateInstruction(MachineInstr *MI,
const SmallVectorImpl<MachineOperand> &Pred) const; ArrayRef<MachineOperand> Pred) const;
/// Returns true if the first specified predicate /// Returns true if the first specified predicate
/// subsumes the second, e.g. GE subsumes GT. /// subsumes the second, e.g. GE subsumes GT.
virtual virtual
bool SubsumesPredicate(const SmallVectorImpl<MachineOperand> &Pred1, bool SubsumesPredicate(ArrayRef<MachineOperand> Pred1,
const SmallVectorImpl<MachineOperand> &Pred2) const { ArrayRef<MachineOperand> Pred2) const {
return false; return false;
} }

5
llvm/lib/CodeGen/TargetInstrInfo.cpp
View File

@ -219,9 +219,8 @@ TargetInstrInfo::isUnpredicatedTerminator(const MachineInstr *MI) const {
return !isPredicated(MI); return !isPredicated(MI);
} }
bool TargetInstrInfo::PredicateInstruction(
bool TargetInstrInfo::PredicateInstruction(MachineInstr *MI, MachineInstr *MI, ArrayRef<MachineOperand> Pred) const {
const SmallVectorImpl<MachineOperand> &Pred) const {
bool MadeChange = false; bool MadeChange = false;
assert(!MI->isBundle() && assert(!MI->isBundle() &&

8
llvm/lib/Target/AArch64/AArch64InstrInfo.cpp
View File

@ -255,7 +255,7 @@ unsigned AArch64InstrInfo::RemoveBranch(MachineBasicBlock &MBB) const {
void AArch64InstrInfo::instantiateCondBranch( void AArch64InstrInfo::instantiateCondBranch(
MachineBasicBlock &MBB, DebugLoc DL, MachineBasicBlock *TBB, MachineBasicBlock &MBB, DebugLoc DL, MachineBasicBlock *TBB,
const SmallVectorImpl<MachineOperand> &Cond) const { ArrayRef<MachineOperand> Cond) const {
if (Cond[0].getImm() != -1) { if (Cond[0].getImm() != -1) {
// Regular Bcc // Regular Bcc
BuildMI(&MBB, DL, get(AArch64::Bcc)).addImm(Cond[0].getImm()).addMBB(TBB); BuildMI(&MBB, DL, get(AArch64::Bcc)).addImm(Cond[0].getImm()).addMBB(TBB);
@ -272,7 +272,7 @@ void AArch64InstrInfo::instantiateCondBranch(
unsigned AArch64InstrInfo::InsertBranch( unsigned AArch64InstrInfo::InsertBranch(
MachineBasicBlock &MBB, MachineBasicBlock *TBB, MachineBasicBlock *FBB, MachineBasicBlock &MBB, MachineBasicBlock *TBB, MachineBasicBlock *FBB,
const SmallVectorImpl<MachineOperand> &Cond, DebugLoc DL) const { ArrayRef<MachineOperand> Cond, DebugLoc DL) const {
// Shouldn't be a fall through. // Shouldn't be a fall through.
assert(TBB && "InsertBranch must not be told to insert a fallthrough"); assert(TBB && "InsertBranch must not be told to insert a fallthrough");
@ -369,7 +369,7 @@ static unsigned canFoldIntoCSel(const MachineRegisterInfo &MRI, unsigned VReg,
} }
bool AArch64InstrInfo::canInsertSelect( bool AArch64InstrInfo::canInsertSelect(
const MachineBasicBlock &MBB, const SmallVectorImpl<MachineOperand> &Cond, const MachineBasicBlock &MBB, ArrayRef<MachineOperand> Cond,
unsigned TrueReg, unsigned FalseReg, int &CondCycles, int &TrueCycles, unsigned TrueReg, unsigned FalseReg, int &CondCycles, int &TrueCycles,
int &FalseCycles) const { int &FalseCycles) const {
// Check register classes. // Check register classes.
@ -412,7 +412,7 @@ bool AArch64InstrInfo::canInsertSelect(
void AArch64InstrInfo::insertSelect(MachineBasicBlock &MBB, void AArch64InstrInfo::insertSelect(MachineBasicBlock &MBB,
MachineBasicBlock::iterator I, DebugLoc DL, MachineBasicBlock::iterator I, DebugLoc DL,
unsigned DstReg, unsigned DstReg,
const SmallVectorImpl<MachineOperand> &Cond, ArrayRef<MachineOperand> Cond,
unsigned TrueReg, unsigned FalseReg) const { unsigned TrueReg, unsigned FalseReg) const {
MachineRegisterInfo &MRI = MBB.getParent()->getRegInfo(); MachineRegisterInfo &MRI = MBB.getParent()->getRegInfo();

13
llvm/lib/Target/AArch64/AArch64InstrInfo.h
View File

@ -140,17 +140,14 @@ public:
bool AllowModify = false) const override; bool AllowModify = false) const override;
unsigned RemoveBranch(MachineBasicBlock &MBB) const override; unsigned RemoveBranch(MachineBasicBlock &MBB) const override;
unsigned InsertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB, unsigned InsertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB,
MachineBasicBlock *FBB, MachineBasicBlock *FBB, ArrayRef<MachineOperand> Cond,
const SmallVectorImpl<MachineOperand> &Cond,
DebugLoc DL) const override; DebugLoc DL) const override;
bool bool
ReverseBranchCondition(SmallVectorImpl<MachineOperand> &Cond) const override; ReverseBranchCondition(SmallVectorImpl<MachineOperand> &Cond) const override;
bool canInsertSelect(const MachineBasicBlock &, bool canInsertSelect(const MachineBasicBlock &, ArrayRef<MachineOperand> Cond,
const SmallVectorImpl<MachineOperand> &Cond, unsigned, unsigned, unsigned, int &, int &, int &) const override;
unsigned, int &, int &, int &) const override;
void insertSelect(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, void insertSelect(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI,
DebugLoc DL, unsigned DstReg, DebugLoc DL, unsigned DstReg, ArrayRef<MachineOperand> Cond,
const SmallVectorImpl<MachineOperand> &Cond,
unsigned TrueReg, unsigned FalseReg) const override; unsigned TrueReg, unsigned FalseReg) const override;
void getNoopForMachoTarget(MCInst &NopInst) const override; void getNoopForMachoTarget(MCInst &NopInst) const override;
@ -189,7 +186,7 @@ public:
private: private:
void instantiateCondBranch(MachineBasicBlock &MBB, DebugLoc DL, void instantiateCondBranch(MachineBasicBlock &MBB, DebugLoc DL,
MachineBasicBlock *TBB, MachineBasicBlock *TBB,
const SmallVectorImpl<MachineOperand> &Cond) const; ArrayRef<MachineOperand> Cond) const;
}; };
/// emitFrameOffset - Emit instructions as needed to set DestReg to SrcReg /// emitFrameOffset - Emit instructions as needed to set DestReg to SrcReg

10
llvm/lib/Target/ARM/ARMBaseInstrInfo.cpp
View File

@ -396,7 +396,7 @@ unsigned ARMBaseInstrInfo::RemoveBranch(MachineBasicBlock &MBB) const {
unsigned unsigned
ARMBaseInstrInfo::InsertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB, ARMBaseInstrInfo::InsertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB,
MachineBasicBlock *FBB, MachineBasicBlock *FBB,
const SmallVectorImpl<MachineOperand> &Cond, ArrayRef<MachineOperand> Cond,
DebugLoc DL) const { DebugLoc DL) const {
ARMFunctionInfo *AFI = MBB.getParent()->getInfo<ARMFunctionInfo>(); ARMFunctionInfo *AFI = MBB.getParent()->getInfo<ARMFunctionInfo>();
int BOpc = !AFI->isThumbFunction() int BOpc = !AFI->isThumbFunction()
@ -458,8 +458,7 @@ bool ARMBaseInstrInfo::isPredicated(const MachineInstr *MI) const {
} }
bool ARMBaseInstrInfo:: bool ARMBaseInstrInfo::
PredicateInstruction(MachineInstr *MI, PredicateInstruction(MachineInstr *MI, ArrayRef<MachineOperand> Pred) const {
const SmallVectorImpl<MachineOperand> &Pred) const {
unsigned Opc = MI->getOpcode(); unsigned Opc = MI->getOpcode();
if (isUncondBranchOpcode(Opc)) { if (isUncondBranchOpcode(Opc)) {
MI->setDesc(get(getMatchingCondBranchOpcode(Opc))); MI->setDesc(get(getMatchingCondBranchOpcode(Opc)));
@ -479,9 +478,8 @@ PredicateInstruction(MachineInstr *MI,
return false; return false;
} }
bool ARMBaseInstrInfo:: bool ARMBaseInstrInfo::SubsumesPredicate(ArrayRef<MachineOperand> Pred1,
SubsumesPredicate(const SmallVectorImpl<MachineOperand> &Pred1, ArrayRef<MachineOperand> Pred2) const {
const SmallVectorImpl<MachineOperand> &Pred2) const {
if (Pred1.size() > 2 || Pred2.size() > 2) if (Pred1.size() > 2 || Pred2.size() > 2)
return false; return false;

9
llvm/lib/Target/ARM/ARMBaseInstrInfo.h
View File

@ -116,8 +116,7 @@ public:
bool AllowModify = false) const override; bool AllowModify = false) const override;
unsigned RemoveBranch(MachineBasicBlock &MBB) const override; unsigned RemoveBranch(MachineBasicBlock &MBB) const override;
unsigned InsertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB, unsigned InsertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB,
MachineBasicBlock *FBB, MachineBasicBlock *FBB, ArrayRef<MachineOperand> Cond,
const SmallVectorImpl<MachineOperand> &Cond,
DebugLoc DL) const override; DebugLoc DL) const override;
bool bool
@ -133,10 +132,10 @@ public:
} }
bool PredicateInstruction(MachineInstr *MI, bool PredicateInstruction(MachineInstr *MI,
const SmallVectorImpl<MachineOperand> &Pred) const override; ArrayRef<MachineOperand> Pred) const override;
bool SubsumesPredicate(const SmallVectorImpl<MachineOperand> &Pred1, bool SubsumesPredicate(ArrayRef<MachineOperand> Pred1,
const SmallVectorImpl<MachineOperand> &Pred2) const override; ArrayRef<MachineOperand> Pred2) const override;
bool DefinesPredicate(MachineInstr *MI, bool DefinesPredicate(MachineInstr *MI,
std::vector<MachineOperand> &Pred) const override; std::vector<MachineOperand> &Pred) const override;

2
llvm/lib/Target/BPF/BPFInstrInfo.cpp
View File

@ -133,7 +133,7 @@ bool BPFInstrInfo::AnalyzeBranch(MachineBasicBlock &MBB,
unsigned BPFInstrInfo::InsertBranch(MachineBasicBlock &MBB, unsigned BPFInstrInfo::InsertBranch(MachineBasicBlock &MBB,
MachineBasicBlock *TBB, MachineBasicBlock *TBB,
MachineBasicBlock *FBB, MachineBasicBlock *FBB,
const SmallVectorImpl<MachineOperand> &Cond, ArrayRef<MachineOperand> Cond,
DebugLoc DL) const { DebugLoc DL) const {
// Shouldn't be a fall through. // Shouldn't be a fall through.
assert(TBB && "InsertBranch must not be told to insert a fallthrough"); assert(TBB && "InsertBranch must not be told to insert a fallthrough");

3
llvm/lib/Target/BPF/BPFInstrInfo.h
View File

@ -51,8 +51,7 @@ public:
unsigned RemoveBranch(MachineBasicBlock &MBB) const override; unsigned RemoveBranch(MachineBasicBlock &MBB) const override;
unsigned InsertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB, unsigned InsertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB,
MachineBasicBlock *FBB, MachineBasicBlock *FBB, ArrayRef<MachineOperand> Cond,
const SmallVectorImpl<MachineOperand> &Cond,
DebugLoc DL) const override; DebugLoc DL) const override;
}; };
} }

13
llvm/lib/Target/Hexagon/HexagonInstrInfo.cpp
View File

@ -159,7 +159,7 @@ findLoopInstr(MachineBasicBlock *BB, int EndLoopOp,
unsigned HexagonInstrInfo::InsertBranch( unsigned HexagonInstrInfo::InsertBranch(
MachineBasicBlock &MBB,MachineBasicBlock *TBB, MachineBasicBlock *FBB, MachineBasicBlock &MBB,MachineBasicBlock *TBB, MachineBasicBlock *FBB,
const SmallVectorImpl<MachineOperand> &Cond, DebugLoc DL) const { ArrayRef<MachineOperand> Cond, DebugLoc DL) const {
Opcode_t BOpc = Hexagon::J2_jump; Opcode_t BOpc = Hexagon::J2_jump;
Opcode_t BccOpc = Hexagon::J2_jumpt; Opcode_t BccOpc = Hexagon::J2_jumpt;
@ -1013,7 +1013,7 @@ int HexagonInstrInfo::getCondOpcode(int Opc, bool invertPredicate) const {
bool HexagonInstrInfo:: bool HexagonInstrInfo::
PredicateInstruction(MachineInstr *MI, PredicateInstruction(MachineInstr *MI,
const SmallVectorImpl<MachineOperand> &Cond) const { ArrayRef<MachineOperand> Cond) const {
if (Cond.empty() || isEndLoopN(Cond[0].getImm())) { if (Cond.empty() || isEndLoopN(Cond[0].getImm())) {
DEBUG(dbgs() << "\nCannot predicate:"; MI->dump();); DEBUG(dbgs() << "\nCannot predicate:"; MI->dump(););
return false; return false;
@ -1162,8 +1162,8 @@ HexagonInstrInfo::DefinesPredicate(MachineInstr *MI,
bool bool
HexagonInstrInfo:: HexagonInstrInfo::
SubsumesPredicate(const SmallVectorImpl<MachineOperand> &Pred1, SubsumesPredicate(ArrayRef<MachineOperand> Pred1,
const SmallVectorImpl<MachineOperand> &Pred2) const { ArrayRef<MachineOperand> Pred2) const {
// TODO: Fix this // TODO: Fix this
return false; return false;
} }
@ -1982,8 +1982,7 @@ bool HexagonInstrInfo::PredOpcodeHasJMP_c(Opcode_t Opcode) const {
(Opcode == Hexagon::J2_jumpf); (Opcode == Hexagon::J2_jumpf);
} }
bool HexagonInstrInfo::predOpcodeHasNot( bool HexagonInstrInfo::predOpcodeHasNot(ArrayRef<MachineOperand> Cond) const {
const SmallVectorImpl<MachineOperand> &Cond) const {
if (Cond.empty() || !isPredicated(Cond[0].getImm())) if (Cond.empty() || !isPredicated(Cond[0].getImm()))
return false; return false;
return !isPredicatedTrue(Cond[0].getImm()); return !isPredicatedTrue(Cond[0].getImm());
@ -1994,7 +1993,7 @@ bool HexagonInstrInfo::isEndLoopN(Opcode_t Opcode) const {
Opcode == Hexagon::ENDLOOP1); Opcode == Hexagon::ENDLOOP1);
} }
bool HexagonInstrInfo::getPredReg(const SmallVectorImpl<MachineOperand> &Cond, bool HexagonInstrInfo::getPredReg(ArrayRef<MachineOperand> Cond,
unsigned &PredReg, unsigned &PredRegPos, unsigned &PredReg, unsigned &PredRegPos,
unsigned &PredRegFlags) const { unsigned &PredRegFlags) const {
if (Cond.empty()) if (Cond.empty())

16
llvm/lib/Target/Hexagon/HexagonInstrInfo.h
View File

@ -69,8 +69,7 @@ public:
unsigned RemoveBranch(MachineBasicBlock &MBB) const override; unsigned RemoveBranch(MachineBasicBlock &MBB) const override;
unsigned InsertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB, unsigned InsertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB,
MachineBasicBlock *FBB, MachineBasicBlock *FBB, ArrayRef<MachineOperand> Cond,
const SmallVectorImpl<MachineOperand> &Cond,
DebugLoc DL) const override; DebugLoc DL) const override;
bool analyzeCompare(const MachineInstr *MI, bool analyzeCompare(const MachineInstr *MI,
@ -129,7 +128,7 @@ public:
bool isBranch(const MachineInstr *MI) const; bool isBranch(const MachineInstr *MI) const;
bool isPredicable(MachineInstr *MI) const override; bool isPredicable(MachineInstr *MI) const override;
bool PredicateInstruction(MachineInstr *MI, bool PredicateInstruction(MachineInstr *MI,
const SmallVectorImpl<MachineOperand> &Cond) const override; ArrayRef<MachineOperand> Cond) const override;
bool isProfitableToIfCvt(MachineBasicBlock &MBB, unsigned NumCycles, bool isProfitableToIfCvt(MachineBasicBlock &MBB, unsigned NumCycles,
unsigned ExtraPredCycles, unsigned ExtraPredCycles,
@ -149,8 +148,8 @@ public:
bool isPredicatedNew(unsigned Opcode) const; bool isPredicatedNew(unsigned Opcode) const;
bool DefinesPredicate(MachineInstr *MI, bool DefinesPredicate(MachineInstr *MI,
std::vector<MachineOperand> &Pred) const override; std::vector<MachineOperand> &Pred) const override;
bool SubsumesPredicate(const SmallVectorImpl<MachineOperand> &Pred1, bool SubsumesPredicate(ArrayRef<MachineOperand> Pred1,
const SmallVectorImpl<MachineOperand> &Pred2) const override; ArrayRef<MachineOperand> Pred2) const override;
bool bool
ReverseBranchCondition(SmallVectorImpl<MachineOperand> &Cond) const override; ReverseBranchCondition(SmallVectorImpl<MachineOperand> &Cond) const override;
@ -222,11 +221,10 @@ public:
bool NonExtEquivalentExists (const MachineInstr *MI) const; bool NonExtEquivalentExists (const MachineInstr *MI) const;
short getNonExtOpcode(const MachineInstr *MI) const; short getNonExtOpcode(const MachineInstr *MI) const;
bool PredOpcodeHasJMP_c(Opcode_t Opcode) const; bool PredOpcodeHasJMP_c(Opcode_t Opcode) const;
bool predOpcodeHasNot(const SmallVectorImpl<MachineOperand> &Cond) const; bool predOpcodeHasNot(ArrayRef<MachineOperand> Cond) const;
bool isEndLoopN(Opcode_t Opcode) const; bool isEndLoopN(Opcode_t Opcode) const;
bool getPredReg(const SmallVectorImpl<MachineOperand> &Cond, bool getPredReg(ArrayRef<MachineOperand> Cond, unsigned &PredReg,
unsigned &PredReg, unsigned &PredRegPos, unsigned &PredRegPos, unsigned &PredRegFlags) const;
unsigned &PredRegFlags) const;
int getCondOpcode(int Opc, bool sense) const; int getCondOpcode(int Opc, bool sense) const;
}; };

2
llvm/lib/Target/MSP430/MSP430InstrInfo.cpp
View File

@ -262,7 +262,7 @@ bool MSP430InstrInfo::AnalyzeBranch(MachineBasicBlock &MBB,
unsigned unsigned
MSP430InstrInfo::InsertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB, MSP430InstrInfo::InsertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB,
MachineBasicBlock *FBB, MachineBasicBlock *FBB,
const SmallVectorImpl<MachineOperand> &Cond, ArrayRef<MachineOperand> Cond,
DebugLoc DL) const { DebugLoc DL) const {
// Shouldn't be a fall through. // Shouldn't be a fall through.
assert(TBB && "InsertBranch must not be told to insert a fallthrough"); assert(TBB && "InsertBranch must not be told to insert a fallthrough");

3
llvm/lib/Target/MSP430/MSP430InstrInfo.h
View File

@ -82,8 +82,7 @@ public:
unsigned RemoveBranch(MachineBasicBlock &MBB) const override; unsigned RemoveBranch(MachineBasicBlock &MBB) const override;
unsigned InsertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB, unsigned InsertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB,
MachineBasicBlock *FBB, MachineBasicBlock *FBB, ArrayRef<MachineOperand> Cond,
const SmallVectorImpl<MachineOperand> &Cond,
DebugLoc DL) const override; DebugLoc DL) const override;
}; };

5
llvm/lib/Target/Mips/MipsInstrInfo.cpp
View File

@ -96,8 +96,7 @@ bool MipsInstrInfo::AnalyzeBranch(MachineBasicBlock &MBB,
void void
MipsInstrInfo::BuildCondBr(MachineBasicBlock &MBB, MachineBasicBlock *TBB, MipsInstrInfo::BuildCondBr(MachineBasicBlock &MBB, MachineBasicBlock *TBB,
DebugLoc DL, DebugLoc DL, ArrayRef<MachineOperand> Cond) const {
const SmallVectorImpl<MachineOperand> &Cond) const {
unsigned Opc = Cond[0].getImm(); unsigned Opc = Cond[0].getImm();
const MCInstrDesc &MCID = get(Opc); const MCInstrDesc &MCID = get(Opc);
MachineInstrBuilder MIB = BuildMI(&MBB, DL, MCID); MachineInstrBuilder MIB = BuildMI(&MBB, DL, MCID);
@ -115,7 +114,7 @@ MipsInstrInfo::BuildCondBr(MachineBasicBlock &MBB, MachineBasicBlock *TBB,
unsigned MipsInstrInfo::InsertBranch( unsigned MipsInstrInfo::InsertBranch(
MachineBasicBlock &MBB, MachineBasicBlock *TBB, MachineBasicBlock *FBB, MachineBasicBlock &MBB, MachineBasicBlock *TBB, MachineBasicBlock *FBB,
const SmallVectorImpl<MachineOperand> &Cond, DebugLoc DL) const { ArrayRef<MachineOperand> Cond, DebugLoc DL) const {
// Shouldn't be a fall through. // Shouldn't be a fall through.
assert(TBB && "InsertBranch must not be told to insert a fallthrough"); assert(TBB && "InsertBranch must not be told to insert a fallthrough");

5
llvm/lib/Target/Mips/MipsInstrInfo.h
View File

@ -59,8 +59,7 @@ public:
unsigned RemoveBranch(MachineBasicBlock &MBB) const override; unsigned RemoveBranch(MachineBasicBlock &MBB) const override;
unsigned InsertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB, unsigned InsertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB,
MachineBasicBlock *FBB, MachineBasicBlock *FBB, ArrayRef<MachineOperand> Cond,
const SmallVectorImpl<MachineOperand> &Cond,
DebugLoc DL) const override; DebugLoc DL) const override;
bool bool
@ -140,7 +139,7 @@ private:
SmallVectorImpl<MachineOperand> &Cond) const; SmallVectorImpl<MachineOperand> &Cond) const;
void BuildCondBr(MachineBasicBlock &MBB, MachineBasicBlock *TBB, DebugLoc DL, void BuildCondBr(MachineBasicBlock &MBB, MachineBasicBlock *TBB, DebugLoc DL,
const SmallVectorImpl<MachineOperand>& Cond) const; ArrayRef<MachineOperand> Cond) const;
}; };
/// Create MipsInstrInfo objects. /// Create MipsInstrInfo objects.

2
llvm/lib/Target/NVPTX/NVPTXInstrInfo.cpp
View File

@ -248,7 +248,7 @@ unsigned NVPTXInstrInfo::RemoveBranch(MachineBasicBlock &MBB) const {
unsigned NVPTXInstrInfo::InsertBranch( unsigned NVPTXInstrInfo::InsertBranch(
MachineBasicBlock &MBB, MachineBasicBlock *TBB, MachineBasicBlock *FBB, MachineBasicBlock &MBB, MachineBasicBlock *TBB, MachineBasicBlock *FBB,
const SmallVectorImpl<MachineOperand> &Cond, DebugLoc DL) const { ArrayRef<MachineOperand> Cond, DebugLoc DL) const {
// Shouldn't be a fall through. // Shouldn't be a fall through.
assert(TBB && "InsertBranch must not be told to insert a fallthrough"); assert(TBB && "InsertBranch must not be told to insert a fallthrough");
assert((Cond.size() == 1 || Cond.size() == 0) && assert((Cond.size() == 1 || Cond.size() == 0) &&

2
llvm/lib/Target/NVPTX/NVPTXInstrInfo.h
View File

@ -66,7 +66,7 @@ public:
unsigned RemoveBranch(MachineBasicBlock &MBB) const override; unsigned RemoveBranch(MachineBasicBlock &MBB) const override;
unsigned InsertBranch( unsigned InsertBranch(
MachineBasicBlock &MBB, MachineBasicBlock *TBB, MachineBasicBlock *FBB, MachineBasicBlock &MBB, MachineBasicBlock *TBB, MachineBasicBlock *FBB,
const SmallVectorImpl<MachineOperand> &Cond, DebugLoc DL) const override; ArrayRef<MachineOperand> Cond, DebugLoc DL) const override;
unsigned getLdStCodeAddrSpace(const MachineInstr &MI) const { unsigned getLdStCodeAddrSpace(const MachineInstr &MI) const {
return MI.getOperand(2).getImm(); return MI.getOperand(2).getImm();
} }

17
llvm/lib/Target/PowerPC/PPCInstrInfo.cpp
View File

@ -548,7 +548,7 @@ unsigned PPCInstrInfo::RemoveBranch(MachineBasicBlock &MBB) const {
unsigned unsigned
PPCInstrInfo::InsertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB, PPCInstrInfo::InsertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB,
MachineBasicBlock *FBB, MachineBasicBlock *FBB,
const SmallVectorImpl<MachineOperand> &Cond, ArrayRef<MachineOperand> Cond,
DebugLoc DL) const { DebugLoc DL) const {
// Shouldn't be a fall through. // Shouldn't be a fall through.
assert(TBB && "InsertBranch must not be told to insert a fallthrough"); assert(TBB && "InsertBranch must not be told to insert a fallthrough");
@ -593,7 +593,7 @@ PPCInstrInfo::InsertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB,
// Select analysis. // Select analysis.
bool PPCInstrInfo::canInsertSelect(const MachineBasicBlock &MBB, bool PPCInstrInfo::canInsertSelect(const MachineBasicBlock &MBB,
const SmallVectorImpl<MachineOperand> &Cond, ArrayRef<MachineOperand> Cond,
unsigned TrueReg, unsigned FalseReg, unsigned TrueReg, unsigned FalseReg,
int &CondCycles, int &TrueCycles, int &FalseCycles) const { int &CondCycles, int &TrueCycles, int &FalseCycles) const {
if (!Subtarget.hasISEL()) if (!Subtarget.hasISEL())
@ -634,8 +634,7 @@ bool PPCInstrInfo::canInsertSelect(const MachineBasicBlock &MBB,
void PPCInstrInfo::insertSelect(MachineBasicBlock &MBB, void PPCInstrInfo::insertSelect(MachineBasicBlock &MBB,
MachineBasicBlock::iterator MI, DebugLoc dl, MachineBasicBlock::iterator MI, DebugLoc dl,
unsigned DestReg, unsigned DestReg, ArrayRef<MachineOperand> Cond,
const SmallVectorImpl<MachineOperand> &Cond,
unsigned TrueReg, unsigned FalseReg) const { unsigned TrueReg, unsigned FalseReg) const {
assert(Cond.size() == 2 && assert(Cond.size() == 2 &&
"PPC branch conditions have two components!"); "PPC branch conditions have two components!");
@ -1213,9 +1212,8 @@ bool PPCInstrInfo::isUnpredicatedTerminator(const MachineInstr *MI) const {
return !isPredicated(MI); return !isPredicated(MI);
} }
bool PPCInstrInfo::PredicateInstruction( bool PPCInstrInfo::PredicateInstruction(MachineInstr *MI,
MachineInstr *MI, ArrayRef<MachineOperand> Pred) const {
const SmallVectorImpl<MachineOperand> &Pred) const {
unsigned OpC = MI->getOpcode(); unsigned OpC = MI->getOpcode();
if (OpC == PPC::BLR || OpC == PPC::BLR8) { if (OpC == PPC::BLR || OpC == PPC::BLR8) {
if (Pred[1].getReg() == PPC::CTR8 || Pred[1].getReg() == PPC::CTR) { if (Pred[1].getReg() == PPC::CTR8 || Pred[1].getReg() == PPC::CTR) {
@ -1306,9 +1304,8 @@ bool PPCInstrInfo::PredicateInstruction(
return false; return false;
} }
bool PPCInstrInfo::SubsumesPredicate( bool PPCInstrInfo::SubsumesPredicate(ArrayRef<MachineOperand> Pred1,
const SmallVectorImpl<MachineOperand> &Pred1, ArrayRef<MachineOperand> Pred2) const {
const SmallVectorImpl<MachineOperand> &Pred2) const {
assert(Pred1.size() == 2 && "Invalid PPC first predicate"); assert(Pred1.size() == 2 && "Invalid PPC first predicate");
assert(Pred2.size() == 2 && "Invalid PPC second predicate"); assert(Pred2.size() == 2 && "Invalid PPC second predicate");

20
llvm/lib/Target/PowerPC/PPCInstrInfo.h
View File

@ -141,18 +141,14 @@ public:
bool AllowModify) const override; bool AllowModify) const override;
unsigned RemoveBranch(MachineBasicBlock &MBB) const override; unsigned RemoveBranch(MachineBasicBlock &MBB) const override;
unsigned InsertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB, unsigned InsertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB,
MachineBasicBlock *FBB, MachineBasicBlock *FBB, ArrayRef<MachineOperand> Cond,
const SmallVectorImpl<MachineOperand> &Cond,
DebugLoc DL) const override; DebugLoc DL) const override;
// Select analysis. // Select analysis.
bool canInsertSelect(const MachineBasicBlock&, bool canInsertSelect(const MachineBasicBlock &, ArrayRef<MachineOperand> Cond,
const SmallVectorImpl<MachineOperand> &Cond, unsigned, unsigned, int &, int &, int &) const override;
unsigned, unsigned, int&, int&, int&) const override; void insertSelect(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI,
void insertSelect(MachineBasicBlock &MBB, DebugLoc DL, unsigned DstReg, ArrayRef<MachineOperand> Cond,
MachineBasicBlock::iterator MI, DebugLoc DL,
unsigned DstReg,
const SmallVectorImpl<MachineOperand> &Cond,
unsigned TrueReg, unsigned FalseReg) const override; unsigned TrueReg, unsigned FalseReg) const override;
void copyPhysReg(MachineBasicBlock &MBB, void copyPhysReg(MachineBasicBlock &MBB,
@ -211,10 +207,10 @@ public:
bool isUnpredicatedTerminator(const MachineInstr *MI) const override; bool isUnpredicatedTerminator(const MachineInstr *MI) const override;
bool PredicateInstruction(MachineInstr *MI, bool PredicateInstruction(MachineInstr *MI,
const SmallVectorImpl<MachineOperand> &Pred) const override; ArrayRef<MachineOperand> Pred) const override;
bool SubsumesPredicate(const SmallVectorImpl<MachineOperand> &Pred1, bool SubsumesPredicate(ArrayRef<MachineOperand> Pred1,
const SmallVectorImpl<MachineOperand> &Pred2) const override; ArrayRef<MachineOperand> Pred2) const override;
bool DefinesPredicate(MachineInstr *MI, bool DefinesPredicate(MachineInstr *MI,
std::vector<MachineOperand> &Pred) const override; std::vector<MachineOperand> &Pred) const override;

7
llvm/lib/Target/R600/AMDGPUInstrInfo.cpp
View File

@ -234,10 +234,9 @@ bool AMDGPUInstrInfo::isPredicated(const MachineInstr *MI) const {
// TODO: Implement this function // TODO: Implement this function
return false; return false;
} }
bool
AMDGPUInstrInfo::SubsumesPredicate(const SmallVectorImpl<MachineOperand> &Pred1, bool AMDGPUInstrInfo::SubsumesPredicate(ArrayRef<MachineOperand> Pred1,
const SmallVectorImpl<MachineOperand> &Pred2) ArrayRef<MachineOperand> Pred2) const {
const {
// TODO: Implement this function // TODO: Implement this function
return false; return false;
} }

4
llvm/lib/Target/R600/AMDGPUInstrInfo.h
View File

@ -125,8 +125,8 @@ public:
void insertNoop(MachineBasicBlock &MBB, void insertNoop(MachineBasicBlock &MBB,
MachineBasicBlock::iterator MI) const override; MachineBasicBlock::iterator MI) const override;
bool isPredicated(const MachineInstr *MI) const override; bool isPredicated(const MachineInstr *MI) const override;
bool SubsumesPredicate(const SmallVectorImpl<MachineOperand> &Pred1, bool SubsumesPredicate(ArrayRef<MachineOperand> Pred1,
const SmallVectorImpl<MachineOperand> &Pred2) const override; ArrayRef<MachineOperand> Pred2) const override;
bool DefinesPredicate(MachineInstr *MI, bool DefinesPredicate(MachineInstr *MI,
std::vector<MachineOperand> &Pred) const override; std::vector<MachineOperand> &Pred) const override;
bool isPredicable(MachineInstr *MI) const override; bool isPredicable(MachineInstr *MI) const override;

13
llvm/lib/Target/R600/R600InstrInfo.cpp
View File

@ -354,7 +354,7 @@ R600InstrInfo::ExtractSrcs(MachineInstr *MI,
const DenseMap<unsigned, unsigned> &PV, const DenseMap<unsigned, unsigned> &PV,
unsigned &ConstCount) const { unsigned &ConstCount) const {
ConstCount = 0; ConstCount = 0;
const SmallVector<std::pair<MachineOperand *, int64_t>, 3> Srcs = getSrcs(MI); ArrayRef<std::pair<MachineOperand *, int64_t>> Srcs = getSrcs(MI);
const std::pair<int, unsigned> DummyPair(-1, 0); const std::pair<int, unsigned> DummyPair(-1, 0);
std::vector<std::pair<int, unsigned> > Result; std::vector<std::pair<int, unsigned> > Result;
unsigned i = 0; unsigned i = 0;
@ -628,8 +628,7 @@ R600InstrInfo::fitsConstReadLimitations(const std::vector<MachineInstr *> &MIs)
if (!isALUInstr(MI->getOpcode())) if (!isALUInstr(MI->getOpcode()))
continue; continue;
const SmallVectorImpl<std::pair<MachineOperand *, int64_t> > &Srcs = ArrayRef<std::pair<MachineOperand *, int64_t>> Srcs = getSrcs(MI);
getSrcs(MI);
for (unsigned j = 0, e = Srcs.size(); j < e; j++) { for (unsigned j = 0, e = Srcs.size(); j < e; j++) {
std::pair<MachineOperand *, unsigned> Src = Srcs[j]; std::pair<MachineOperand *, unsigned> Src = Srcs[j];
@ -782,7 +781,7 @@ unsigned
R600InstrInfo::InsertBranch(MachineBasicBlock &MBB, R600InstrInfo::InsertBranch(MachineBasicBlock &MBB,
MachineBasicBlock *TBB, MachineBasicBlock *TBB,
MachineBasicBlock *FBB, MachineBasicBlock *FBB,
const SmallVectorImpl<MachineOperand> &Cond, ArrayRef<MachineOperand> Cond,
DebugLoc DL) const { DebugLoc DL) const {
assert(TBB && "InsertBranch must not be told to insert a fallthrough"); assert(TBB && "InsertBranch must not be told to insert a fallthrough");
@ -1000,15 +999,15 @@ R600InstrInfo::DefinesPredicate(MachineInstr *MI,
bool bool
R600InstrInfo::SubsumesPredicate(const SmallVectorImpl<MachineOperand> &Pred1, R600InstrInfo::SubsumesPredicate(ArrayRef<MachineOperand> Pred1,
const SmallVectorImpl<MachineOperand> &Pred2) const { ArrayRef<MachineOperand> Pred2) const {
return false; return false;
} }
bool bool
R600InstrInfo::PredicateInstruction(MachineInstr *MI, R600InstrInfo::PredicateInstruction(MachineInstr *MI,
const SmallVectorImpl<MachineOperand> &Pred) const { ArrayRef<MachineOperand> Pred) const {
int PIdx = MI->findFirstPredOperandIdx(); int PIdx = MI->findFirstPredOperandIdx();
if (MI->getOpcode() == AMDGPU::CF_ALU) { if (MI->getOpcode() == AMDGPU::CF_ALU) {

10
llvm/lib/Target/R600/R600InstrInfo.h
View File

@ -162,7 +162,9 @@ namespace llvm {
bool AnalyzeBranch(MachineBasicBlock &MBB, MachineBasicBlock *&TBB, MachineBasicBlock *&FBB, bool AnalyzeBranch(MachineBasicBlock &MBB, MachineBasicBlock *&TBB, MachineBasicBlock *&FBB,
SmallVectorImpl<MachineOperand> &Cond, bool AllowModify) const override; SmallVectorImpl<MachineOperand> &Cond, bool AllowModify) const override;
unsigned InsertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB, MachineBasicBlock *FBB, const SmallVectorImpl<MachineOperand> &Cond, DebugLoc DL) const override; unsigned InsertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB,
MachineBasicBlock *FBB, ArrayRef<MachineOperand> Cond,
DebugLoc DL) const override;
unsigned RemoveBranch(MachineBasicBlock &MBB) const override; unsigned RemoveBranch(MachineBasicBlock &MBB) const override;
@ -188,14 +190,14 @@ namespace llvm {
bool DefinesPredicate(MachineInstr *MI, bool DefinesPredicate(MachineInstr *MI,
std::vector<MachineOperand> &Pred) const override; std::vector<MachineOperand> &Pred) const override;
bool SubsumesPredicate(const SmallVectorImpl<MachineOperand> &Pred1, bool SubsumesPredicate(ArrayRef<MachineOperand> Pred1,
const SmallVectorImpl<MachineOperand> &Pred2) const override; ArrayRef<MachineOperand> Pred2) const override;
bool isProfitableToUnpredicate(MachineBasicBlock &TMBB, bool isProfitableToUnpredicate(MachineBasicBlock &TMBB,
MachineBasicBlock &FMBB) const override; MachineBasicBlock &FMBB) const override;
bool PredicateInstruction(MachineInstr *MI, bool PredicateInstruction(MachineInstr *MI,
const SmallVectorImpl<MachineOperand> &Pred) const override; ArrayRef<MachineOperand> Pred) const override;
unsigned int getPredicationCost(const MachineInstr *) const override; unsigned int getPredicationCost(const MachineInstr *) const override;

2
llvm/lib/Target/Sparc/SparcInstrInfo.cpp
View File

@ -229,7 +229,7 @@ bool SparcInstrInfo::AnalyzeBranch(MachineBasicBlock &MBB,
unsigned unsigned
SparcInstrInfo::InsertBranch(MachineBasicBlock &MBB,MachineBasicBlock *TBB, SparcInstrInfo::InsertBranch(MachineBasicBlock &MBB,MachineBasicBlock *TBB,
MachineBasicBlock *FBB, MachineBasicBlock *FBB,
const SmallVectorImpl<MachineOperand> &Cond, ArrayRef<MachineOperand> Cond,
DebugLoc DL) const { DebugLoc DL) const {
assert(TBB && "InsertBranch must not be told to insert a fallthrough"); assert(TBB && "InsertBranch must not be told to insert a fallthrough");
assert((Cond.size() == 1 || Cond.size() == 0) && assert((Cond.size() == 1 || Cond.size() == 0) &&

3
llvm/lib/Target/Sparc/SparcInstrInfo.h
View File

@ -73,8 +73,7 @@ public:
unsigned RemoveBranch(MachineBasicBlock &MBB) const override; unsigned RemoveBranch(MachineBasicBlock &MBB) const override;
unsigned InsertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB, unsigned InsertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB,
MachineBasicBlock *FBB, MachineBasicBlock *FBB, ArrayRef<MachineOperand> Cond,
const SmallVectorImpl<MachineOperand> &Cond,
DebugLoc DL) const override; DebugLoc DL) const override;
void copyPhysReg(MachineBasicBlock &MBB, void copyPhysReg(MachineBasicBlock &MBB,

5
llvm/lib/Target/SystemZ/SystemZInstrInfo.cpp
View File

@ -362,7 +362,7 @@ ReverseBranchCondition(SmallVectorImpl<MachineOperand> &Cond) const {
unsigned unsigned
SystemZInstrInfo::InsertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB, SystemZInstrInfo::InsertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB,
MachineBasicBlock *FBB, MachineBasicBlock *FBB,
const SmallVectorImpl<MachineOperand> &Cond, ArrayRef<MachineOperand> Cond,
DebugLoc DL) const { DebugLoc DL) const {
// In this function we output 32-bit branches, which should always // In this function we output 32-bit branches, which should always
// have enough range. They can be shortened and relaxed by later code // have enough range. They can be shortened and relaxed by later code
@ -530,8 +530,7 @@ isProfitableToIfCvt(MachineBasicBlock &TMBB,
} }
bool SystemZInstrInfo:: bool SystemZInstrInfo::
PredicateInstruction(MachineInstr *MI, PredicateInstruction(MachineInstr *MI, ArrayRef<MachineOperand> Pred) const {
const SmallVectorImpl<MachineOperand> &Pred) const {
assert(Pred.size() == 2 && "Invalid condition"); assert(Pred.size() == 2 && "Invalid condition");
unsigned CCValid = Pred[0].getImm(); unsigned CCValid = Pred[0].getImm();
unsigned CCMask = Pred[1].getImm(); unsigned CCMask = Pred[1].getImm();

6
llvm/lib/Target/SystemZ/SystemZInstrInfo.h
View File

@ -149,8 +149,7 @@ public:
bool AllowModify) const override; bool AllowModify) const override;
unsigned RemoveBranch(MachineBasicBlock &MBB) const override; unsigned RemoveBranch(MachineBasicBlock &MBB) const override;
unsigned InsertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB, unsigned InsertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB,
MachineBasicBlock *FBB, MachineBasicBlock *FBB, ArrayRef<MachineOperand> Cond,
const SmallVectorImpl<MachineOperand> &Cond,
DebugLoc DL) const override; DebugLoc DL) const override;
bool analyzeCompare(const MachineInstr *MI, unsigned &SrcReg, bool analyzeCompare(const MachineInstr *MI, unsigned &SrcReg,
unsigned &SrcReg2, int &Mask, int &Value) const override; unsigned &SrcReg2, int &Mask, int &Value) const override;
@ -167,8 +166,7 @@ public:
unsigned NumCyclesF, unsigned ExtraPredCyclesF, unsigned NumCyclesF, unsigned ExtraPredCyclesF,
const BranchProbability &Probability) const override; const BranchProbability &Probability) const override;
bool PredicateInstruction(MachineInstr *MI, bool PredicateInstruction(MachineInstr *MI,
const SmallVectorImpl<MachineOperand> &Pred) const ArrayRef<MachineOperand> Pred) const override;
override;
void copyPhysReg(MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI, void copyPhysReg(MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI,
DebugLoc DL, unsigned DestReg, unsigned SrcReg, DebugLoc DL, unsigned DestReg, unsigned SrcReg,
bool KillSrc) const override; bool KillSrc) const override;

8
llvm/lib/Target/X86/X86InstrInfo.cpp
View File

@ -3622,8 +3622,7 @@ unsigned X86InstrInfo::RemoveBranch(MachineBasicBlock &MBB) const {
unsigned unsigned
X86InstrInfo::InsertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB, X86InstrInfo::InsertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB,
MachineBasicBlock *FBB, MachineBasicBlock *FBB, ArrayRef<MachineOperand> Cond,
const SmallVectorImpl<MachineOperand> &Cond,
DebugLoc DL) const { DebugLoc DL) const {
// Shouldn't be a fall through. // Shouldn't be a fall through.
assert(TBB && "InsertBranch must not be told to insert a fallthrough"); assert(TBB && "InsertBranch must not be told to insert a fallthrough");
@ -3671,7 +3670,7 @@ X86InstrInfo::InsertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB,
bool X86InstrInfo:: bool X86InstrInfo::
canInsertSelect(const MachineBasicBlock &MBB, canInsertSelect(const MachineBasicBlock &MBB,
const SmallVectorImpl<MachineOperand> &Cond, ArrayRef<MachineOperand> Cond,
unsigned TrueReg, unsigned FalseReg, unsigned TrueReg, unsigned FalseReg,
int &CondCycles, int &TrueCycles, int &FalseCycles) const { int &CondCycles, int &TrueCycles, int &FalseCycles) const {
// Not all subtargets have cmov instructions. // Not all subtargets have cmov instructions.
@ -3708,8 +3707,7 @@ canInsertSelect(const MachineBasicBlock &MBB,
void X86InstrInfo::insertSelect(MachineBasicBlock &MBB, void X86InstrInfo::insertSelect(MachineBasicBlock &MBB,
MachineBasicBlock::iterator I, DebugLoc DL, MachineBasicBlock::iterator I, DebugLoc DL,
unsigned DstReg, unsigned DstReg, ArrayRef<MachineOperand> Cond,
const SmallVectorImpl<MachineOperand> &Cond,
unsigned TrueReg, unsigned FalseReg) const { unsigned TrueReg, unsigned FalseReg) const {
MachineRegisterInfo &MRI = MBB.getParent()->getRegInfo(); MachineRegisterInfo &MRI = MBB.getParent()->getRegInfo();
assert(Cond.size() == 1 && "Invalid Cond array"); assert(Cond.size() == 1 && "Invalid Cond array");

9
llvm/lib/Target/X86/X86InstrInfo.h
View File

@ -269,16 +269,13 @@ public:
bool AllowModify) const override; bool AllowModify) const override;
unsigned RemoveBranch(MachineBasicBlock &MBB) const override; unsigned RemoveBranch(MachineBasicBlock &MBB) const override;
unsigned InsertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB, unsigned InsertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB,
MachineBasicBlock *FBB, MachineBasicBlock *FBB, ArrayRef<MachineOperand> Cond,
const SmallVectorImpl<MachineOperand> &Cond,
DebugLoc DL) const override; DebugLoc DL) const override;
bool canInsertSelect(const MachineBasicBlock&, bool canInsertSelect(const MachineBasicBlock&, ArrayRef<MachineOperand> Cond,
const SmallVectorImpl<MachineOperand> &Cond,
unsigned, unsigned, int&, int&, int&) const override; unsigned, unsigned, int&, int&, int&) const override;
void insertSelect(MachineBasicBlock &MBB, void insertSelect(MachineBasicBlock &MBB,
MachineBasicBlock::iterator MI, DebugLoc DL, MachineBasicBlock::iterator MI, DebugLoc DL,
unsigned DstReg, unsigned DstReg, ArrayRef<MachineOperand> Cond,
const SmallVectorImpl<MachineOperand> &Cond,
unsigned TrueReg, unsigned FalseReg) const override; unsigned TrueReg, unsigned FalseReg) const override;
void copyPhysReg(MachineBasicBlock &MBB, void copyPhysReg(MachineBasicBlock &MBB,
MachineBasicBlock::iterator MI, DebugLoc DL, MachineBasicBlock::iterator MI, DebugLoc DL,

2
llvm/lib/Target/XCore/XCoreInstrInfo.cpp
View File

@ -281,7 +281,7 @@ XCoreInstrInfo::AnalyzeBranch(MachineBasicBlock &MBB, MachineBasicBlock *&TBB,
unsigned unsigned
XCoreInstrInfo::InsertBranch(MachineBasicBlock &MBB,MachineBasicBlock *TBB, XCoreInstrInfo::InsertBranch(MachineBasicBlock &MBB,MachineBasicBlock *TBB,
MachineBasicBlock *FBB, MachineBasicBlock *FBB,
const SmallVectorImpl<MachineOperand> &Cond, ArrayRef<MachineOperand> Cond,
DebugLoc DL)const{ DebugLoc DL)const{
// Shouldn't be a fall through. // Shouldn't be a fall through.
assert(TBB && "InsertBranch must not be told to insert a fallthrough"); assert(TBB && "InsertBranch must not be told to insert a fallthrough");

3
llvm/lib/Target/XCore/XCoreInstrInfo.h
View File

@ -56,8 +56,7 @@ public:
bool AllowModify) const override; bool AllowModify) const override;
unsigned InsertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB, unsigned InsertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB,
MachineBasicBlock *FBB, MachineBasicBlock *FBB, ArrayRef<MachineOperand> Cond,
const SmallVectorImpl<MachineOperand> &Cond,
DebugLoc DL) const override; DebugLoc DL) const override;
unsigned RemoveBranch(MachineBasicBlock &MBB) const override; unsigned RemoveBranch(MachineBasicBlock &MBB) const override;