forked from OSchip/llvm-project
[CodeGen] ArrayRef'ize cond/pred in various TII APIs. NFC.
llvm-svn: 239553
This commit is contained in:
parent
7c6e6e49cc
commit
c88bf54366
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@ -405,7 +405,7 @@ public:
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/// merging needs to be disabled.
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virtual unsigned InsertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB,
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MachineBasicBlock *FBB,
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const SmallVectorImpl<MachineOperand> &Cond,
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ArrayRef<MachineOperand> Cond,
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DebugLoc DL) const {
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llvm_unreachable("Target didn't implement TargetInstrInfo::InsertBranch!");
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}
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@ -530,7 +530,7 @@ public:
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/// @param TrueCycles Latency from TrueReg to select output.
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/// @param FalseCycles Latency from FalseReg to select output.
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virtual bool canInsertSelect(const MachineBasicBlock &MBB,
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const SmallVectorImpl<MachineOperand> &Cond,
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ArrayRef<MachineOperand> Cond,
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unsigned TrueReg, unsigned FalseReg,
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int &CondCycles,
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int &TrueCycles, int &FalseCycles) const {
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@ -554,8 +554,7 @@ public:
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/// @param FalseReg Virtual register to copy when Cons is false.
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virtual void insertSelect(MachineBasicBlock &MBB,
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MachineBasicBlock::iterator I, DebugLoc DL,
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unsigned DstReg,
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const SmallVectorImpl<MachineOperand> &Cond,
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unsigned DstReg, ArrayRef<MachineOperand> Cond,
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unsigned TrueReg, unsigned FalseReg) const {
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llvm_unreachable("Target didn't implement TargetInstrInfo::insertSelect!");
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}
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@ -878,13 +877,13 @@ public:
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/// It returns true if the operation was successful.
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virtual
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bool PredicateInstruction(MachineInstr *MI,
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const SmallVectorImpl<MachineOperand> &Pred) const;
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ArrayRef<MachineOperand> Pred) const;
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/// Returns true if the first specified predicate
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/// subsumes the second, e.g. GE subsumes GT.
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virtual
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bool SubsumesPredicate(const SmallVectorImpl<MachineOperand> &Pred1,
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const SmallVectorImpl<MachineOperand> &Pred2) const {
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bool SubsumesPredicate(ArrayRef<MachineOperand> Pred1,
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ArrayRef<MachineOperand> Pred2) const {
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return false;
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}
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@ -219,9 +219,8 @@ TargetInstrInfo::isUnpredicatedTerminator(const MachineInstr *MI) const {
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return !isPredicated(MI);
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}
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bool TargetInstrInfo::PredicateInstruction(MachineInstr *MI,
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const SmallVectorImpl<MachineOperand> &Pred) const {
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bool TargetInstrInfo::PredicateInstruction(
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MachineInstr *MI, ArrayRef<MachineOperand> Pred) const {
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bool MadeChange = false;
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assert(!MI->isBundle() &&
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@ -255,7 +255,7 @@ unsigned AArch64InstrInfo::RemoveBranch(MachineBasicBlock &MBB) const {
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void AArch64InstrInfo::instantiateCondBranch(
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MachineBasicBlock &MBB, DebugLoc DL, MachineBasicBlock *TBB,
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const SmallVectorImpl<MachineOperand> &Cond) const {
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ArrayRef<MachineOperand> Cond) const {
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if (Cond[0].getImm() != -1) {
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// Regular Bcc
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BuildMI(&MBB, DL, get(AArch64::Bcc)).addImm(Cond[0].getImm()).addMBB(TBB);
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@ -272,7 +272,7 @@ void AArch64InstrInfo::instantiateCondBranch(
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unsigned AArch64InstrInfo::InsertBranch(
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MachineBasicBlock &MBB, MachineBasicBlock *TBB, MachineBasicBlock *FBB,
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const SmallVectorImpl<MachineOperand> &Cond, DebugLoc DL) const {
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ArrayRef<MachineOperand> Cond, DebugLoc DL) const {
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// Shouldn't be a fall through.
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assert(TBB && "InsertBranch must not be told to insert a fallthrough");
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@ -369,7 +369,7 @@ static unsigned canFoldIntoCSel(const MachineRegisterInfo &MRI, unsigned VReg,
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}
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bool AArch64InstrInfo::canInsertSelect(
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const MachineBasicBlock &MBB, const SmallVectorImpl<MachineOperand> &Cond,
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const MachineBasicBlock &MBB, ArrayRef<MachineOperand> Cond,
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unsigned TrueReg, unsigned FalseReg, int &CondCycles, int &TrueCycles,
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int &FalseCycles) const {
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// Check register classes.
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@ -412,7 +412,7 @@ bool AArch64InstrInfo::canInsertSelect(
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void AArch64InstrInfo::insertSelect(MachineBasicBlock &MBB,
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MachineBasicBlock::iterator I, DebugLoc DL,
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unsigned DstReg,
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const SmallVectorImpl<MachineOperand> &Cond,
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ArrayRef<MachineOperand> Cond,
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unsigned TrueReg, unsigned FalseReg) const {
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MachineRegisterInfo &MRI = MBB.getParent()->getRegInfo();
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@ -140,17 +140,14 @@ public:
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bool AllowModify = false) const override;
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unsigned RemoveBranch(MachineBasicBlock &MBB) const override;
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unsigned InsertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB,
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MachineBasicBlock *FBB,
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const SmallVectorImpl<MachineOperand> &Cond,
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MachineBasicBlock *FBB, ArrayRef<MachineOperand> Cond,
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DebugLoc DL) const override;
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bool
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ReverseBranchCondition(SmallVectorImpl<MachineOperand> &Cond) const override;
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bool canInsertSelect(const MachineBasicBlock &,
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const SmallVectorImpl<MachineOperand> &Cond, unsigned,
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unsigned, int &, int &, int &) const override;
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bool canInsertSelect(const MachineBasicBlock &, ArrayRef<MachineOperand> Cond,
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unsigned, unsigned, int &, int &, int &) const override;
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void insertSelect(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI,
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DebugLoc DL, unsigned DstReg,
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const SmallVectorImpl<MachineOperand> &Cond,
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DebugLoc DL, unsigned DstReg, ArrayRef<MachineOperand> Cond,
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unsigned TrueReg, unsigned FalseReg) const override;
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void getNoopForMachoTarget(MCInst &NopInst) const override;
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@ -189,7 +186,7 @@ public:
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private:
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void instantiateCondBranch(MachineBasicBlock &MBB, DebugLoc DL,
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MachineBasicBlock *TBB,
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const SmallVectorImpl<MachineOperand> &Cond) const;
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ArrayRef<MachineOperand> Cond) const;
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};
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/// emitFrameOffset - Emit instructions as needed to set DestReg to SrcReg
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@ -396,7 +396,7 @@ unsigned ARMBaseInstrInfo::RemoveBranch(MachineBasicBlock &MBB) const {
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unsigned
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ARMBaseInstrInfo::InsertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB,
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MachineBasicBlock *FBB,
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const SmallVectorImpl<MachineOperand> &Cond,
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ArrayRef<MachineOperand> Cond,
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DebugLoc DL) const {
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ARMFunctionInfo *AFI = MBB.getParent()->getInfo<ARMFunctionInfo>();
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int BOpc = !AFI->isThumbFunction()
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@ -458,8 +458,7 @@ bool ARMBaseInstrInfo::isPredicated(const MachineInstr *MI) const {
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}
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bool ARMBaseInstrInfo::
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PredicateInstruction(MachineInstr *MI,
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const SmallVectorImpl<MachineOperand> &Pred) const {
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PredicateInstruction(MachineInstr *MI, ArrayRef<MachineOperand> Pred) const {
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unsigned Opc = MI->getOpcode();
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if (isUncondBranchOpcode(Opc)) {
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MI->setDesc(get(getMatchingCondBranchOpcode(Opc)));
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@ -479,9 +478,8 @@ PredicateInstruction(MachineInstr *MI,
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return false;
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}
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bool ARMBaseInstrInfo::
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SubsumesPredicate(const SmallVectorImpl<MachineOperand> &Pred1,
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const SmallVectorImpl<MachineOperand> &Pred2) const {
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bool ARMBaseInstrInfo::SubsumesPredicate(ArrayRef<MachineOperand> Pred1,
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ArrayRef<MachineOperand> Pred2) const {
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if (Pred1.size() > 2 || Pred2.size() > 2)
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return false;
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@ -116,8 +116,7 @@ public:
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bool AllowModify = false) const override;
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unsigned RemoveBranch(MachineBasicBlock &MBB) const override;
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unsigned InsertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB,
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MachineBasicBlock *FBB,
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const SmallVectorImpl<MachineOperand> &Cond,
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MachineBasicBlock *FBB, ArrayRef<MachineOperand> Cond,
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DebugLoc DL) const override;
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bool
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@ -133,10 +132,10 @@ public:
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}
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bool PredicateInstruction(MachineInstr *MI,
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const SmallVectorImpl<MachineOperand> &Pred) const override;
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ArrayRef<MachineOperand> Pred) const override;
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bool SubsumesPredicate(const SmallVectorImpl<MachineOperand> &Pred1,
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const SmallVectorImpl<MachineOperand> &Pred2) const override;
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bool SubsumesPredicate(ArrayRef<MachineOperand> Pred1,
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ArrayRef<MachineOperand> Pred2) const override;
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bool DefinesPredicate(MachineInstr *MI,
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std::vector<MachineOperand> &Pred) const override;
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@ -133,7 +133,7 @@ bool BPFInstrInfo::AnalyzeBranch(MachineBasicBlock &MBB,
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unsigned BPFInstrInfo::InsertBranch(MachineBasicBlock &MBB,
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MachineBasicBlock *TBB,
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MachineBasicBlock *FBB,
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const SmallVectorImpl<MachineOperand> &Cond,
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ArrayRef<MachineOperand> Cond,
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DebugLoc DL) const {
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// Shouldn't be a fall through.
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assert(TBB && "InsertBranch must not be told to insert a fallthrough");
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@ -51,8 +51,7 @@ public:
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unsigned RemoveBranch(MachineBasicBlock &MBB) const override;
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unsigned InsertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB,
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MachineBasicBlock *FBB,
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const SmallVectorImpl<MachineOperand> &Cond,
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MachineBasicBlock *FBB, ArrayRef<MachineOperand> Cond,
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DebugLoc DL) const override;
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};
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}
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@ -159,7 +159,7 @@ findLoopInstr(MachineBasicBlock *BB, int EndLoopOp,
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unsigned HexagonInstrInfo::InsertBranch(
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MachineBasicBlock &MBB,MachineBasicBlock *TBB, MachineBasicBlock *FBB,
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const SmallVectorImpl<MachineOperand> &Cond, DebugLoc DL) const {
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ArrayRef<MachineOperand> Cond, DebugLoc DL) const {
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Opcode_t BOpc = Hexagon::J2_jump;
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Opcode_t BccOpc = Hexagon::J2_jumpt;
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@ -1013,7 +1013,7 @@ int HexagonInstrInfo::getCondOpcode(int Opc, bool invertPredicate) const {
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bool HexagonInstrInfo::
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PredicateInstruction(MachineInstr *MI,
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const SmallVectorImpl<MachineOperand> &Cond) const {
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ArrayRef<MachineOperand> Cond) const {
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if (Cond.empty() || isEndLoopN(Cond[0].getImm())) {
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DEBUG(dbgs() << "\nCannot predicate:"; MI->dump(););
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return false;
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@ -1162,8 +1162,8 @@ HexagonInstrInfo::DefinesPredicate(MachineInstr *MI,
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bool
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HexagonInstrInfo::
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SubsumesPredicate(const SmallVectorImpl<MachineOperand> &Pred1,
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const SmallVectorImpl<MachineOperand> &Pred2) const {
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SubsumesPredicate(ArrayRef<MachineOperand> Pred1,
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ArrayRef<MachineOperand> Pred2) const {
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// TODO: Fix this
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return false;
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}
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@ -1982,8 +1982,7 @@ bool HexagonInstrInfo::PredOpcodeHasJMP_c(Opcode_t Opcode) const {
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(Opcode == Hexagon::J2_jumpf);
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}
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bool HexagonInstrInfo::predOpcodeHasNot(
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const SmallVectorImpl<MachineOperand> &Cond) const {
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bool HexagonInstrInfo::predOpcodeHasNot(ArrayRef<MachineOperand> Cond) const {
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if (Cond.empty() || !isPredicated(Cond[0].getImm()))
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return false;
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return !isPredicatedTrue(Cond[0].getImm());
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@ -1994,7 +1993,7 @@ bool HexagonInstrInfo::isEndLoopN(Opcode_t Opcode) const {
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Opcode == Hexagon::ENDLOOP1);
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}
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bool HexagonInstrInfo::getPredReg(const SmallVectorImpl<MachineOperand> &Cond,
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bool HexagonInstrInfo::getPredReg(ArrayRef<MachineOperand> Cond,
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unsigned &PredReg, unsigned &PredRegPos,
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unsigned &PredRegFlags) const {
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if (Cond.empty())
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@ -69,8 +69,7 @@ public:
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unsigned RemoveBranch(MachineBasicBlock &MBB) const override;
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unsigned InsertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB,
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MachineBasicBlock *FBB,
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const SmallVectorImpl<MachineOperand> &Cond,
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MachineBasicBlock *FBB, ArrayRef<MachineOperand> Cond,
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DebugLoc DL) const override;
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bool analyzeCompare(const MachineInstr *MI,
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@ -129,7 +128,7 @@ public:
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bool isBranch(const MachineInstr *MI) const;
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bool isPredicable(MachineInstr *MI) const override;
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bool PredicateInstruction(MachineInstr *MI,
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const SmallVectorImpl<MachineOperand> &Cond) const override;
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ArrayRef<MachineOperand> Cond) const override;
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bool isProfitableToIfCvt(MachineBasicBlock &MBB, unsigned NumCycles,
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unsigned ExtraPredCycles,
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@ -149,8 +148,8 @@ public:
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bool isPredicatedNew(unsigned Opcode) const;
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bool DefinesPredicate(MachineInstr *MI,
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std::vector<MachineOperand> &Pred) const override;
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bool SubsumesPredicate(const SmallVectorImpl<MachineOperand> &Pred1,
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const SmallVectorImpl<MachineOperand> &Pred2) const override;
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bool SubsumesPredicate(ArrayRef<MachineOperand> Pred1,
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ArrayRef<MachineOperand> Pred2) const override;
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bool
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ReverseBranchCondition(SmallVectorImpl<MachineOperand> &Cond) const override;
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@ -222,11 +221,10 @@ public:
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bool NonExtEquivalentExists (const MachineInstr *MI) const;
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short getNonExtOpcode(const MachineInstr *MI) const;
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bool PredOpcodeHasJMP_c(Opcode_t Opcode) const;
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bool predOpcodeHasNot(const SmallVectorImpl<MachineOperand> &Cond) const;
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bool predOpcodeHasNot(ArrayRef<MachineOperand> Cond) const;
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bool isEndLoopN(Opcode_t Opcode) const;
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bool getPredReg(const SmallVectorImpl<MachineOperand> &Cond,
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unsigned &PredReg, unsigned &PredRegPos,
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unsigned &PredRegFlags) const;
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bool getPredReg(ArrayRef<MachineOperand> Cond, unsigned &PredReg,
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unsigned &PredRegPos, unsigned &PredRegFlags) const;
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int getCondOpcode(int Opc, bool sense) const;
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};
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@ -262,7 +262,7 @@ bool MSP430InstrInfo::AnalyzeBranch(MachineBasicBlock &MBB,
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unsigned
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MSP430InstrInfo::InsertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB,
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MachineBasicBlock *FBB,
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const SmallVectorImpl<MachineOperand> &Cond,
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ArrayRef<MachineOperand> Cond,
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DebugLoc DL) const {
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// Shouldn't be a fall through.
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assert(TBB && "InsertBranch must not be told to insert a fallthrough");
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@ -82,8 +82,7 @@ public:
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unsigned RemoveBranch(MachineBasicBlock &MBB) const override;
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unsigned InsertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB,
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MachineBasicBlock *FBB,
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const SmallVectorImpl<MachineOperand> &Cond,
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MachineBasicBlock *FBB, ArrayRef<MachineOperand> Cond,
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DebugLoc DL) const override;
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};
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@ -96,8 +96,7 @@ bool MipsInstrInfo::AnalyzeBranch(MachineBasicBlock &MBB,
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void
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MipsInstrInfo::BuildCondBr(MachineBasicBlock &MBB, MachineBasicBlock *TBB,
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DebugLoc DL,
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const SmallVectorImpl<MachineOperand> &Cond) const {
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DebugLoc DL, ArrayRef<MachineOperand> Cond) const {
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unsigned Opc = Cond[0].getImm();
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const MCInstrDesc &MCID = get(Opc);
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MachineInstrBuilder MIB = BuildMI(&MBB, DL, MCID);
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@ -115,7 +114,7 @@ MipsInstrInfo::BuildCondBr(MachineBasicBlock &MBB, MachineBasicBlock *TBB,
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unsigned MipsInstrInfo::InsertBranch(
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MachineBasicBlock &MBB, MachineBasicBlock *TBB, MachineBasicBlock *FBB,
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const SmallVectorImpl<MachineOperand> &Cond, DebugLoc DL) const {
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ArrayRef<MachineOperand> Cond, DebugLoc DL) const {
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// Shouldn't be a fall through.
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assert(TBB && "InsertBranch must not be told to insert a fallthrough");
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@ -59,8 +59,7 @@ public:
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unsigned RemoveBranch(MachineBasicBlock &MBB) const override;
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unsigned InsertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB,
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MachineBasicBlock *FBB,
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const SmallVectorImpl<MachineOperand> &Cond,
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MachineBasicBlock *FBB, ArrayRef<MachineOperand> Cond,
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DebugLoc DL) const override;
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bool
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SmallVectorImpl<MachineOperand> &Cond) const;
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void BuildCondBr(MachineBasicBlock &MBB, MachineBasicBlock *TBB, DebugLoc DL,
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const SmallVectorImpl<MachineOperand>& Cond) const;
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ArrayRef<MachineOperand> Cond) const;
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};
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/// Create MipsInstrInfo objects.
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@ -248,7 +248,7 @@ unsigned NVPTXInstrInfo::RemoveBranch(MachineBasicBlock &MBB) const {
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unsigned NVPTXInstrInfo::InsertBranch(
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MachineBasicBlock &MBB, MachineBasicBlock *TBB, MachineBasicBlock *FBB,
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const SmallVectorImpl<MachineOperand> &Cond, DebugLoc DL) const {
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ArrayRef<MachineOperand> Cond, DebugLoc DL) const {
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// Shouldn't be a fall through.
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assert(TBB && "InsertBranch must not be told to insert a fallthrough");
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assert((Cond.size() == 1 || Cond.size() == 0) &&
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@ -66,7 +66,7 @@ public:
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unsigned RemoveBranch(MachineBasicBlock &MBB) const override;
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unsigned InsertBranch(
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MachineBasicBlock &MBB, MachineBasicBlock *TBB, MachineBasicBlock *FBB,
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const SmallVectorImpl<MachineOperand> &Cond, DebugLoc DL) const override;
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ArrayRef<MachineOperand> Cond, DebugLoc DL) const override;
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unsigned getLdStCodeAddrSpace(const MachineInstr &MI) const {
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return MI.getOperand(2).getImm();
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}
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@ -548,7 +548,7 @@ unsigned PPCInstrInfo::RemoveBranch(MachineBasicBlock &MBB) const {
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unsigned
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PPCInstrInfo::InsertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB,
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MachineBasicBlock *FBB,
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const SmallVectorImpl<MachineOperand> &Cond,
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ArrayRef<MachineOperand> Cond,
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DebugLoc DL) const {
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// Shouldn't be a fall through.
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assert(TBB && "InsertBranch must not be told to insert a fallthrough");
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@ -593,7 +593,7 @@ PPCInstrInfo::InsertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB,
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// Select analysis.
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bool PPCInstrInfo::canInsertSelect(const MachineBasicBlock &MBB,
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const SmallVectorImpl<MachineOperand> &Cond,
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ArrayRef<MachineOperand> Cond,
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unsigned TrueReg, unsigned FalseReg,
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int &CondCycles, int &TrueCycles, int &FalseCycles) const {
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if (!Subtarget.hasISEL())
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@ -634,8 +634,7 @@ bool PPCInstrInfo::canInsertSelect(const MachineBasicBlock &MBB,
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void PPCInstrInfo::insertSelect(MachineBasicBlock &MBB,
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MachineBasicBlock::iterator MI, DebugLoc dl,
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unsigned DestReg,
|
||||
const SmallVectorImpl<MachineOperand> &Cond,
|
||||
unsigned DestReg, ArrayRef<MachineOperand> Cond,
|
||||
unsigned TrueReg, unsigned FalseReg) const {
|
||||
assert(Cond.size() == 2 &&
|
||||
"PPC branch conditions have two components!");
|
||||
|
@ -1213,9 +1212,8 @@ bool PPCInstrInfo::isUnpredicatedTerminator(const MachineInstr *MI) const {
|
|||
return !isPredicated(MI);
|
||||
}
|
||||
|
||||
bool PPCInstrInfo::PredicateInstruction(
|
||||
MachineInstr *MI,
|
||||
const SmallVectorImpl<MachineOperand> &Pred) const {
|
||||
bool PPCInstrInfo::PredicateInstruction(MachineInstr *MI,
|
||||
ArrayRef<MachineOperand> Pred) const {
|
||||
unsigned OpC = MI->getOpcode();
|
||||
if (OpC == PPC::BLR || OpC == PPC::BLR8) {
|
||||
if (Pred[1].getReg() == PPC::CTR8 || Pred[1].getReg() == PPC::CTR) {
|
||||
|
@ -1306,9 +1304,8 @@ bool PPCInstrInfo::PredicateInstruction(
|
|||
return false;
|
||||
}
|
||||
|
||||
bool PPCInstrInfo::SubsumesPredicate(
|
||||
const SmallVectorImpl<MachineOperand> &Pred1,
|
||||
const SmallVectorImpl<MachineOperand> &Pred2) const {
|
||||
bool PPCInstrInfo::SubsumesPredicate(ArrayRef<MachineOperand> Pred1,
|
||||
ArrayRef<MachineOperand> Pred2) const {
|
||||
assert(Pred1.size() == 2 && "Invalid PPC first predicate");
|
||||
assert(Pred2.size() == 2 && "Invalid PPC second predicate");
|
||||
|
||||
|
|
|
@ -141,18 +141,14 @@ public:
|
|||
bool AllowModify) const override;
|
||||
unsigned RemoveBranch(MachineBasicBlock &MBB) const override;
|
||||
unsigned InsertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB,
|
||||
MachineBasicBlock *FBB,
|
||||
const SmallVectorImpl<MachineOperand> &Cond,
|
||||
MachineBasicBlock *FBB, ArrayRef<MachineOperand> Cond,
|
||||
DebugLoc DL) const override;
|
||||
|
||||
// Select analysis.
|
||||
bool canInsertSelect(const MachineBasicBlock&,
|
||||
const SmallVectorImpl<MachineOperand> &Cond,
|
||||
unsigned, unsigned, int&, int&, int&) const override;
|
||||
void insertSelect(MachineBasicBlock &MBB,
|
||||
MachineBasicBlock::iterator MI, DebugLoc DL,
|
||||
unsigned DstReg,
|
||||
const SmallVectorImpl<MachineOperand> &Cond,
|
||||
bool canInsertSelect(const MachineBasicBlock &, ArrayRef<MachineOperand> Cond,
|
||||
unsigned, unsigned, int &, int &, int &) const override;
|
||||
void insertSelect(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI,
|
||||
DebugLoc DL, unsigned DstReg, ArrayRef<MachineOperand> Cond,
|
||||
unsigned TrueReg, unsigned FalseReg) const override;
|
||||
|
||||
void copyPhysReg(MachineBasicBlock &MBB,
|
||||
|
@ -211,10 +207,10 @@ public:
|
|||
bool isUnpredicatedTerminator(const MachineInstr *MI) const override;
|
||||
|
||||
bool PredicateInstruction(MachineInstr *MI,
|
||||
const SmallVectorImpl<MachineOperand> &Pred) const override;
|
||||
ArrayRef<MachineOperand> Pred) const override;
|
||||
|
||||
bool SubsumesPredicate(const SmallVectorImpl<MachineOperand> &Pred1,
|
||||
const SmallVectorImpl<MachineOperand> &Pred2) const override;
|
||||
bool SubsumesPredicate(ArrayRef<MachineOperand> Pred1,
|
||||
ArrayRef<MachineOperand> Pred2) const override;
|
||||
|
||||
bool DefinesPredicate(MachineInstr *MI,
|
||||
std::vector<MachineOperand> &Pred) const override;
|
||||
|
|
|
@ -234,10 +234,9 @@ bool AMDGPUInstrInfo::isPredicated(const MachineInstr *MI) const {
|
|||
// TODO: Implement this function
|
||||
return false;
|
||||
}
|
||||
bool
|
||||
AMDGPUInstrInfo::SubsumesPredicate(const SmallVectorImpl<MachineOperand> &Pred1,
|
||||
const SmallVectorImpl<MachineOperand> &Pred2)
|
||||
const {
|
||||
|
||||
bool AMDGPUInstrInfo::SubsumesPredicate(ArrayRef<MachineOperand> Pred1,
|
||||
ArrayRef<MachineOperand> Pred2) const {
|
||||
// TODO: Implement this function
|
||||
return false;
|
||||
}
|
||||
|
|
|
@ -125,8 +125,8 @@ public:
|
|||
void insertNoop(MachineBasicBlock &MBB,
|
||||
MachineBasicBlock::iterator MI) const override;
|
||||
bool isPredicated(const MachineInstr *MI) const override;
|
||||
bool SubsumesPredicate(const SmallVectorImpl<MachineOperand> &Pred1,
|
||||
const SmallVectorImpl<MachineOperand> &Pred2) const override;
|
||||
bool SubsumesPredicate(ArrayRef<MachineOperand> Pred1,
|
||||
ArrayRef<MachineOperand> Pred2) const override;
|
||||
bool DefinesPredicate(MachineInstr *MI,
|
||||
std::vector<MachineOperand> &Pred) const override;
|
||||
bool isPredicable(MachineInstr *MI) const override;
|
||||
|
|
|
@ -354,7 +354,7 @@ R600InstrInfo::ExtractSrcs(MachineInstr *MI,
|
|||
const DenseMap<unsigned, unsigned> &PV,
|
||||
unsigned &ConstCount) const {
|
||||
ConstCount = 0;
|
||||
const SmallVector<std::pair<MachineOperand *, int64_t>, 3> Srcs = getSrcs(MI);
|
||||
ArrayRef<std::pair<MachineOperand *, int64_t>> Srcs = getSrcs(MI);
|
||||
const std::pair<int, unsigned> DummyPair(-1, 0);
|
||||
std::vector<std::pair<int, unsigned> > Result;
|
||||
unsigned i = 0;
|
||||
|
@ -628,8 +628,7 @@ R600InstrInfo::fitsConstReadLimitations(const std::vector<MachineInstr *> &MIs)
|
|||
if (!isALUInstr(MI->getOpcode()))
|
||||
continue;
|
||||
|
||||
const SmallVectorImpl<std::pair<MachineOperand *, int64_t> > &Srcs =
|
||||
getSrcs(MI);
|
||||
ArrayRef<std::pair<MachineOperand *, int64_t>> Srcs = getSrcs(MI);
|
||||
|
||||
for (unsigned j = 0, e = Srcs.size(); j < e; j++) {
|
||||
std::pair<MachineOperand *, unsigned> Src = Srcs[j];
|
||||
|
@ -782,7 +781,7 @@ unsigned
|
|||
R600InstrInfo::InsertBranch(MachineBasicBlock &MBB,
|
||||
MachineBasicBlock *TBB,
|
||||
MachineBasicBlock *FBB,
|
||||
const SmallVectorImpl<MachineOperand> &Cond,
|
||||
ArrayRef<MachineOperand> Cond,
|
||||
DebugLoc DL) const {
|
||||
assert(TBB && "InsertBranch must not be told to insert a fallthrough");
|
||||
|
||||
|
@ -1000,15 +999,15 @@ R600InstrInfo::DefinesPredicate(MachineInstr *MI,
|
|||
|
||||
|
||||
bool
|
||||
R600InstrInfo::SubsumesPredicate(const SmallVectorImpl<MachineOperand> &Pred1,
|
||||
const SmallVectorImpl<MachineOperand> &Pred2) const {
|
||||
R600InstrInfo::SubsumesPredicate(ArrayRef<MachineOperand> Pred1,
|
||||
ArrayRef<MachineOperand> Pred2) const {
|
||||
return false;
|
||||
}
|
||||
|
||||
|
||||
bool
|
||||
R600InstrInfo::PredicateInstruction(MachineInstr *MI,
|
||||
const SmallVectorImpl<MachineOperand> &Pred) const {
|
||||
ArrayRef<MachineOperand> Pred) const {
|
||||
int PIdx = MI->findFirstPredOperandIdx();
|
||||
|
||||
if (MI->getOpcode() == AMDGPU::CF_ALU) {
|
||||
|
|
|
@ -162,7 +162,9 @@ namespace llvm {
|
|||
bool AnalyzeBranch(MachineBasicBlock &MBB, MachineBasicBlock *&TBB, MachineBasicBlock *&FBB,
|
||||
SmallVectorImpl<MachineOperand> &Cond, bool AllowModify) const override;
|
||||
|
||||
unsigned InsertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB, MachineBasicBlock *FBB, const SmallVectorImpl<MachineOperand> &Cond, DebugLoc DL) const override;
|
||||
unsigned InsertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB,
|
||||
MachineBasicBlock *FBB, ArrayRef<MachineOperand> Cond,
|
||||
DebugLoc DL) const override;
|
||||
|
||||
unsigned RemoveBranch(MachineBasicBlock &MBB) const override;
|
||||
|
||||
|
@ -188,14 +190,14 @@ namespace llvm {
|
|||
bool DefinesPredicate(MachineInstr *MI,
|
||||
std::vector<MachineOperand> &Pred) const override;
|
||||
|
||||
bool SubsumesPredicate(const SmallVectorImpl<MachineOperand> &Pred1,
|
||||
const SmallVectorImpl<MachineOperand> &Pred2) const override;
|
||||
bool SubsumesPredicate(ArrayRef<MachineOperand> Pred1,
|
||||
ArrayRef<MachineOperand> Pred2) const override;
|
||||
|
||||
bool isProfitableToUnpredicate(MachineBasicBlock &TMBB,
|
||||
MachineBasicBlock &FMBB) const override;
|
||||
|
||||
bool PredicateInstruction(MachineInstr *MI,
|
||||
const SmallVectorImpl<MachineOperand> &Pred) const override;
|
||||
ArrayRef<MachineOperand> Pred) const override;
|
||||
|
||||
unsigned int getPredicationCost(const MachineInstr *) const override;
|
||||
|
||||
|
|
|
@ -229,7 +229,7 @@ bool SparcInstrInfo::AnalyzeBranch(MachineBasicBlock &MBB,
|
|||
unsigned
|
||||
SparcInstrInfo::InsertBranch(MachineBasicBlock &MBB,MachineBasicBlock *TBB,
|
||||
MachineBasicBlock *FBB,
|
||||
const SmallVectorImpl<MachineOperand> &Cond,
|
||||
ArrayRef<MachineOperand> Cond,
|
||||
DebugLoc DL) const {
|
||||
assert(TBB && "InsertBranch must not be told to insert a fallthrough");
|
||||
assert((Cond.size() == 1 || Cond.size() == 0) &&
|
||||
|
|
|
@ -73,8 +73,7 @@ public:
|
|||
unsigned RemoveBranch(MachineBasicBlock &MBB) const override;
|
||||
|
||||
unsigned InsertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB,
|
||||
MachineBasicBlock *FBB,
|
||||
const SmallVectorImpl<MachineOperand> &Cond,
|
||||
MachineBasicBlock *FBB, ArrayRef<MachineOperand> Cond,
|
||||
DebugLoc DL) const override;
|
||||
|
||||
void copyPhysReg(MachineBasicBlock &MBB,
|
||||
|
|
|
@ -362,7 +362,7 @@ ReverseBranchCondition(SmallVectorImpl<MachineOperand> &Cond) const {
|
|||
unsigned
|
||||
SystemZInstrInfo::InsertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB,
|
||||
MachineBasicBlock *FBB,
|
||||
const SmallVectorImpl<MachineOperand> &Cond,
|
||||
ArrayRef<MachineOperand> Cond,
|
||||
DebugLoc DL) const {
|
||||
// In this function we output 32-bit branches, which should always
|
||||
// have enough range. They can be shortened and relaxed by later code
|
||||
|
@ -530,8 +530,7 @@ isProfitableToIfCvt(MachineBasicBlock &TMBB,
|
|||
}
|
||||
|
||||
bool SystemZInstrInfo::
|
||||
PredicateInstruction(MachineInstr *MI,
|
||||
const SmallVectorImpl<MachineOperand> &Pred) const {
|
||||
PredicateInstruction(MachineInstr *MI, ArrayRef<MachineOperand> Pred) const {
|
||||
assert(Pred.size() == 2 && "Invalid condition");
|
||||
unsigned CCValid = Pred[0].getImm();
|
||||
unsigned CCMask = Pred[1].getImm();
|
||||
|
|
|
@ -149,8 +149,7 @@ public:
|
|||
bool AllowModify) const override;
|
||||
unsigned RemoveBranch(MachineBasicBlock &MBB) const override;
|
||||
unsigned InsertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB,
|
||||
MachineBasicBlock *FBB,
|
||||
const SmallVectorImpl<MachineOperand> &Cond,
|
||||
MachineBasicBlock *FBB, ArrayRef<MachineOperand> Cond,
|
||||
DebugLoc DL) const override;
|
||||
bool analyzeCompare(const MachineInstr *MI, unsigned &SrcReg,
|
||||
unsigned &SrcReg2, int &Mask, int &Value) const override;
|
||||
|
@ -167,8 +166,7 @@ public:
|
|||
unsigned NumCyclesF, unsigned ExtraPredCyclesF,
|
||||
const BranchProbability &Probability) const override;
|
||||
bool PredicateInstruction(MachineInstr *MI,
|
||||
const SmallVectorImpl<MachineOperand> &Pred) const
|
||||
override;
|
||||
ArrayRef<MachineOperand> Pred) const override;
|
||||
void copyPhysReg(MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI,
|
||||
DebugLoc DL, unsigned DestReg, unsigned SrcReg,
|
||||
bool KillSrc) const override;
|
||||
|
|
|
@ -3622,8 +3622,7 @@ unsigned X86InstrInfo::RemoveBranch(MachineBasicBlock &MBB) const {
|
|||
|
||||
unsigned
|
||||
X86InstrInfo::InsertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB,
|
||||
MachineBasicBlock *FBB,
|
||||
const SmallVectorImpl<MachineOperand> &Cond,
|
||||
MachineBasicBlock *FBB, ArrayRef<MachineOperand> Cond,
|
||||
DebugLoc DL) const {
|
||||
// Shouldn't be a fall through.
|
||||
assert(TBB && "InsertBranch must not be told to insert a fallthrough");
|
||||
|
@ -3671,7 +3670,7 @@ X86InstrInfo::InsertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB,
|
|||
|
||||
bool X86InstrInfo::
|
||||
canInsertSelect(const MachineBasicBlock &MBB,
|
||||
const SmallVectorImpl<MachineOperand> &Cond,
|
||||
ArrayRef<MachineOperand> Cond,
|
||||
unsigned TrueReg, unsigned FalseReg,
|
||||
int &CondCycles, int &TrueCycles, int &FalseCycles) const {
|
||||
// Not all subtargets have cmov instructions.
|
||||
|
@ -3708,8 +3707,7 @@ canInsertSelect(const MachineBasicBlock &MBB,
|
|||
|
||||
void X86InstrInfo::insertSelect(MachineBasicBlock &MBB,
|
||||
MachineBasicBlock::iterator I, DebugLoc DL,
|
||||
unsigned DstReg,
|
||||
const SmallVectorImpl<MachineOperand> &Cond,
|
||||
unsigned DstReg, ArrayRef<MachineOperand> Cond,
|
||||
unsigned TrueReg, unsigned FalseReg) const {
|
||||
MachineRegisterInfo &MRI = MBB.getParent()->getRegInfo();
|
||||
assert(Cond.size() == 1 && "Invalid Cond array");
|
||||
|
|
|
@ -269,16 +269,13 @@ public:
|
|||
bool AllowModify) const override;
|
||||
unsigned RemoveBranch(MachineBasicBlock &MBB) const override;
|
||||
unsigned InsertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB,
|
||||
MachineBasicBlock *FBB,
|
||||
const SmallVectorImpl<MachineOperand> &Cond,
|
||||
MachineBasicBlock *FBB, ArrayRef<MachineOperand> Cond,
|
||||
DebugLoc DL) const override;
|
||||
bool canInsertSelect(const MachineBasicBlock&,
|
||||
const SmallVectorImpl<MachineOperand> &Cond,
|
||||
bool canInsertSelect(const MachineBasicBlock&, ArrayRef<MachineOperand> Cond,
|
||||
unsigned, unsigned, int&, int&, int&) const override;
|
||||
void insertSelect(MachineBasicBlock &MBB,
|
||||
MachineBasicBlock::iterator MI, DebugLoc DL,
|
||||
unsigned DstReg,
|
||||
const SmallVectorImpl<MachineOperand> &Cond,
|
||||
unsigned DstReg, ArrayRef<MachineOperand> Cond,
|
||||
unsigned TrueReg, unsigned FalseReg) const override;
|
||||
void copyPhysReg(MachineBasicBlock &MBB,
|
||||
MachineBasicBlock::iterator MI, DebugLoc DL,
|
||||
|
|
|
@ -281,7 +281,7 @@ XCoreInstrInfo::AnalyzeBranch(MachineBasicBlock &MBB, MachineBasicBlock *&TBB,
|
|||
unsigned
|
||||
XCoreInstrInfo::InsertBranch(MachineBasicBlock &MBB,MachineBasicBlock *TBB,
|
||||
MachineBasicBlock *FBB,
|
||||
const SmallVectorImpl<MachineOperand> &Cond,
|
||||
ArrayRef<MachineOperand> Cond,
|
||||
DebugLoc DL)const{
|
||||
// Shouldn't be a fall through.
|
||||
assert(TBB && "InsertBranch must not be told to insert a fallthrough");
|
||||
|
|
|
@ -56,8 +56,7 @@ public:
|
|||
bool AllowModify) const override;
|
||||
|
||||
unsigned InsertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB,
|
||||
MachineBasicBlock *FBB,
|
||||
const SmallVectorImpl<MachineOperand> &Cond,
|
||||
MachineBasicBlock *FBB, ArrayRef<MachineOperand> Cond,
|
||||
DebugLoc DL) const override;
|
||||
|
||||
unsigned RemoveBranch(MachineBasicBlock &MBB) const override;
|
||||
|
|
Loading…
Reference in New Issue