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Use VT::getHalfNumVectorElementsVT helpers in a few places. NFCI. 

llvm-svn: 369751
This commit is contained in:
Simon Pilgrim 2019-08-23 12:37:09 +00:00
parent 8e9af64da6
commit c88408cf85
2 changed files with 6 additions and 10 deletions
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9
llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
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@ -6541,8 +6541,7 @@ static SDValue tryFormConcatFromShuffle(SDValue Op, SelectionDAG &DAG) {
if (!isConcatMask(Mask, VT, SplitV0)) if (!isConcatMask(Mask, VT, SplitV0))
return SDValue(); return SDValue();
EVT CastVT = EVT::getVectorVT(*DAG.getContext(), VT.getVectorElementType(), EVT CastVT = VT.getHalfNumVectorElementsVT(*DAG.getContext());
VT.getVectorNumElements() / 2);
if (SplitV0) { if (SplitV0) {
V0 = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, CastVT, V0, V0 = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, CastVT, V0,
DAG.getConstant(0, DL, MVT::i64)); DAG.getConstant(0, DL, MVT::i64));
@ -10610,10 +10609,10 @@ static SDValue splitStores(SDNode *N, TargetLowering::DAGCombinerInfo &DCI,
return ReplacedSplat; return ReplacedSplat;
SDLoc DL(S); SDLoc DL(S);
unsigned NumElts = VT.getVectorNumElements() / 2;
// Split VT into two. // Split VT into two.
EVT HalfVT = EVT HalfVT = VT.getHalfNumVectorElementsVT(*DAG.getContext());
EVT::getVectorVT(*DAG.getContext(), VT.getVectorElementType(), NumElts); unsigned NumElts = HalfVT.getVectorNumElements();
SDValue SubVector0 = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, HalfVT, StVal, SDValue SubVector0 = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, HalfVT, StVal,
DAG.getConstant(0, DL, MVT::i64)); DAG.getConstant(0, DL, MVT::i64));
SDValue SubVector1 = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, HalfVT, StVal, SDValue SubVector1 = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, HalfVT, StVal,

7
llvm/lib/Target/X86/X86ISelLowering.cpp
View File

@ -26543,8 +26543,7 @@ static SDValue LowerBITCAST(SDValue Op, const X86Subtarget &Subtarget,
SDLoc dl(Op); SDLoc dl(Op);
SDValue Lo, Hi; SDValue Lo, Hi;
std::tie(Lo, Hi) = DAG.SplitVector(Op.getOperand(0), dl); std::tie(Lo, Hi) = DAG.SplitVector(Op.getOperand(0), dl);
EVT CastVT = MVT::getVectorVT(DstVT.getVectorElementType(), MVT CastVT = DstVT.getHalfNumVectorElementsVT();
DstVT.getVectorNumElements() / 2);
Lo = DAG.getBitcast(CastVT, Lo); Lo = DAG.getBitcast(CastVT, Lo);
Hi = DAG.getBitcast(CastVT, Hi); Hi = DAG.getBitcast(CastVT, Hi);
return DAG.getNode(ISD::CONCAT_VECTORS, dl, DstVT, Lo, Hi); return DAG.getNode(ISD::CONCAT_VECTORS, dl, DstVT, Lo, Hi);
@ -27845,9 +27844,7 @@ void X86TargetLowering::ReplaceNodeResults(SDNode *N,
// since sign_extend_inreg i8/i16->i64 requires an extend to i32 using // since sign_extend_inreg i8/i16->i64 requires an extend to i32 using
// sra. Then extending from i32 to i64 using pcmpgt. By custom splitting // sra. Then extending from i32 to i64 using pcmpgt. By custom splitting
// we allow the sra from the extend to i32 to be shared by the split. // we allow the sra from the extend to i32 to be shared by the split.
EVT ExtractVT = EVT::getVectorVT(*DAG.getContext(), EVT ExtractVT = InVT.getHalfNumVectorElementsVT(*DAG.getContext());
InVT.getVectorElementType(),
InVT.getVectorNumElements() / 2);
MVT ExtendVT = MVT::getVectorVT(MVT::i32, MVT ExtendVT = MVT::getVectorVT(MVT::i32,
VT.getVectorNumElements()); VT.getVectorNumElements());
In = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, ExtractVT, In = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, ExtractVT,