maxjhandsome
/
llvm-project
forked from OSchip/llvm-project
1
0
Fork 0
Code Issues Pull Requests Packages Releases Wiki Activity

* Remove trailing whitespace 

* Convert tabs to spaces

llvm-svn: 21426
This commit is contained in:
Misha Brukman 2005-04-21 23:38:14 +00:00
parent b440243e94
commit c88330ad13
16 changed files with 263 additions and 262 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

4
llvm/lib/Target/X86/X86.h
View File

@ -1,10 +1,10 @@
//===-- X86.h - Top-level interface for X86 representation ------*- C++ -*-===//
//
//
// The LLVM Compiler Infrastructure
//
// This file was developed by the LLVM research group and is distributed under
// the University of Illinois Open Source License. See LICENSE.TXT for details.
//
//
//===----------------------------------------------------------------------===//
//
// This file contains the entry points for global functions defined in the x86

24
llvm/lib/Target/X86/X86AsmPrinter.cpp
View File

@ -1,10 +1,10 @@
//===-- X86AsmPrinter.cpp - Convert X86 LLVM code to Intel assembly -------===//
//
//
// The LLVM Compiler Infrastructure
//
// This file was developed by the LLVM research group and is distributed under
// the University of Illinois Open Source License. See LICENSE.TXT for details.
//
//
//===----------------------------------------------------------------------===//
//
// This file contains a printer that converts from our internal representation
@ -85,7 +85,7 @@ bool X86SharedAsmPrinter::doInitialization(Module& M) {
forCygwin = false;
const std::string& TT = M.getTargetTriple();
if (TT.length() > 5)
forCygwin = TT.find("cygwin") != std::string::npos ||
forCygwin = TT.find("cygwin") != std::string::npos ||
TT.find("mingw") != std::string::npos;
else if (TT.empty()) {
#if defined(__CYGWIN__) || defined(__MINGW32__)
@ -107,7 +107,7 @@ bool X86SharedAsmPrinter::doInitialization(Module& M) {
void X86SharedAsmPrinter::printConstantPool(MachineConstantPool *MCP) {
const std::vector<Constant*> &CP = MCP->getConstants();
const TargetData &TD = TM.getTargetData();
if (CP.empty()) return;
for (unsigned i = 0, e = CP.size(); i != e; ++i) {
@ -132,13 +132,13 @@ bool X86SharedAsmPrinter::doFinalization(Module &M) {
unsigned Size = TD.getTypeSize(C->getType());
unsigned Align = TD.getTypeAlignmentShift(C->getType());
if (C->isNullValue() &&
if (C->isNullValue() &&
(I->hasLinkOnceLinkage() || I->hasInternalLinkage() ||
I->hasWeakLinkage() /* FIXME: Verify correct */)) {
SwitchSection(O, CurSection, ".data");
if (!forCygwin && I->hasInternalLinkage())
O << "\t.local " << name << "\n";
O << "\t.comm " << name << "," << TD.getTypeSize(C->getType());
if (!forCygwin)
O << "," << (1 << Align);
@ -240,7 +240,7 @@ namespace {
void printMachineInstruction(const MachineInstr *MI);
void printOp(const MachineOperand &MO, bool elideOffsetKeyword = false);
void printMemReference(const MachineInstr *MI, unsigned Op);
bool runOnMachineFunction(MachineFunction &F);
bool runOnMachineFunction(MachineFunction &F);
bool doInitialization(Module &M);
};
} // end of anonymous namespace
@ -335,7 +335,7 @@ void X86IntelAsmPrinter::printOp(const MachineOperand &MO,
O << GlobalPrefix << MO.getSymbolName();
return;
default:
O << "<unknown operand type>"; return;
O << "<unknown operand type>"; return;
}
}
@ -363,7 +363,7 @@ void X86IntelAsmPrinter::printMemReference(const MachineInstr *MI, unsigned Op){
O << ScaleVal << "*";
printOp(IndexReg);
}
if (DispSpec.getImmedValue())
O << " + " << DispSpec.getImmedValue();
O << "]";
@ -465,7 +465,7 @@ namespace {
void printMachineInstruction(const MachineInstr *MI);
void printOp(const MachineOperand &MO, bool isCallOperand = false);
void printMemReference(const MachineInstr *MI, unsigned Op);
bool runOnMachineFunction(MachineFunction &F);
bool runOnMachineFunction(MachineFunction &F);
};
} // end of anonymous namespace
@ -553,7 +553,7 @@ void X86ATTAsmPrinter::printOp(const MachineOperand &MO, bool isCallOp) {
O << GlobalPrefix << MO.getSymbolName();
return;
default:
O << "<unknown operand type>"; return;
O << "<unknown operand type>"; return;
}
}
@ -627,7 +627,7 @@ void X86ATTAsmPrinter::printMachineInstruction(const MachineInstr *MI) {
///
FunctionPass *llvm::createX86CodePrinterPass(std::ostream &o,TargetMachine &tm){
switch (AsmWriterFlavor) {
default:
default:
assert(0 && "Unknown asm flavor!");
case intel:
return new X86IntelAsmPrinter(o, tm);

8
llvm/lib/Target/X86/X86CodeEmitter.cpp
View File

@ -1,10 +1,10 @@
//===-- X86/X86CodeEmitter.cpp - Convert X86 code to machine code ---------===//
//
//
// The LLVM Compiler Infrastructure
//
// This file was developed by the LLVM research group and is distributed under
// the University of Illinois Open Source License. See LICENSE.TXT for details.
//
//
//===----------------------------------------------------------------------===//
//
// This file contains the pass that transforms the X86 machine instructions into
@ -398,7 +398,7 @@ void Emitter::emitInstruction(const MachineInstr &MI) {
} else if (MO.isExternalSymbol()) {
emitExternalSymbolAddress(MO.getSymbolName(), true);
} else if (MO.isImmediate()) {
emitConstant(MO.getImmedValue(), sizeOfImm(Desc));
emitConstant(MO.getImmedValue(), sizeOfImm(Desc));
} else {
assert(0 && "Unknown RawFrm operand!");
}
@ -476,7 +476,7 @@ void Emitter::emitInstruction(const MachineInstr &MI) {
case X86II::MRM0m: case X86II::MRM1m:
case X86II::MRM2m: case X86II::MRM3m:
case X86II::MRM4m: case X86II::MRM5m:
case X86II::MRM6m: case X86II::MRM7m:
case X86II::MRM6m: case X86II::MRM7m:
MCE.emitByte(BaseOpcode);
emitMemModRMByte(MI, 0, (Desc.TSFlags & X86II::FormMask)-X86II::MRM0m);

83
llvm/lib/Target/X86/X86FloatingPoint.cpp
View File

@ -1,10 +1,10 @@
//===-- X86FloatingPoint.cpp - Floating point Reg -> Stack converter ------===//
//
//
// The LLVM Compiler Infrastructure
//
// This file was developed by the LLVM research group and is distributed under
// the University of Illinois Open Source License. See LICENSE.TXT for details.
//
//
//===----------------------------------------------------------------------===//
//
// This file defines the pass which converts floating point instructions from
@ -68,8 +68,8 @@ namespace {
void dumpStack() const {
std::cerr << "Stack contents:";
for (unsigned i = 0; i != StackTop; ++i) {
std::cerr << " FP" << Stack[i];
assert(RegMap[Stack[i]] == i && "Stack[] doesn't match RegMap[]!");
std::cerr << " FP" << Stack[i];
assert(RegMap[Stack[i]] == i && "Stack[] doesn't match RegMap[]!");
}
std::cerr << "\n";
}
@ -104,20 +104,20 @@ namespace {
bool isAtTop(unsigned RegNo) const { return getSlot(RegNo) == StackTop-1; }
void moveToTop(unsigned RegNo, MachineBasicBlock::iterator &I) {
if (!isAtTop(RegNo)) {
unsigned Slot = getSlot(RegNo);
unsigned STReg = getSTReg(RegNo);
unsigned RegOnTop = getStackEntry(0);
unsigned Slot = getSlot(RegNo);
unsigned STReg = getSTReg(RegNo);
unsigned RegOnTop = getStackEntry(0);
// Swap the slots the regs are in
std::swap(RegMap[RegNo], RegMap[RegOnTop]);
// Swap the slots the regs are in
std::swap(RegMap[RegNo], RegMap[RegOnTop]);
// Swap stack slot contents
assert(RegMap[RegOnTop] < StackTop);
std::swap(Stack[RegMap[RegOnTop]], Stack[StackTop-1]);
// Swap stack slot contents
assert(RegMap[RegOnTop] < StackTop);
std::swap(Stack[RegMap[RegOnTop]], Stack[StackTop-1]);
// Emit an fxch to update the runtime processors version of the state
BuildMI(*MBB, I, X86::FXCH, 1).addReg(STReg);
NumFXCH++;
// Emit an fxch to update the runtime processors version of the state
BuildMI(*MBB, I, X86::FXCH, 1).addReg(STReg);
NumFXCH++;
}
}
@ -196,7 +196,7 @@ bool FPS::processBasicBlock(MachineFunction &MF, MachineBasicBlock &BB) {
const TargetInstrInfo &TII = *MF.getTarget().getInstrInfo();
bool Changed = false;
MBB = &BB;
for (MachineBasicBlock::iterator I = BB.begin(); I != BB.end(); ++I) {
MachineInstr *MI = I;
unsigned Flags = TII.get(MI->getOpcode()).TSFlags;
@ -208,23 +208,24 @@ bool FPS::processBasicBlock(MachineFunction &MF, MachineBasicBlock &BB) {
PrevMI = prior(I);
++NumFP; // Keep track of # of pseudo instrs
DEBUG(std::cerr << "\nFPInst:\t";
MI->print(std::cerr, &(MF.getTarget())));
DEBUG(std::cerr << "\nFPInst:\t"; MI->print(std::cerr, &(MF.getTarget())));
// Get dead variables list now because the MI pointer may be deleted as part
// of processing!
LiveVariables::killed_iterator IB = LV->dead_begin(MI);
LiveVariables::killed_iterator IE = LV->dead_end(MI);
DEBUG(const MRegisterInfo *MRI = MF.getTarget().getRegisterInfo();
LiveVariables::killed_iterator I = LV->killed_begin(MI);
LiveVariables::killed_iterator E = LV->killed_end(MI);
if (I != E) {
std::cerr << "Killed Operands:";
for (; I != E; ++I)
std::cerr << " %" << MRI->getName(I->second);
std::cerr << "\n";
});
DEBUG(
const MRegisterInfo *MRI = MF.getTarget().getRegisterInfo();
LiveVariables::killed_iterator I = LV->killed_begin(MI);
LiveVariables::killed_iterator E = LV->killed_end(MI);
if (I != E) {
std::cerr << "Killed Operands:";
for (; I != E; ++I)
std::cerr << " %" << MRI->getName(I->second);
std::cerr << "\n";
}
);
switch (Flags & X86II::FPTypeMask) {
case X86II::ZeroArgFP: handleZeroArgFP(I); break;
@ -242,11 +243,11 @@ bool FPS::processBasicBlock(MachineFunction &MF, MachineBasicBlock &BB) {
for (; IB != IE; ++IB) {
unsigned Reg = IB->second;
if (Reg >= X86::FP0 && Reg <= X86::FP6) {
DEBUG(std::cerr << "Register FP#" << Reg-X86::FP0 << " is dead!\n");
DEBUG(std::cerr << "Register FP#" << Reg-X86::FP0 << " is dead!\n");
freeStackSlotAfter(I, Reg-X86::FP0);
}
}
// Print out all of the instructions expanded to if -debug
DEBUG(
MachineBasicBlock::iterator PrevI(PrevMI);
@ -423,7 +424,7 @@ void FPS::handleOneArgFP(MachineBasicBlock::iterator &I) {
unsigned Reg = getFPReg(MI->getOperand(MI->getNumOperands()-1));
bool KillsSrc = false;
for (LiveVariables::killed_iterator KI = LV->killed_begin(MI),
E = LV->killed_end(MI); KI != E; ++KI)
E = LV->killed_end(MI); KI != E; ++KI)
KillsSrc |= KI->second == X86::FP0+Reg;
// FSTP80r and FISTP64r are strange because there are no non-popping versions.
@ -438,7 +439,7 @@ void FPS::handleOneArgFP(MachineBasicBlock::iterator &I) {
moveToTop(Reg, I); // Move to the top of the stack...
}
MI->RemoveOperand(MI->getNumOperands()-1); // Remove explicit ST(0) operand
if (MI->getOpcode() == X86::FSTP80m || MI->getOpcode() == X86::FISTP64m) {
assert(StackTop > 0 && "Stack empty??");
--StackTop;
@ -464,7 +465,7 @@ void FPS::handleOneArgFPRW(MachineBasicBlock::iterator &I) {
unsigned Reg = getFPReg(MI->getOperand(1));
bool KillsSrc = false;
for (LiveVariables::killed_iterator KI = LV->killed_begin(MI),
E = LV->killed_end(MI); KI != E; ++KI)
E = LV->killed_end(MI); KI != E; ++KI)
KillsSrc |= KI->second == X86::FP0+Reg;
if (KillsSrc) {
@ -529,7 +530,7 @@ static const TableEntry ReverseSTiTable[] = {
/// ST(i) = fsub ST(0), ST(i)
/// ST(0) = fsubr ST(0), ST(i)
/// ST(i) = fsubr ST(0), ST(i)
///
///
void FPS::handleTwoArgFP(MachineBasicBlock::iterator &I) {
ASSERT_SORTED(ForwardST0Table); ASSERT_SORTED(ReverseST0Table);
ASSERT_SORTED(ForwardSTiTable); ASSERT_SORTED(ReverseSTiTable);
@ -543,7 +544,7 @@ void FPS::handleTwoArgFP(MachineBasicBlock::iterator &I) {
bool KillsOp0 = false, KillsOp1 = false;
for (LiveVariables::killed_iterator KI = LV->killed_begin(MI),
E = LV->killed_end(MI); KI != E; ++KI) {
E = LV->killed_end(MI); KI != E; ++KI) {
KillsOp0 |= (KI->second == X86::FP0+Op0);
KillsOp1 |= (KI->second == X86::FP0+Op1);
}
@ -583,8 +584,8 @@ void FPS::handleTwoArgFP(MachineBasicBlock::iterator &I) {
// Now we know that one of our operands is on the top of the stack, and at
// least one of our operands is killed by this instruction.
assert((TOS == Op0 || TOS == Op1) && (KillsOp0 || KillsOp1) &&
"Stack conditions not set up right!");
assert((TOS == Op0 || TOS == Op1) && (KillsOp0 || KillsOp1) &&
"Stack conditions not set up right!");
// We decide which form to use based on what is on the top of the stack, and
// which operand is killed by this instruction.
@ -602,7 +603,7 @@ void FPS::handleTwoArgFP(MachineBasicBlock::iterator &I) {
else
InstTable = ReverseSTiTable;
}
int Opcode = Lookup(InstTable, ARRAY_SIZE(ForwardST0Table), MI->getOpcode());
assert(Opcode != -1 && "Unknown TwoArgFP pseudo instruction!");
@ -631,7 +632,7 @@ void FPS::handleTwoArgFP(MachineBasicBlock::iterator &I) {
/// handleCompareFP - Handle FUCOM and FUCOMI instructions, which have two FP
/// register arguments and no explicit destinations.
///
///
void FPS::handleCompareFP(MachineBasicBlock::iterator &I) {
ASSERT_SORTED(ForwardST0Table); ASSERT_SORTED(ReverseST0Table);
ASSERT_SORTED(ForwardSTiTable); ASSERT_SORTED(ReverseSTiTable);
@ -644,7 +645,7 @@ void FPS::handleCompareFP(MachineBasicBlock::iterator &I) {
bool KillsOp0 = false, KillsOp1 = false;
for (LiveVariables::killed_iterator KI = LV->killed_begin(MI),
E = LV->killed_end(MI); KI != E; ++KI) {
E = LV->killed_end(MI); KI != E; ++KI) {
KillsOp0 |= (KI->second == X86::FP0+Op0);
KillsOp1 |= (KI->second == X86::FP0+Op1);
}
@ -679,7 +680,7 @@ void FPS::handleCondMovFP(MachineBasicBlock::iterator &I) {
MI->getOperand(0).setReg(getSTReg(Op1));
// If we kill the second operand, make sure to pop it from the stack.
if (Op0 != Op1)
if (Op0 != Op1)
for (LiveVariables::killed_iterator KI = LV->killed_begin(MI),
E = LV->killed_end(MI); KI != E; ++KI)
if (KI->second == X86::FP0+Op1) {
@ -711,7 +712,7 @@ void FPS::handleSpecialFP(MachineBasicBlock::iterator &I) {
unsigned DestReg = getFPReg(MI->getOperand(0));
bool KillsSrc = false;
for (LiveVariables::killed_iterator KI = LV->killed_begin(MI),
E = LV->killed_end(MI); KI != E; ++KI)
E = LV->killed_end(MI); KI != E; ++KI)
KillsSrc |= KI->second == X86::FP0+SrcReg;
if (KillsSrc) {

116
llvm/lib/Target/X86/X86ISelPattern.cpp
View File

@ -4,7 +4,7 @@
//
// This file was developed by the LLVM research group and is distributed under
// the University of Illinois Open Source License. See LICENSE.TXT for details.
//
//
//===----------------------------------------------------------------------===//
//
// This file defines a pattern matching instruction selector for X86.
@ -51,7 +51,7 @@ namespace {
addRegisterClass(MVT::i16, X86::R16RegisterClass);
addRegisterClass(MVT::i32, X86::R32RegisterClass);
addRegisterClass(MVT::f64, X86::RFPRegisterClass);
// FIXME: Eliminate these two classes when legalize can handle promotions
// well.
/**/ addRegisterClass(MVT::i1, X86::R8RegisterClass);
@ -67,9 +67,9 @@ namespace {
// These should be promoted to a larger select which is supported.
/**/ setOperationAction(ISD::SELECT , MVT::i1 , Promote);
setOperationAction(ISD::SELECT , MVT::i8 , Promote);
computeRegisterProperties();
addLegalFPImmediate(+0.0); // FLD0
addLegalFPImmediate(+1.0); // FLD1
addLegalFPImmediate(-0.0); // FLD0/FCHS
@ -111,11 +111,11 @@ X86TargetLowering::LowerArguments(Function &F, SelectionDAG &DAG) {
// [ESP] -- return address
// [ESP + 4] -- first argument (leftmost lexically)
// [ESP + 8] -- second argument, if first argument is four bytes in size
// ...
// ...
//
MachineFunction &MF = DAG.getMachineFunction();
MachineFrameInfo *MFI = MF.getFrameInfo();
unsigned ArgOffset = 0; // Frame mechanisms handle retaddr slot
for (Function::arg_iterator I = F.arg_begin(), E = F.arg_end(); I != E; ++I) {
MVT::ValueType ObjectVT = getValueType(I->getType());
@ -133,7 +133,7 @@ X86TargetLowering::LowerArguments(Function &F, SelectionDAG &DAG) {
}
// Create the frame index object for this incoming parameter...
int FI = MFI->CreateFixedObject(ObjSize, ArgOffset);
// Create the SelectionDAG nodes corresponding to a load from this parameter
SDOperand FIN = DAG.getFrameIndex(FI, MVT::i32);
@ -293,7 +293,7 @@ LowerVAArgNext(bool isVANext, SDOperand Chain, SDOperand VAList,
}
return std::make_pair(Result, Chain);
}
std::pair<SDOperand, SDOperand> X86TargetLowering::
LowerFrameReturnAddress(bool isFrameAddress, SDOperand Chain, unsigned Depth,
@ -307,7 +307,7 @@ LowerFrameReturnAddress(bool isFrameAddress, SDOperand Chain, unsigned Depth,
MachineFunction &MF = DAG.getMachineFunction();
ReturnAddrIndex = MF.getFrameInfo()->CreateFixedObject(4, -4);
}
SDOperand RetAddrFI = DAG.getFrameIndex(ReturnAddrIndex, MVT::i32);
if (!isFrameAddress)
@ -330,17 +330,17 @@ namespace {
RegBase,
FrameIndexBase,
} BaseType;
struct { // This is really a union, discriminated by BaseType!
SDOperand Reg;
int FrameIndex;
} Base;
unsigned Scale;
SDOperand IndexReg;
unsigned Disp;
GlobalValue *GV;
X86ISelAddressMode()
: BaseType(RegBase), Scale(1), IndexReg(), Disp(), GV(0) {
}
@ -451,7 +451,7 @@ void ISel::InstructionSelectBasicBlock(SelectionDAG &DAG) {
break;
}
}
// Insert FP_REG_KILL instructions into basic blocks that need them. This
// only occurs due to the floating point stackifier not being aggressive
// enough to handle arbitrary global stackification.
@ -468,7 +468,7 @@ void ISel::InstructionSelectBasicBlock(SelectionDAG &DAG) {
BuildMI(*BB, BB->getFirstTerminator(), X86::FP_REG_KILL, 0);
++NumFPKill;
}
// Clear state used for selection.
ExprMap.clear();
RegPressureMap.clear();
@ -577,7 +577,7 @@ X86AddressMode ISel::SelectAddrExprs(const X86ISelAddressMode &IAM) {
} else if (IAM.IndexReg.Val) {
Result.IndexReg = SelectExpr(IAM.IndexReg);
}
switch (IAM.BaseType) {
case X86ISelAddressMode::RegBase:
Result.BaseType = X86AddressMode::RegBase;
@ -679,7 +679,7 @@ bool ISel::MatchAddress(SDOperand N, X86ISelAddressMode &AM) {
ConstantSDNode *AddVal =
cast<ConstantSDNode>(MulVal.Val->getOperand(1));
AM.Disp += AddVal->getValue() * CN->getValue();
} else {
} else {
Reg = N.Val->getOperand(0);
}
@ -964,12 +964,12 @@ void ISel::EmitSelectCC(SDOperand Cond, MVT::ValueType SVT,
static const unsigned CMOVTAB16[] = {
X86::CMOVE16rr, X86::CMOVNE16rr, X86::CMOVL16rr, X86::CMOVLE16rr,
X86::CMOVG16rr, X86::CMOVGE16rr, X86::CMOVB16rr, X86::CMOVBE16rr,
X86::CMOVA16rr, X86::CMOVAE16rr, X86::CMOVP16rr, X86::CMOVNP16rr,
X86::CMOVA16rr, X86::CMOVAE16rr, X86::CMOVP16rr, X86::CMOVNP16rr,
};
static const unsigned CMOVTAB32[] = {
X86::CMOVE32rr, X86::CMOVNE32rr, X86::CMOVL32rr, X86::CMOVLE32rr,
X86::CMOVG32rr, X86::CMOVGE32rr, X86::CMOVB32rr, X86::CMOVBE32rr,
X86::CMOVA32rr, X86::CMOVAE32rr, X86::CMOVP32rr, X86::CMOVNP32rr,
X86::CMOVA32rr, X86::CMOVAE32rr, X86::CMOVP32rr, X86::CMOVNP32rr,
};
static const unsigned CMOVTABFP[] = {
X86::FCMOVE , X86::FCMOVNE, /*missing*/0, /*missing*/0,
@ -1318,7 +1318,7 @@ bool ISel::EmitOrOpOp(SDOperand Op1, SDOperand Op2, unsigned DestReg) {
return true;
}
}
return false;
}
@ -1335,10 +1335,10 @@ unsigned ISel::SelectExpr(SDOperand N) {
// Just use the specified register as our input.
return dyn_cast<RegSDNode>(Node)->getReg();
}
unsigned &Reg = ExprMap[N];
if (Reg) return Reg;
switch (N.getOpcode()) {
default:
Reg = Result = (N.getValueType() != MVT::Other) ?
@ -1368,7 +1368,7 @@ unsigned ISel::SelectExpr(SDOperand N) {
ExprMap[N.getValue(i)] = MakeReg(Node->getValueType(i));
break;
}
switch (N.getOpcode()) {
default:
Node->dump();
@ -1447,7 +1447,7 @@ unsigned ISel::SelectExpr(SDOperand N) {
X86AddressMode AM;
EmitFoldedLoad(N.getOperand(0), AM);
addFullAddress(BuildMI(BB, Opc[SrcIs16+DestIs16*2], 4, Result), AM);
return Result;
}
@ -1457,7 +1457,7 @@ unsigned ISel::SelectExpr(SDOperand N) {
Tmp1 = SelectExpr(N.getOperand(0));
BuildMI(BB, Opc[SrcIs16+DestIs16*2], 1, Result).addReg(Tmp1);
return Result;
}
}
case ISD::SIGN_EXTEND: {
int DestIs16 = N.getValueType() == MVT::i16;
int SrcIs16 = N.getOperand(0).getValueType() == MVT::i16;
@ -1556,7 +1556,7 @@ unsigned ISel::SelectExpr(SDOperand N) {
}
Tmp1 = SelectExpr(N.getOperand(0)); // Get the operand register
if (PromoteType != MVT::Other) {
Tmp2 = MakeReg(PromoteType);
BuildMI(BB, PromoteOpcode, 1, Tmp2).addReg(Tmp1);
@ -1622,11 +1622,11 @@ unsigned ISel::SelectExpr(SDOperand N) {
MachineConstantPool *CP = F->getConstantPool();
unsigned Zero = MakeReg(MVT::i32);
Constant *Null = Constant::getNullValue(Type::UIntTy);
addConstantPoolReference(BuildMI(BB, X86::LEA32r, 5, Zero),
addConstantPoolReference(BuildMI(BB, X86::LEA32r, 5, Zero),
CP->getConstantPoolIndex(Null));
unsigned Offset = MakeReg(MVT::i32);
Constant *OffsetCst = ConstantUInt::get(Type::UIntTy, 0x5f800000);
addConstantPoolReference(BuildMI(BB, X86::LEA32r, 5, Offset),
CP->getConstantPoolIndex(OffsetCst));
unsigned Addr = MakeReg(MVT::i32);
@ -1664,7 +1664,7 @@ unsigned ISel::SelectExpr(SDOperand N) {
// Reload the modified control word now...
addFrameReference(BuildMI(BB, X86::FLDCW16m, 4), CWFrameIdx);
// Restore the memory image of control word to original value
addFrameReference(BuildMI(BB, X86::MOV8mr, 5),
CWFrameIdx, 1).addReg(HighPartOfCW);
@ -1850,7 +1850,7 @@ unsigned ISel::SelectExpr(SDOperand N) {
unsigned MovOpc, LowReg, HiReg;
switch (N.getValueType()) {
default: assert(0 && "Unsupported VT!");
case MVT::i8:
case MVT::i8:
MovOpc = X86::MOV8rr;
LowReg = X86::AL;
HiReg = X86::AH;
@ -1887,7 +1887,7 @@ unsigned ISel::SelectExpr(SDOperand N) {
BuildMI(BB, Opc, 1).addReg(Tmp2);
BuildMI(BB, MovOpc, 1, Result).addReg(HiReg);
return Result;
}
}
case ISD::SUB:
case ISD::MUL:
@ -1907,7 +1907,7 @@ unsigned ISel::SelectExpr(SDOperand N) {
static const unsigned ANDTab[] = {
X86::AND8ri, X86::AND16ri, X86::AND32ri, 0, 0,
X86::AND8rm, X86::AND16rm, X86::AND32rm, 0, 0,
X86::AND8rr, X86::AND16rr, X86::AND32rr, 0, 0,
X86::AND8rr, X86::AND16rr, X86::AND32rr, 0, 0,
};
static const unsigned ORTab[] = {
X86::OR8ri, X86::OR16ri, X86::OR32ri, 0, 0,
@ -2140,12 +2140,12 @@ unsigned ISel::SelectExpr(SDOperand N) {
.addReg(ShiftOpLo);
// TmpReg3 = shl inLo, CL
BuildMI(BB, X86::SHL32rCL, 1, TmpReg3).addReg(ShiftOpLo);
// Set the flags to indicate whether the shift was by more than 32 bits.
BuildMI(BB, X86::TEST8ri, 2).addReg(X86::CL).addImm(32);
// DestHi = (>32) ? TmpReg3 : TmpReg2;
BuildMI(BB, X86::CMOVNE32rr, 2,
BuildMI(BB, X86::CMOVNE32rr, 2,
Result+1).addReg(TmpReg2).addReg(TmpReg3);
// DestLo = (>32) ? TmpReg : TmpReg3;
BuildMI(BB, X86::CMOVNE32rr, 2,
@ -2155,19 +2155,19 @@ unsigned ISel::SelectExpr(SDOperand N) {
BuildMI(BB, X86::SHRD32rrCL,2,TmpReg2).addReg(ShiftOpLo)
.addReg(ShiftOpHi);
// TmpReg3 = s[ah]r inHi, CL
BuildMI(BB, N.getOpcode() == ISD::SRA_PARTS ? X86::SAR32rCL
BuildMI(BB, N.getOpcode() == ISD::SRA_PARTS ? X86::SAR32rCL
: X86::SHR32rCL, 1, TmpReg3)
.addReg(ShiftOpHi);
// Set the flags to indicate whether the shift was by more than 32 bits.
BuildMI(BB, X86::TEST8ri, 2).addReg(X86::CL).addImm(32);
// DestLo = (>32) ? TmpReg3 : TmpReg2;
BuildMI(BB, X86::CMOVNE32rr, 2,
BuildMI(BB, X86::CMOVNE32rr, 2,
Result).addReg(TmpReg2).addReg(TmpReg3);
// DestHi = (>32) ? TmpReg : TmpReg3;
BuildMI(BB, X86::CMOVNE32rr, 2,
BuildMI(BB, X86::CMOVNE32rr, 2,
Result+1).addReg(TmpReg3).addReg(TmpReg);
}
return Result+N.ResNo;
@ -2258,7 +2258,7 @@ unsigned ISel::SelectExpr(SDOperand N) {
BuildMI(BB, SHROpc, 2, TmpReg2).addReg(TmpReg).addImm(32-Log);
unsigned TmpReg3 = MakeReg(N.getValueType());
BuildMI(BB, ADDOpc, 2, TmpReg3).addReg(Tmp1).addReg(TmpReg2);
unsigned TmpReg4 = isNeg ? MakeReg(N.getValueType()) : Result;
BuildMI(BB, SAROpc, 2, TmpReg4).addReg(TmpReg3).addImm(Log);
if (isNeg)
@ -2322,7 +2322,7 @@ unsigned ISel::SelectExpr(SDOperand N) {
}
// Emit the DIV/IDIV instruction.
BuildMI(BB, DivOpcode, 1).addReg(Tmp2);
BuildMI(BB, DivOpcode, 1).addReg(Tmp2);
// Get the result of the divide or rem.
BuildMI(BB, MovOpcode, 1, Result).addReg(isDiv ? LoReg : HiReg);
@ -2342,7 +2342,7 @@ unsigned ISel::SelectExpr(SDOperand N) {
BuildMI(BB, Opc, 2, Result).addReg(Tmp1).addReg(Tmp1);
return Result;
}
switch (N.getValueType()) {
default: assert(0 && "Cannot shift this type!");
case MVT::i8: Opc = X86::SHL8ri; break;
@ -2592,7 +2592,7 @@ unsigned ISel::SelectExpr(SDOperand N) {
<< " the stack alignment yet!";
abort();
}
if (ConstantSDNode *CN = dyn_cast<ConstantSDNode>(N.getOperand(1))) {
Select(N.getOperand(0));
BuildMI(BB, X86::SUB32ri, 2, X86::ESP).addReg(X86::ESP)
@ -2759,7 +2759,7 @@ bool ISel::TryToFoldLoadOpStore(SDNode *Node) {
X86::SHR8mi, X86::SHR16mi, X86::SHR32mi,
/*Have to put the reg in CL*/0, 0, 0,
};
const unsigned *TabPtr = 0;
switch (StVal.getOpcode()) {
default:
@ -2770,7 +2770,7 @@ bool ISel::TryToFoldLoadOpStore(SDNode *Node) {
case ISD::UDIV:
case ISD::SREM:
case ISD::UREM: return false;
case ISD::ADD: TabPtr = ADDTAB; break;
case ISD::SUB: TabPtr = SUBTAB; break;
case ISD::AND: TabPtr = ANDTAB; break;
@ -2780,7 +2780,7 @@ bool ISel::TryToFoldLoadOpStore(SDNode *Node) {
case ISD::SRA: TabPtr = SARTAB; break;
case ISD::SRL: TabPtr = SHRTAB; break;
}
// Handle: [mem] op= CST
SDOperand Op0 = StVal.getOperand(0);
SDOperand Op1 = StVal.getOperand(1);
@ -2793,7 +2793,7 @@ bool ISel::TryToFoldLoadOpStore(SDNode *Node) {
case MVT::i16: Opc = TabPtr[1]; break;
case MVT::i32: Opc = TabPtr[2]; break;
}
if (Opc) {
if (!ExprMap.insert(std::make_pair(TheLoad.getValue(1), 1)).second)
assert(0 && "Already emitted?");
@ -2807,7 +2807,7 @@ bool ISel::TryToFoldLoadOpStore(SDNode *Node) {
} else {
SelectAddress(TheLoad.getOperand(1), AM);
Select(TheLoad.getOperand(0));
}
}
if (StVal.getOpcode() == ISD::ADD) {
if (CN->getValue() == 1) {
@ -2838,19 +2838,19 @@ bool ISel::TryToFoldLoadOpStore(SDNode *Node) {
}
}
}
addFullAddress(BuildMI(BB, Opc, 4+1),AM).addImm(CN->getValue());
return true;
}
}
// If we have [mem] = V op [mem], try to turn it into:
// [mem] = [mem] op V.
if (Op1 == TheLoad && StVal.getOpcode() != ISD::SUB &&
StVal.getOpcode() != ISD::SHL && StVal.getOpcode() != ISD::SRA &&
StVal.getOpcode() != ISD::SRL)
std::swap(Op0, Op1);
if (Op0 != TheLoad) return false;
switch (Op0.getValueType()) {
@ -2892,7 +2892,7 @@ void ISel::Select(SDOperand N) {
case ISD::EntryToken: return; // Noop
case ISD::TokenFactor:
if (Node->getNumOperands() == 2) {
bool OneFirst =
bool OneFirst =
getRegPressure(Node->getOperand(1))>getRegPressure(Node->getOperand(0));
Select(Node->getOperand(OneFirst));
Select(Node->getOperand(!OneFirst));
@ -2915,7 +2915,7 @@ void ISel::Select(SDOperand N) {
Select(N.getOperand(0));
}
Tmp2 = cast<RegSDNode>(N)->getReg();
if (Tmp1 != Tmp2) {
switch (N.getOperand(1).getValueType()) {
default: assert(0 && "Invalid type for operation!");
@ -3077,7 +3077,7 @@ void ISel::Select(SDOperand N) {
case MVT::i1: Opc = X86::MOV8mr; break;
case MVT::f32: Opc = X86::FST32m; break;
}
std::vector<std::pair<unsigned, unsigned> > RP;
RP.push_back(std::make_pair(getRegPressure(N.getOperand(0)), 0));
RP.push_back(std::make_pair(getRegPressure(N.getOperand(1)), 1));
@ -3148,7 +3148,7 @@ void ISel::Select(SDOperand N) {
case MVT::i32: Opc = X86::MOV32mr; break;
case MVT::f64: Opc = X86::FST64m; break;
}
std::vector<std::pair<unsigned, unsigned> > RP;
RP.push_back(std::make_pair(getRegPressure(N.getOperand(0)), 0));
RP.push_back(std::make_pair(getRegPressure(N.getOperand(1)), 1));
@ -3171,7 +3171,7 @@ void ISel::Select(SDOperand N) {
case ISD::ADJCALLSTACKUP:
Select(N.getOperand(0));
Tmp1 = cast<ConstantSDNode>(N.getOperand(1))->getValue();
Opc = N.getOpcode() == ISD::ADJCALLSTACKDOWN ? X86::ADJCALLSTACKDOWN :
X86::ADJCALLSTACKUP;
BuildMI(BB, Opc, 1).addImm(Tmp1);
@ -3291,5 +3291,5 @@ void ISel::Select(SDOperand N) {
/// description file.
///
FunctionPass *llvm::createX86PatternInstructionSelector(TargetMachine &TM) {
return new ISel(TM);
return new ISel(TM);
}

214
llvm/lib/Target/X86/X86ISelSimple.cpp
View File

@ -1,10 +1,10 @@
//===-- X86ISelSimple.cpp - A simple instruction selector for x86 ---------===//
//
//
// The LLVM Compiler Infrastructure
//
// This file was developed by the LLVM research group and is distributed under
// the University of Illinois Open Source License. See LICENSE.TXT for details.
//
//
//===----------------------------------------------------------------------===//
//
// This file defines a simple peephole instruction selector for the x86 target
@ -217,8 +217,8 @@ namespace {
MachineBasicBlock *MBB,
MachineBasicBlock::iterator MBBI);
void visitSelectInst(SelectInst &SI);
// Memory Instructions
void visitLoadInst(LoadInst &I);
void visitStoreInst(StoreInst &I);
@ -226,7 +226,7 @@ namespace {
void visitAllocaInst(AllocaInst &I);
void visitMallocInst(MallocInst &I);
void visitFreeInst(FreeInst &I);
// Other operators
void visitShiftInst(ShiftInst &I);
void visitPHINode(PHINode &I) {} // PHI nodes handled by second pass
@ -295,7 +295,7 @@ namespace {
void doMultiply(MachineBasicBlock *MBB, MachineBasicBlock::iterator MBBI,
unsigned DestReg, const Type *DestTy,
unsigned Op0Reg, unsigned Op1Reg);
void doMultiplyConst(MachineBasicBlock *MBB,
void doMultiplyConst(MachineBasicBlock *MBB,
MachineBasicBlock::iterator MBBI,
unsigned DestReg, const Type *DestTy,
unsigned Op0Reg, unsigned Op1Val);
@ -323,11 +323,11 @@ namespace {
// Emit code for a 'SHLD DestReg, Op0, Op1, Amt' operation, where Amt is a
// constant.
void doSHLDConst(MachineBasicBlock *MBB,
void doSHLDConst(MachineBasicBlock *MBB,
MachineBasicBlock::iterator MBBI,
unsigned DestReg, unsigned Op0Reg, unsigned Op1Reg,
unsigned Op1Val);
/// emitSelectOperation - Common code shared between visitSelectInst and the
/// constant expression support.
void emitSelectOperation(MachineBasicBlock *MBB,
@ -414,7 +414,7 @@ unsigned X86ISel::getReg(Value *V, MachineBasicBlock *MBB,
} else if (CastInst *CI = dyn_cast<CastInst>(V)) {
// Do not emit noop casts at all, unless it's a double -> float cast.
if (getClassB(CI->getType()) == getClassB(CI->getOperand(0)->getType()) &&
(CI->getType() != Type::FloatTy ||
(CI->getType() != Type::FloatTy ||
CI->getOperand(0)->getType() != Type::DoubleTy))
return getReg(CI->getOperand(0), MBB, IPt);
} else if (AllocaInst *AI = dyn_castFixedAlloca(V)) {
@ -448,7 +448,7 @@ unsigned X86ISel::getFixedSizedAllocaFI(AllocaInst *AI) {
unsigned TySize = TM.getTargetData().getTypeSize(Ty);
TySize *= CUI->getValue(); // Get total allocated size...
unsigned Alignment = TM.getTargetData().getTypeAlignment(Ty);
// Create a new stack object using the frame manager...
int FrameIdx = F->getFrameInfo()->CreateStackObject(TySize, Alignment);
AllocaMap.insert(I, std::make_pair(AI, FrameIdx));
@ -563,11 +563,11 @@ void X86ISel::copyConstantToRegister(MachineBasicBlock *MBB,
else if (CFP->isExactlyValue(-0.0)) {
unsigned Tmp = makeAnotherReg(Type::DoubleTy);
BuildMI(*MBB, IP, X86::FLD0, 0, Tmp);
BuildMI(*MBB, IP, X86::FCHS, 1, R).addReg(Tmp);
BuildMI(*MBB, IP, X86::FCHS, 1, R).addReg(Tmp);
} else if (CFP->isExactlyValue(-1.0)) {
unsigned Tmp = makeAnotherReg(Type::DoubleTy);
BuildMI(*MBB, IP, X86::FLD1, 0, Tmp);
BuildMI(*MBB, IP, X86::FCHS, 1, R).addReg(Tmp);
BuildMI(*MBB, IP, X86::FCHS, 1, R).addReg(Tmp);
} else { // FIXME: PI, other native values
// FIXME: 2*PI -> LDPI + FADD
@ -586,7 +586,7 @@ void X86ISel::copyConstantToRegister(MachineBasicBlock *MBB,
}
unsigned CPI = CP->getConstantPoolIndex(CFP);
assert(Ty == Type::FloatTy || Ty == Type::DoubleTy && "Unknown FP type!");
unsigned LoadOpcode = Ty == Type::FloatTy ? X86::FLD32m : X86::FLD64m;
addConstantPoolReference(BuildMI(*MBB, IP, LoadOpcode, 4, R), CPI);
@ -613,7 +613,7 @@ void X86ISel::LoadArgumentsToVirtualRegs(Function &Fn) {
// [ESP] -- return address
// [ESP + 4] -- first argument (leftmost lexically)
// [ESP + 8] -- second argument, if first argument is four bytes in size
// ...
// ...
//
unsigned ArgOffset = 0; // Frame mechanisms handle retaddr slot
MachineFrameInfo *MFI = F->getFrameInfo();
@ -704,7 +704,7 @@ void X86ISel::EmitSpecialCodeForMain() {
// Switch the FPU to 64-bit precision mode for better compatibility and speed.
int CWFrameIdx = F->getFrameInfo()->CreateStackObject(2, 2);
addFrameReference(BuildMI(BB, X86::FNSTCW16m, 4), CWFrameIdx);
// Set the high part to be 64-bit precision.
addFrameReference(BuildMI(BB, X86::MOV8mi, 5),
CWFrameIdx, 1).addImm(2);
@ -756,7 +756,7 @@ void X86ISel::SelectPHINodes() {
// predecessor. Recycle it.
ValReg = EntryIt->second;
} else {
} else {
// Get the incoming value into a virtual register.
//
Value *Val = PN->getIncomingValue(i);
@ -774,11 +774,11 @@ void X86ISel::SelectPHINodes() {
// might be arbitrarily complex if it is a constant expression),
// just insert the computation at the top of the basic block.
MachineBasicBlock::iterator PI = PredMBB->begin();
// Skip over any PHI nodes though!
while (PI != PredMBB->end() && PI->getOpcode() == X86::PHI)
++PI;
ValReg = getReg(Val, PredMBB, PI);
}
@ -927,7 +927,7 @@ void X86ISel::getAddressingMode(Value *Addr, X86AddressMode &AM) {
// canFoldSetCCIntoBranchOrSelect - Return the setcc instruction if we can fold
// it into the conditional branch or select instruction which is the only user
// of the cc instruction. This is the case if the conditional branch is the
// only user of the setcc. We also don't handle long arguments below, so we
// only user of the setcc. We also don't handle long arguments below, so we
// reject them here as well.
//
static SetCondInst *canFoldSetCCIntoBranchOrSelect(Value *V) {
@ -1028,13 +1028,13 @@ unsigned X86ISel::EmitComparison(unsigned OpNum, Value *Op0, Value *Op1,
static const unsigned TESTTab[] = {
X86::TEST8ri, X86::TEST16ri, X86::TEST32ri
};
// Emit test X, i
unsigned LHS = getReg(Op0I->getOperand(0), MBB, IP);
unsigned Imm =
cast<ConstantInt>(Op0I->getOperand(1))->getRawValue();
BuildMI(*MBB, IP, TESTTab[Class], 2).addReg(LHS).addImm(Imm);
if (OpNum == 2) return 6; // Map jl -> js
if (OpNum == 3) return 7; // Map jg -> jns
return OpNum;
@ -1176,7 +1176,7 @@ unsigned X86ISel::EmitComparison(unsigned OpNum, Value *Op0, Value *Op1,
}
/// SetCC instructions - Here we just emit boilerplate code to set a byte-sized
/// register, then move it to wherever the result should be.
/// register, then move it to wherever the result should be.
///
void X86ISel::visitSetCondInst(SetCondInst &I) {
if (canFoldSetCCIntoBranchOrSelect(&I))
@ -1218,7 +1218,7 @@ void X86ISel::visitSelectInst(SelectInst &SI) {
emitSelectOperation(BB, MII, SI.getCondition(), SI.getTrueValue(),
SI.getFalseValue(), DestReg);
}
/// emitSelect - Common code shared between visitSelectInst and the constant
/// expression support.
void X86ISel::emitSelectOperation(MachineBasicBlock *MBB,
@ -1226,7 +1226,7 @@ void X86ISel::emitSelectOperation(MachineBasicBlock *MBB,
Value *Cond, Value *TrueVal, Value *FalseVal,
unsigned DestReg) {
unsigned SelectClass = getClassB(TrueVal->getType());
// We don't support 8-bit conditional moves. If we have incoming constants,
// transform them into 16-bit constants to avoid having a run-time conversion.
if (SelectClass == cByte) {
@ -1251,14 +1251,14 @@ void X86ISel::emitSelectOperation(MachineBasicBlock *MBB,
unsigned Opcode;
if (SetCondInst *SCI = canFoldSetCCIntoBranchOrSelect(Cond)) {
// We successfully folded the setcc into the select instruction.
unsigned OpNum = getSetCCNumber(SCI->getOpcode());
OpNum = EmitComparison(OpNum, SCI->getOperand(0), SCI->getOperand(1), MBB,
IP);
const Type *CompTy = SCI->getOperand(0)->getType();
bool isSigned = CompTy->isSigned() && getClassB(CompTy) != cFP;
// LLVM -> X86 signed X86 unsigned
// ----- ---------- ------------
// seteq -> cmovNE cmovNE
@ -1270,7 +1270,7 @@ void X86ISel::emitSelectOperation(MachineBasicBlock *MBB,
// ----
// cmovNS // Used by comparison with 0 optimization
// cmovS
switch (SelectClass) {
default: assert(0 && "Unknown value class!");
case cFP: {
@ -1296,7 +1296,7 @@ void X86ISel::emitSelectOperation(MachineBasicBlock *MBB,
// Long comparisons end up in the BL register.
CondReg = X86::BL;
}
BuildMI(*MBB, IP, X86::TEST8rr, 2).addReg(CondReg).addReg(CondReg);
Opcode = X86::FCMOVE;
}
@ -1511,7 +1511,7 @@ void X86ISel::visitBranchInst(BranchInst &BI) {
BuildMI(BB, X86::JNE, 1).addMBB(MBBMap[BI.getSuccessor(0)]);
} else {
BuildMI(BB, X86::JE, 1).addMBB(MBBMap[BI.getSuccessor(1)]);
if (BI.getSuccessor(0) != NextBB)
BuildMI(BB, X86::JMP, 1).addMBB(MBBMap[BI.getSuccessor(0)]);
}
@ -1524,7 +1524,7 @@ void X86ISel::visitBranchInst(BranchInst &BI) {
const Type *CompTy = SCI->getOperand(0)->getType();
bool isSigned = CompTy->isSigned() && getClassB(CompTy) != cFP;
// LLVM -> X86 signed X86 unsigned
// ----- ---------- ------------
@ -1543,7 +1543,7 @@ void X86ISel::visitBranchInst(BranchInst &BI) {
{ X86::JE, X86::JNE, X86::JL, X86::JGE, X86::JG, X86::JLE,
X86::JS, X86::JNS },
};
if (BI.getSuccessor(0) != NextBB) {
BuildMI(BB, OpcodeTab[isSigned][OpNum], 1)
.addMBB(MBBMap[BI.getSuccessor(0)]);
@ -1645,7 +1645,7 @@ void X86ISel::doCall(const ValueRecord &Ret, MachineInstr *CallMI,
}
ArgOffset += 4; // 8 byte entry, not 4.
break;
case cFP:
if (ConstantFP *CFP = dyn_cast_or_null<ConstantFP>(Args[i].Val)) {
// Store constant FP values with integer instructions to avoid having
@ -1750,7 +1750,7 @@ void X86ISel::visitCallInst(CallInst &CI) {
unsigned DestReg = CI.getType() != Type::VoidTy ? getReg(CI) : 0;
doCall(ValueRecord(DestReg, CI.getType()), TheCall, Args);
}
}
/// LowerUnknownIntrinsicFunctionCalls - This performs a prepass over the
/// function, lowering any calls to unknown intrinsic functions into the
@ -2061,7 +2061,7 @@ void X86ISel::visitIntrinsicCall(Intrinsic::ID ID, CallInst &CI) {
BuildMI(BB, Opc[Class], 0);
return;
}
default: assert(0 && "Error: unknown intrinsics should have been lowered!");
}
}
@ -2117,7 +2117,7 @@ void X86ISel::visitSimpleBinary(BinaryOperator &B, unsigned OperatorClass) {
// Special case: op Reg, load [mem]
if (isa<LoadInst>(Op0) && !isa<LoadInst>(Op1) && Class != cLong &&
Op0->hasOneUse() &&
Op0->hasOneUse() &&
isSafeToFoldLoadIntoInstruction(*cast<LoadInst>(Op0), B))
if (!B.swapOperands())
std::swap(Op0, Op1); // Make sure any loads are in the RHS.
@ -2131,7 +2131,7 @@ void X86ISel::visitSimpleBinary(BinaryOperator &B, unsigned OperatorClass) {
// Arithmetic operators
{ X86::ADD8rm, X86::ADD16rm, X86::ADD32rm }, // ADD
{ X86::SUB8rm, X86::SUB16rm, X86::SUB32rm }, // SUB
// Bitwise operators
{ X86::AND8rm, X86::AND16rm, X86::AND32rm }, // AND
{ X86:: OR8rm, X86:: OR16rm, X86:: OR32rm }, // OR
@ -2157,7 +2157,7 @@ void X86ISel::visitSimpleBinary(BinaryOperator &B, unsigned OperatorClass) {
} else {
X86AddressMode AM;
getAddressingMode(cast<LoadInst>(Op1)->getOperand(0), AM);
addFullAddress(BuildMI(BB, Opcode, 5, DestReg).addReg(Op0r), AM);
}
return;
@ -2166,7 +2166,7 @@ void X86ISel::visitSimpleBinary(BinaryOperator &B, unsigned OperatorClass) {
// If this is a floating point subtract, check to see if we can fold the first
// operand in.
if (Class == cFP && OperatorClass == 1 &&
isa<LoadInst>(Op0) &&
isa<LoadInst>(Op0) &&
isSafeToFoldLoadIntoInstruction(*cast<LoadInst>(Op0), B)) {
const Type *Ty = Op0->getType();
assert(Ty == Type::FloatTy || Ty == Type::DoubleTy && "Unknown FP type!");
@ -2180,7 +2180,7 @@ void X86ISel::visitSimpleBinary(BinaryOperator &B, unsigned OperatorClass) {
} else {
X86AddressMode AM;
getAddressingMode(cast<LoadInst>(Op0)->getOperand(0), AM);
addFullAddress(BuildMI(BB, Opcode, 5, DestReg).addReg(Op1r), AM);
}
return;
@ -2216,7 +2216,7 @@ void X86ISel::emitBinaryFPOperation(MachineBasicBlock *BB,
DestReg).addReg(Op0r), CPI);
return;
}
// Special case: R1 = op <const fp>, R2
if (ConstantFP *CFP = dyn_cast<ConstantFP>(Op0))
if (CFP->isExactlyValue(-0.0) && OperatorClass == 1) {
@ -2236,7 +2236,7 @@ void X86ISel::emitBinaryFPOperation(MachineBasicBlock *BB,
{ X86::FADD32m, X86::FSUBR32m, X86::FMUL32m, X86::FDIVR32m }, // Float
{ X86::FADD64m, X86::FSUBR64m, X86::FMUL64m, X86::FDIVR64m }, // Double
};
assert(Ty == Type::FloatTy||Ty == Type::DoubleTy && "Unknown FP type!");
unsigned Opcode = OpcodeTab[Ty != Type::FloatTy][OperatorClass];
unsigned Op1r = getReg(Op1, BB, IP);
@ -2266,7 +2266,7 @@ void X86ISel::emitBinaryFPOperation(MachineBasicBlock *BB,
void X86ISel::emitSimpleBinaryOperation(MachineBasicBlock *MBB,
MachineBasicBlock::iterator IP,
Value *Op0, Value *Op1,
unsigned OperatorClass,
unsigned OperatorClass,
unsigned DestReg) {
unsigned Class = getClassB(Op0->getType());
@ -2286,7 +2286,7 @@ void X86ISel::emitSimpleBinaryOperation(MachineBasicBlock *MBB,
if (CI->isNullValue()) {
unsigned op1Reg = getReg(Op1, MBB, IP);
BuildMI(*MBB, IP, NEGTab[Class], 1, DestReg).addReg(op1Reg);
if (Class == cLong) {
// We just emitted: Dl = neg Sl
// Now emit : T = addc Sh, 0
@ -2300,7 +2300,7 @@ void X86ISel::emitSimpleBinaryOperation(MachineBasicBlock *MBB,
// sub C, X -> tmp = neg X; DestReg = add tmp, C. This is better
// than copying C into a temporary register, because of register
// pressure (tmp and destreg can share a register.
static unsigned const ADDRITab[] = {
static unsigned const ADDRITab[] = {
X86::ADD8ri, X86::ADD16ri, X86::ADD32ri, 0, X86::ADD32ri
};
unsigned op1Reg = getReg(Op1, MBB, IP);
@ -2344,18 +2344,18 @@ void X86ISel::emitSimpleBinaryOperation(MachineBasicBlock *MBB,
BuildMI(*MBB, IP, INCTab[Class], 1, DestReg).addReg(Op0r);
return;
}
static const unsigned OpcodeTab[][5] = {
// Arithmetic operators
{ X86::ADD8ri, X86::ADD16ri, X86::ADD32ri, 0, X86::ADD32ri }, // ADD
{ X86::SUB8ri, X86::SUB16ri, X86::SUB32ri, 0, X86::SUB32ri }, // SUB
// Bitwise operators
{ X86::AND8ri, X86::AND16ri, X86::AND32ri, 0, X86::AND32ri }, // AND
{ X86:: OR8ri, X86:: OR16ri, X86:: OR32ri, 0, X86::OR32ri }, // OR
{ X86::XOR8ri, X86::XOR16ri, X86::XOR32ri, 0, X86::XOR32ri }, // XOR
};
unsigned Opcode = OpcodeTab[OperatorClass][Class];
unsigned Op1l = cast<ConstantInt>(Op1C)->getRawValue();
@ -2363,11 +2363,11 @@ void X86ISel::emitSimpleBinaryOperation(MachineBasicBlock *MBB,
BuildMI(*MBB, IP, Opcode, 2, DestReg).addReg(Op0r).addImm(Op1l);
return;
}
// If this is a long value and the high or low bits have a special
// property, emit some special cases.
unsigned Op1h = cast<ConstantInt>(Op1C)->getRawValue() >> 32LL;
// If the constant is zero in the low 32-bits, just copy the low part
// across and apply the normal 32-bit operation to the high parts. There
// will be no carry or borrow into the top.
@ -2380,7 +2380,7 @@ void X86ISel::emitSimpleBinaryOperation(MachineBasicBlock *MBB,
.addReg(Op0r+1).addImm(Op1h);
return;
}
// If this is a logical operation and the top 32-bits are zero, just
// operate on the lower 32.
if (Op1h == 0 && OperatorClass > 1) {
@ -2392,15 +2392,15 @@ void X86ISel::emitSimpleBinaryOperation(MachineBasicBlock *MBB,
BuildMI(*MBB, IP, X86::MOV32ri, 1, DestReg+1).addImm(0);
return;
}
// TODO: We could handle lots of other special cases here, such as AND'ing
// with 0xFFFFFFFF00000000 -> noop, etc.
// Otherwise, code generate the full operation with a constant.
static const unsigned TopTab[] = {
X86::ADC32ri, X86::SBB32ri, X86::AND32ri, X86::OR32ri, X86::XOR32ri
};
BuildMI(*MBB, IP, Opcode, 2, DestReg).addReg(Op0r).addImm(Op1l);
BuildMI(*MBB, IP, TopTab[OperatorClass], 2, DestReg+1)
.addReg(Op0r+1).addImm(Op1h);
@ -2412,18 +2412,18 @@ void X86ISel::emitSimpleBinaryOperation(MachineBasicBlock *MBB,
// Arithmetic operators
{ X86::ADD8rr, X86::ADD16rr, X86::ADD32rr, 0, X86::ADD32rr }, // ADD
{ X86::SUB8rr, X86::SUB16rr, X86::SUB32rr, 0, X86::SUB32rr }, // SUB
// Bitwise operators
{ X86::AND8rr, X86::AND16rr, X86::AND32rr, 0, X86::AND32rr }, // AND
{ X86:: OR8rr, X86:: OR16rr, X86:: OR32rr, 0, X86:: OR32rr }, // OR
{ X86::XOR8rr, X86::XOR16rr, X86::XOR32rr, 0, X86::XOR32rr }, // XOR
};
unsigned Opcode = OpcodeTab[OperatorClass][Class];
unsigned Op0r = getReg(Op0, MBB, IP);
unsigned Op1r = getReg(Op1, MBB, IP);
BuildMI(*MBB, IP, Opcode, 2, DestReg).addReg(Op0r).addReg(Op1r);
if (Class == cLong) { // Handle the upper 32 bits of long values...
static const unsigned TopTab[] = {
X86::ADC32rr, X86::SBB32rr, X86::AND32rr, X86::OR32rr, X86::XOR32rr
@ -2568,7 +2568,7 @@ void X86ISel::doMultiplyConst(MachineBasicBlock *MBB,
return;
}
}
if (Class == cShort) {
BuildMI(*MBB, IP, X86::IMUL16rri,2,DestReg).addReg(op0Reg).addImm(ConstRHS);
return;
@ -2580,7 +2580,7 @@ void X86ISel::doMultiplyConst(MachineBasicBlock *MBB,
// Most general case, emit a normal multiply...
TmpReg = makeAnotherReg(DestTy);
BuildMI(*MBB, IP, MOVriTab[Class], 1, TmpReg).addImm(ConstRHS);
// Emit a MUL to multiply the register holding the index by
// elementSize, putting the result in OffsetReg.
doMultiply(MBB, IP, DestReg, DestTy, op0Reg, TmpReg);
@ -2605,7 +2605,7 @@ void X86ISel::visitMul(BinaryOperator &I) {
const Type *Ty = Op0->getType();
assert(Ty == Type::FloatTy||Ty == Type::DoubleTy && "Unknown FP type!");
unsigned Opcode = Ty == Type::FloatTy ? X86::FMUL32m : X86::FMUL64m;
unsigned Op0r = getReg(Op0);
if (AllocaInst *AI = dyn_castFixedAlloca(LI->getOperand(0))) {
unsigned FI = getFixedSizedAllocaFI(AI);
@ -2613,7 +2613,7 @@ void X86ISel::visitMul(BinaryOperator &I) {
} else {
X86AddressMode AM;
getAddressingMode(LI->getOperand(0), AM);
addFullAddress(BuildMI(BB, Opcode, 5, ResultReg).addReg(Op0r), AM);
}
return;
@ -2624,7 +2624,7 @@ void X86ISel::visitMul(BinaryOperator &I) {
emitMultiply(BB, IP, Op0, Op1, ResultReg);
}
void X86ISel::emitMultiply(MachineBasicBlock *MBB,
void X86ISel::emitMultiply(MachineBasicBlock *MBB,
MachineBasicBlock::iterator IP,
Value *Op0, Value *Op1, unsigned DestReg) {
MachineBasicBlock &BB = *MBB;
@ -2655,14 +2655,14 @@ void X86ISel::emitMultiply(MachineBasicBlock *MBB,
if (ConstantInt *CI = dyn_cast<ConstantInt>(Op1)) {
unsigned CLow = CI->getRawValue();
unsigned CHi = CI->getRawValue() >> 32;
if (CLow == 0) {
// If the low part of the constant is all zeros, things are simple.
BuildMI(BB, IP, X86::MOV32ri, 1, DestReg).addImm(0);
doMultiplyConst(&BB, IP, DestReg+1, Type::UIntTy, Op0Reg, CHi);
return;
}
// Multiply the two low parts... capturing carry into EDX
unsigned OverflowReg = 0;
if (CLow == 1) {
@ -2673,15 +2673,15 @@ void X86ISel::emitMultiply(MachineBasicBlock *MBB,
BuildMI(BB, IP, X86::MOV32ri, 1, Op1RegL).addImm(CLow);
BuildMI(BB, IP, X86::MOV32rr, 1, X86::EAX).addReg(Op0Reg);
BuildMI(BB, IP, X86::MUL32r, 1).addReg(Op1RegL); // AL*BL
BuildMI(BB, IP, X86::MOV32rr, 1, DestReg).addReg(X86::EAX); // AL*BL
BuildMI(BB, IP, X86::MOV32rr, 1,
OverflowReg).addReg(X86::EDX); // AL*BL >> 32
}
unsigned AHBLReg = makeAnotherReg(Type::UIntTy); // AH*BL
doMultiplyConst(&BB, IP, AHBLReg, Type::UIntTy, Op0Reg+1, CLow);
unsigned AHBLplusOverflowReg;
if (OverflowReg) {
AHBLplusOverflowReg = makeAnotherReg(Type::UIntTy);
@ -2690,13 +2690,13 @@ void X86ISel::emitMultiply(MachineBasicBlock *MBB,
} else {
AHBLplusOverflowReg = AHBLReg;
}
if (CHi == 0) {
BuildMI(BB, IP, X86::MOV32rr, 1, DestReg+1).addReg(AHBLplusOverflowReg);
} else {
unsigned ALBHReg = makeAnotherReg(Type::UIntTy); // AL*BH
doMultiplyConst(&BB, IP, ALBHReg, Type::UIntTy, Op0Reg, CHi);
BuildMI(BB, IP, X86::ADD32rr, 2, // AL*BH + AH*BL + (AL*BL >> 32)
DestReg+1).addReg(AHBLplusOverflowReg).addReg(ALBHReg);
}
@ -2709,24 +2709,24 @@ void X86ISel::emitMultiply(MachineBasicBlock *MBB,
// Multiply the two low parts... capturing carry into EDX
BuildMI(BB, IP, X86::MOV32rr, 1, X86::EAX).addReg(Op0Reg);
BuildMI(BB, IP, X86::MUL32r, 1).addReg(Op1Reg); // AL*BL
unsigned OverflowReg = makeAnotherReg(Type::UIntTy);
BuildMI(BB, IP, X86::MOV32rr, 1, DestReg).addReg(X86::EAX); // AL*BL
BuildMI(BB, IP, X86::MOV32rr, 1,
OverflowReg).addReg(X86::EDX); // AL*BL >> 32
unsigned AHBLReg = makeAnotherReg(Type::UIntTy); // AH*BL
BuildMI(BB, IP, X86::IMUL32rr, 2,
AHBLReg).addReg(Op0Reg+1).addReg(Op1Reg);
unsigned AHBLplusOverflowReg = makeAnotherReg(Type::UIntTy);
BuildMI(BB, IP, X86::ADD32rr, 2, // AH*BL+(AL*BL >> 32)
AHBLplusOverflowReg).addReg(AHBLReg).addReg(OverflowReg);
unsigned ALBHReg = makeAnotherReg(Type::UIntTy); // AL*BH
BuildMI(BB, IP, X86::IMUL32rr, 2,
ALBHReg).addReg(Op0Reg).addReg(Op1Reg+1);
BuildMI(BB, IP, X86::ADD32rr, 2, // AL*BH + AH*BL + (AL*BL >> 32)
DestReg+1).addReg(AHBLplusOverflowReg).addReg(ALBHReg);
}
@ -2748,7 +2748,7 @@ void X86ISel::visitDivRem(BinaryOperator &I) {
const Type *Ty = Op0->getType();
assert(Ty == Type::FloatTy||Ty == Type::DoubleTy && "Unknown FP type!");
unsigned Opcode = Ty == Type::FloatTy ? X86::FDIV32m : X86::FDIV64m;
unsigned Op0r = getReg(Op0);
if (AllocaInst *AI = dyn_castFixedAlloca(LI->getOperand(0))) {
unsigned FI = getFixedSizedAllocaFI(AI);
@ -2756,7 +2756,7 @@ void X86ISel::visitDivRem(BinaryOperator &I) {
} else {
X86AddressMode AM;
getAddressingMode(LI->getOperand(0), AM);
addFullAddress(BuildMI(BB, Opcode, 5, ResultReg).addReg(Op0r), AM);
}
return;
@ -2767,7 +2767,7 @@ void X86ISel::visitDivRem(BinaryOperator &I) {
const Type *Ty = Op0->getType();
assert(Ty == Type::FloatTy||Ty == Type::DoubleTy && "Unknown FP type!");
unsigned Opcode = Ty == Type::FloatTy ? X86::FDIVR32m : X86::FDIVR64m;
unsigned Op1r = getReg(Op1);
if (AllocaInst *AI = dyn_castFixedAlloca(LI->getOperand(0))) {
unsigned FI = getFixedSizedAllocaFI(AI);
@ -2927,7 +2927,7 @@ void X86ISel::emitDivRemOperation(MachineBasicBlock *BB,
unsigned TmpReg1 = makeAnotherReg(Op0->getType());
BuildMI(*BB, IP, ANDOpcode[Class], 2, TmpReg1).addReg(Op0Reg).addImm(1);
unsigned TmpReg2 = makeAnotherReg(Op0->getType());
BuildMI(*BB, IP, XOROpcode[Class], 2,
TmpReg2).addReg(TmpReg1).addReg(TmpReg0);
@ -2971,7 +2971,7 @@ void X86ISel::emitDivRemOperation(MachineBasicBlock *BB,
// Figure out which register we want to pick the result out of...
unsigned DestReg = isDiv ? Reg : ExtReg;
// Put the result into the destination register...
BuildMI(*BB, IP, MovOpcode[Class], 1, ResultReg).addReg(DestReg);
}
@ -2991,7 +2991,7 @@ void X86ISel::visitShiftInst(ShiftInst &I) {
/// Emit code for a 'SHLD DestReg, Op0, Op1, Amt' operation, where Amt is a
/// constant.
void X86ISel::doSHLDConst(MachineBasicBlock *MBB,
void X86ISel::doSHLDConst(MachineBasicBlock *MBB,
MachineBasicBlock::iterator IP,
unsigned DestReg, unsigned Op0Reg, unsigned Op1Reg,
unsigned Amt) {
@ -3019,7 +3019,7 @@ void X86ISel::doSHLDConst(MachineBasicBlock *MBB,
// NOTE: It is always cheaper on the P4 to emit SHLD as two shifts and an OR
// than it is to emit a real SHLD.
BuildMI(*MBB, IP, X86::SHLD32rri8, 3,
BuildMI(*MBB, IP, X86::SHLD32rri8, 3,
DestReg).addReg(Op0Reg).addReg(Op1Reg).addImm(Amt);
}
}
@ -3028,8 +3028,8 @@ void X86ISel::doSHLDConst(MachineBasicBlock *MBB,
/// constant expression support.
void X86ISel::emitShiftOperation(MachineBasicBlock *MBB,
MachineBasicBlock::iterator IP,
Value *Op, Value *ShiftAmount,
bool isLeftShift, const Type *ResultTy,
Value *Op, Value *ShiftAmount,
bool isLeftShift, const Type *ResultTy,
unsigned DestReg) {
unsigned SrcReg = getReg (Op, MBB, IP);
bool isSigned = ResultTy->isSigned ();
@ -3127,7 +3127,7 @@ void X86ISel::emitShiftOperation(MachineBasicBlock *MBB,
BuildMI(*MBB, IP, X86::TEST8ri, 2).addReg(X86::CL).addImm(32);
// DestHi = (>32) ? TmpReg3 : TmpReg2;
BuildMI(*MBB, IP, X86::CMOVNE32rr, 2,
BuildMI(*MBB, IP, X86::CMOVNE32rr, 2,
DestReg+1).addReg(TmpReg2).addReg(TmpReg3);
// DestLo = (>32) ? TmpReg : TmpReg3;
BuildMI(*MBB, IP, X86::CMOVNE32rr, 2,
@ -3144,11 +3144,11 @@ void X86ISel::emitShiftOperation(MachineBasicBlock *MBB,
BuildMI(*MBB, IP, X86::TEST8ri, 2).addReg(X86::CL).addImm(32);
// DestLo = (>32) ? TmpReg3 : TmpReg2;
BuildMI(*MBB, IP, X86::CMOVNE32rr, 2,
BuildMI(*MBB, IP, X86::CMOVNE32rr, 2,
DestReg).addReg(TmpReg2).addReg(TmpReg3);
// DestHi = (>32) ? TmpReg : TmpReg3;
BuildMI(*MBB, IP, X86::CMOVNE32rr, 2,
BuildMI(*MBB, IP, X86::CMOVNE32rr, 2,
DestReg+1).addReg(TmpReg3).addReg(TmpReg);
}
}
@ -3235,7 +3235,7 @@ void X86ISel::visitLoadInst(LoadInst &I) {
bool Swapped = false;
if (!isa<LoadInst>(User->getOperand(1)))
Swapped = !cast<BinaryOperator>(User)->swapOperands();
// Okay, now that everything is set up, if this load is used by the second
// operand, and if there are no instructions that invalidate the load
// before the binary operator, eliminate the load.
@ -3253,7 +3253,7 @@ void X86ISel::visitLoadInst(LoadInst &I) {
return; // Eliminate the load!
// If we swapped the operands to the instruction, but couldn't fold the
// load anyway, swap them back. We don't want to break add X, int
// load anyway, swap them back. We don't want to break add X, int
// folding.
if (Swapped) cast<BinaryOperator>(User)->swapOperands();
}
@ -3278,7 +3278,7 @@ void X86ISel::visitLoadInst(LoadInst &I) {
} else {
X86AddressMode AM;
getAddressingMode(I.getOperand(0), AM);
if (Class == cLong) {
addFullAddress(BuildMI(BB, X86::MOV32rm, 4, DestReg), AM);
AM.Disp += 4;
@ -3339,7 +3339,7 @@ void X86ISel::visitStoreInst(StoreInst &I) {
addFullAddress(BuildMI(BB, X86::MOV32mi, 5), AM).addImm(
unsigned(V.I >> 32));
}
} else if (Class == cLong) {
unsigned ValReg = getReg(I.getOperand(0));
addFullAddress(BuildMI(BB, X86::MOV32mr, 5), AM).addReg(ValReg);
@ -3374,7 +3374,7 @@ void X86ISel::visitCastInst(CastInst &CI) {
// Noop casts are not emitted: getReg will return the source operand as the
// register to use for any uses of the noop cast.
if (DestClass == SrcClass) {
// The only detail in this plan is that casts from double -> float are
// The only detail in this plan is that casts from double -> float are
// truncating operations that we have to codegen through memory (despite
// the fact that the source/dest registers are the same class).
if (CI.getType() != Type::FloatTy || Op->getType() != Type::DoubleTy)
@ -3390,7 +3390,7 @@ void X86ISel::visitCastInst(CastInst &CI) {
if (!isa<GetElementPtrInst>(*I)) {
AllUsesAreGEPs = false;
break;
}
}
// No need to codegen this cast if all users are getelementptr instrs...
if (AllUsesAreGEPs) return;
@ -3497,7 +3497,7 @@ void X86ISel::emitCastOperation(MachineBasicBlock *BB,
{ X86::MOVSX16rr8, X86::MOVSX32rr8, X86::MOVSX32rr16, X86::MOV32rr }, // s
{ X86::MOVZX16rr8, X86::MOVZX32rr8, X86::MOVZX32rr16, X86::MOV32rr } // u
};
bool isUnsigned = SrcTy->isUnsigned() || SrcTy == Type::BoolTy;
BuildMI(*BB, IP, Opc[isUnsigned][SrcClass + DestClass - 1], 1,
DestReg).addReg(SrcReg);
@ -3516,7 +3516,7 @@ void X86ISel::emitCastOperation(MachineBasicBlock *BB,
BuildMI(*BB, IP, X86::MOV32rr, 1, DestReg).addReg(SrcReg);
return;
}
// Handle cast of LARGER int to SMALLER int using a move to EAX followed by a
// move out of AX or AL.
if ((SrcClass <= cInt || SrcClass == cLong) && DestClass <= cInt
@ -3560,7 +3560,7 @@ void X86ISel::emitCastOperation(MachineBasicBlock *BB,
default: // No promotion needed...
break;
}
if (PromoteType) {
unsigned TmpReg = makeAnotherReg(PromoteType);
BuildMI(*BB, IP, PromoteOpcode, 1, TmpReg).addReg(SrcReg);
@ -3618,11 +3618,11 @@ void X86ISel::emitCastOperation(MachineBasicBlock *BB,
MachineConstantPool *CP = F->getConstantPool();
unsigned Zero = makeAnotherReg(Type::IntTy);
Constant *Null = Constant::getNullValue(Type::UIntTy);
addConstantPoolReference(BuildMI(*BB, IP, X86::LEA32r, 5, Zero),
addConstantPoolReference(BuildMI(*BB, IP, X86::LEA32r, 5, Zero),
CP->getConstantPoolIndex(Null));
unsigned Offset = makeAnotherReg(Type::IntTy);
Constant *OffsetCst = ConstantUInt::get(Type::UIntTy, 0x5f800000);
addConstantPoolReference(BuildMI(*BB, IP, X86::LEA32r, 5, Offset),
CP->getConstantPoolIndex(OffsetCst));
unsigned Addr = makeAnotherReg(Type::IntTy);
@ -3659,7 +3659,7 @@ void X86ISel::emitCastOperation(MachineBasicBlock *BB,
// Reload the modified control word now...
addFrameReference(BuildMI(*BB, IP, X86::FLDCW16m, 4), CWFrameIdx);
// Restore the memory image of control word to original value
addFrameReference(BuildMI(*BB, IP, X86::MOV8mr, 5),
CWFrameIdx, 1).addReg(HighPartOfCW);
@ -3801,7 +3801,7 @@ void X86ISel::visitGetElementPtrInst(GetElementPtrInst &I) {
///
/// Note that there is one fewer entry in GEPTypes than there is in GEPOps.
///
void X86ISel::getGEPIndex(MachineBasicBlock *MBB,
void X86ISel::getGEPIndex(MachineBasicBlock *MBB,
MachineBasicBlock::iterator IP,
std::vector<Value*> &GEPOps,
std::vector<const Type*> &GEPTypes,
@ -3822,7 +3822,7 @@ void X86ISel::getGEPIndex(MachineBasicBlock *MBB,
// It's a struct access. CUI is the index into the structure,
// which names the field. This index must have unsigned type.
const ConstantUInt *CUI = cast<ConstantUInt>(GEPOps.back());
// Use the TargetData structure to pick out what the layout of the
// structure is in memory. Since the structure index must be constant, we
// can get its value and use it to find the right byte offset from the
@ -3849,7 +3849,7 @@ void X86ISel::getGEPIndex(MachineBasicBlock *MBB,
// If the index reg is already taken, we can't handle this index.
if (AM.IndexReg) return;
// If this is a size that we can handle, then add the index as
// If this is a size that we can handle, then add the index as
switch (TypeSize) {
case 1: case 2: case 4: case 8:
// These are all acceptable scales on X86.
@ -3906,7 +3906,7 @@ bool X86ISel::isGEPFoldable(MachineBasicBlock *MBB,
GEPOps.resize(IdxEnd-IdxBegin+1);
GEPOps[0] = Src;
std::copy(IdxBegin, IdxEnd, GEPOps.begin()+1);
std::vector<const Type*>
GEPTypes(gep_type_begin(Src->getType(), IdxBegin, IdxEnd),
gep_type_end(Src->getType(), IdxBegin, IdxEnd));
@ -3944,7 +3944,7 @@ void X86ISel::emitGEPOperation(MachineBasicBlock *MBB,
GEPOps.resize(IdxEnd-IdxBegin+1);
GEPOps[0] = Src;
std::copy(IdxBegin, IdxEnd, GEPOps.begin()+1);
std::vector<const Type*> GEPTypes;
GEPTypes.assign(gep_type_begin(Src->getType(), IdxBegin, IdxEnd),
gep_type_end(Src->getType(), IdxBegin, IdxEnd));
@ -3954,7 +3954,7 @@ void X86ISel::emitGEPOperation(MachineBasicBlock *MBB,
unsigned OldSize = GEPOps.size();
X86AddressMode AM;
getGEPIndex(MBB, IP, GEPOps, GEPTypes, AM);
if (GEPOps.size() != OldSize) {
// getGEPIndex consumed some of the input. Build an LEA instruction here.
unsigned NextTarget = 0;
@ -4061,7 +4061,7 @@ void X86ISel::visitAllocaInst(AllocaInst &I) {
// statically stack allocate the space, so we don't need to do anything here.
//
if (dyn_castFixedAlloca(&I)) return;
// Find the data size of the alloca inst's getAllocatedType.
const Type *Ty = I.getAllocatedType();
unsigned TySize = TM.getTargetData().getTypeSize(Ty);
@ -4070,7 +4070,7 @@ void X86ISel::visitAllocaInst(AllocaInst &I) {
// constant by the variable amount.
unsigned TotalSizeReg = makeAnotherReg(Type::UIntTy);
unsigned SrcReg1 = getReg(I.getArraySize());
// TotalSizeReg = mul <numelements>, <TypeSize>
MachineBasicBlock::iterator MBBI = BB->end();
doMultiplyConst(BB, MBBI, TotalSizeReg, Type::UIntTy, SrcReg1, TySize);
@ -4082,7 +4082,7 @@ void X86ISel::visitAllocaInst(AllocaInst &I) {
// AlignedSize = and <AddedSize>, ~15
unsigned AlignedSize = makeAnotherReg(Type::UIntTy);
BuildMI(BB, X86::AND32ri, 2, AlignedSize).addReg(AddedSizeReg).addImm(~15);
// Subtract size from stack pointer, thereby allocating some space.
BuildMI(BB, X86::SUB32rr, 2, X86::ESP).addReg(X86::ESP).addReg(AlignedSize);
@ -4129,7 +4129,7 @@ void X86ISel::visitFreeInst(FreeInst &I) {
1).addExternalSymbol("free", true);
doCall(ValueRecord(0, Type::VoidTy), TheCall, Args);
}
/// createX86SimpleInstructionSelector - This pass converts an LLVM function
/// into a machine code representation is a very simple peep-hole fashion. The
/// generated code sucks but the implementation is nice and simple.

10
llvm/lib/Target/X86/X86InstrBuilder.h
View File

@ -1,10 +1,10 @@
//===-- X86InstrBuilder.h - Functions to aid building x86 insts -*- C++ -*-===//
//
//
// The LLVM Compiler Infrastructure
//
// This file was developed by the LLVM research group and is distributed under
// the University of Illinois Open Source License. See LICENSE.TXT for details.
//
//
//===----------------------------------------------------------------------===//
//
// This file exposes functions that may be used with BuildMI from the
@ -37,17 +37,17 @@ struct X86AddressMode {
RegBase,
FrameIndexBase,
} BaseType;
union {
unsigned Reg;
int FrameIndex;
} Base;
unsigned Scale;
unsigned IndexReg;
unsigned Disp;
GlobalValue *GV;
X86AddressMode() : BaseType(RegBase), Scale(1), IndexReg(0), Disp(0), GV(0) {
Base.Reg = 0;
}

8
llvm/lib/Target/X86/X86InstrInfo.cpp
View File

@ -1,10 +1,10 @@
//===- X86InstrInfo.cpp - X86 Instruction Information -----------*- C++ -*-===//
//
//
// The LLVM Compiler Infrastructure
//
// This file was developed by the LLVM research group and is distributed under
// the University of Illinois Open Source License. See LICENSE.TXT for details.
//
//
//===----------------------------------------------------------------------===//
//
// This file contains the X86 implementation of the TargetInstrInfo class.
@ -55,8 +55,8 @@ MachineInstr *X86InstrInfo::convertToThreeAddress(MachineInstr *MI) const {
unsigned Dest = MI->getOperand(0).getReg();
unsigned Src = MI->getOperand(1).getReg();
// FIXME: None of these instructions are promotable to LEAs without
// additional information. In particular, LEA doesn't set the flags that
// FIXME: None of these instructions are promotable to LEAs without
// additional information. In particular, LEA doesn't set the flags that
// add and inc do. :(
return 0;

8
llvm/lib/Target/X86/X86InstrInfo.h
View File

@ -1,10 +1,10 @@
//===- X86InstrInfo.h - X86 Instruction Information ------------*- C++ -*- ===//
//
//
// The LLVM Compiler Infrastructure
//
// This file was developed by the LLVM research group and is distributed under
// the University of Illinois Open Source License. See LICENSE.TXT for details.
//
//
//===----------------------------------------------------------------------===//
//
// This file contains the X86 implementation of the TargetInstrInfo class.
@ -37,7 +37,7 @@ namespace X86II {
/// Raw - This form is for instructions that don't have any operands, so
/// they are just a fixed opcode value, like 'leave'.
RawFrm = 1,
/// AddRegFrm - This form is used for instructions like 'push r32' that have
/// their one register operand added to their opcode.
AddRegFrm = 2,
@ -61,7 +61,7 @@ namespace X86II {
/// to specify a source, which in this case is memory.
///
MRMSrcMem = 6,
/// MRM[0-7][rm] - These forms are used to represent instructions that use
/// a Mod/RM byte, and use the middle field to hold extended opcode
/// information. In the intel manual these are represented as /0, /1, ...

10
llvm/lib/Target/X86/X86JITInfo.cpp
View File

@ -1,10 +1,10 @@
//===-- X86JITInfo.cpp - Implement the JIT interfaces for the X86 target --===//
//
//
// The LLVM Compiler Infrastructure
//
// This file was developed by the LLVM research group and is distributed under
// the University of Illinois Open Source License. See LICENSE.TXT for details.
//
//
//===----------------------------------------------------------------------===//
//
// This file implements the JIT interfaces for the X86 target.
@ -54,7 +54,7 @@ static void CompilationCallback() {
// been performed. Having a variable sized alloca disables frame pointer
// elimination currently, even if it's dead. This is a gross hack.
alloca(10+(RetAddr >> 31));
#endif
assert(StackPtr[1] == RetAddr &&
"Could not find return address on the stack!");
@ -74,7 +74,7 @@ static void CompilationCallback() {
// Sanity check to make sure this really is a call instruction.
assert(((unsigned char*)(intptr_t)RetAddr)[-1] == 0xE8 &&"Not a call instr!");
unsigned NewVal = (intptr_t)JITCompilerFunction((void*)(intptr_t)RetAddr);
// Rewrite the call target... so that we don't end up here every time we
@ -110,7 +110,7 @@ void *X86JITInfo::emitFunctionStub(void *Fn, MachineCodeEmitter &MCE) {
MCE.emitWord((intptr_t)Fn-MCE.getCurrentPCValue()-4);
return MCE.finishFunctionStub(0);
}
MCE.startFunctionStub(6);
MCE.emitByte(0xE8); // Call with 32 bit pc-rel destination...

8
llvm/lib/Target/X86/X86JITInfo.h
View File

@ -1,10 +1,10 @@
//===- X86JITInfo.h - X86 implementation of the JIT interface --*- C++ -*-===//
//
//
// The LLVM Compiler Infrastructure
//
// This file was developed by the LLVM research group and is distributed under
// the University of Illinois Open Source License. See LICENSE.TXT for details.
//
//
//===----------------------------------------------------------------------===//
//
// This file contains the X86 implementation of the TargetJITInfo class.
@ -30,14 +30,14 @@ namespace llvm {
/// is not supported for this target.
///
virtual void addPassesToJITCompile(FunctionPassManager &PM);
/// replaceMachineCodeForFunction - Make it so that calling the function
/// whose machine code is at OLD turns into a call to NEW, perhaps by
/// overwriting OLD with a branch to NEW. This is used for self-modifying
/// code.
///
virtual void replaceMachineCodeForFunction(void *Old, void *New);
/// emitFunctionStub - Use the specified MachineCodeEmitter object to emit a
/// small native function that simply calls the function at the specified
/// address.

8
llvm/lib/Target/X86/X86PeepholeOpt.cpp
View File

@ -1,10 +1,10 @@
//===-- X86PeepholeOpt.cpp - X86 Peephole Optimizer -----------------------===//
//
//
// The LLVM Compiler Infrastructure
//
// This file was developed by the LLVM research group and is distributed under
// the University of Illinois Open Source License. See LICENSE.TXT for details.
//
//
//===----------------------------------------------------------------------===//
//
// This file contains a peephole optimizer for the X86.
@ -489,8 +489,8 @@ bool SSAPH::PeepholeOptimize(MachineBasicBlock &MBB,
}
}
}
// Perform instruction specific optimizations.
switch (MI->getOpcode()) {

6
llvm/lib/Target/X86/X86RegisterInfo.h
View File

@ -1,10 +1,10 @@
//===- X86RegisterInfo.h - X86 Register Information Impl --------*- C++ -*-===//
//
//
// The LLVM Compiler Infrastructure
//
// This file was developed by the LLVM research group and is distributed under
// the University of Illinois Open Source License. See LICENSE.TXT for details.
//
//
//===----------------------------------------------------------------------===//
//
// This file contains the X86 implementation of the MRegisterInfo class.
@ -34,7 +34,7 @@ struct X86RegisterInfo : public X86GenRegisterInfo {
void loadRegFromStackSlot(MachineBasicBlock &MBB,
MachineBasicBlock::iterator MI,
unsigned DestReg, int FrameIndex) const;
void copyRegToReg(MachineBasicBlock &MBB,
MachineBasicBlock::iterator MI,
unsigned DestReg, unsigned SrcReg,

4
llvm/lib/Target/X86/X86Relocations.h
View File

@ -1,10 +1,10 @@
//===- X86Relocations.h - X86 Code Relocations ------------------*- C++ -*-===//
//
//
// The LLVM Compiler Infrastructure
//
// This file was developed by the LLVM research group and is distributed under
// the University of Illinois Open Source License. See LICENSE.TXT for details.
//
//
//===----------------------------------------------------------------------===//
//
// This file defines the X86 target-specific relocation types.

6
llvm/lib/Target/X86/X86TargetMachine.cpp
View File

@ -1,12 +1,12 @@
//===-- X86TargetMachine.cpp - Define TargetMachine for the X86 -----------===//
//
//
// The LLVM Compiler Infrastructure
//
// This file was developed by the LLVM research group and is distributed under
// the University of Illinois Open Source License. See LICENSE.TXT for details.
//
//
//===----------------------------------------------------------------------===//
//
//
// This file defines the X86 specific subclass of TargetMachine.
//
//===----------------------------------------------------------------------===//

8
llvm/lib/Target/X86/X86TargetMachine.h
View File

@ -1,12 +1,12 @@
//===-- X86TargetMachine.h - Define TargetMachine for the X86 ---*- C++ -*-===//
//
//
// The LLVM Compiler Infrastructure
//
// This file was developed by the LLVM research group and is distributed under
// the University of Illinois Open Source License. See LICENSE.TXT for details.
//
//
//===----------------------------------------------------------------------===//
//
//
// This file declares the X86 specific subclass of TargetMachine.
//
//===----------------------------------------------------------------------===//
@ -45,7 +45,7 @@ public:
///
virtual bool addPassesToEmitMachineCode(FunctionPassManager &PM,
MachineCodeEmitter &MCE);
virtual bool addPassesToEmitAssembly(PassManager &PM, std::ostream &Out);
static unsigned getModuleMatchQuality(const Module &M);