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[LLDB][AArch64] Move instruction emulation to optional GetRegisterInfo 

Depends on D134539

Reviewed By: clayborg

Differential Revision: https://reviews.llvm.org/D134540
This commit is contained in:
David Spickett 2022-09-23 14:47:06 +00:00
parent ee8dd43c24
commit c87f1f5bfb
1 changed files with 54 additions and 47 deletions
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101
lldb/source/Plugins/Instruction/ARM64/EmulateInstructionARM64.cpp
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@ -663,9 +663,10 @@ bool EmulateInstructionARM64::EmulateADDSUBImm(const uint32_t opcode) {
}
Context context;
RegisterInfo reg_info_Rn;
if (GetRegisterInfo(eRegisterKindLLDB, n, reg_info_Rn))
context.SetRegisterPlusOffset(reg_info_Rn, imm);
llvm::Optional<RegisterInfo> reg_info_Rn =
GetRegisterInfo(eRegisterKindLLDB, n);
if (reg_info_Rn)
context.SetRegisterPlusOffset(*reg_info_Rn, imm);
if (n == GetFramePointerRegisterNumber() && d == gpr_sp_arm64 && !setflags) {
// 'mov sp, fp' - common epilogue instruction, CFA is now in terms of the
@ -769,24 +770,25 @@ bool EmulateInstructionARM64::EmulateLDPSTP(const uint32_t opcode) {
RegisterValue data_Rt;
RegisterValue data_Rt2;
RegisterInfo reg_info_base;
RegisterInfo reg_info_Rt;
RegisterInfo reg_info_Rt2;
if (!GetRegisterInfo(eRegisterKindLLDB, gpr_x0_arm64 + n, reg_info_base))
llvm::Optional<RegisterInfo> reg_info_base =
GetRegisterInfo(eRegisterKindLLDB, gpr_x0_arm64 + n);
if (!reg_info_base)
return false;
llvm::Optional<RegisterInfo> reg_info_Rt;
llvm::Optional<RegisterInfo> reg_info_Rt2;
if (vector) {
if (!GetRegisterInfo(eRegisterKindLLDB, fpu_d0_arm64 + t, reg_info_Rt))
return false;
if (!GetRegisterInfo(eRegisterKindLLDB, fpu_d0_arm64 + t2, reg_info_Rt2))
return false;
reg_info_Rt = GetRegisterInfo(eRegisterKindLLDB, fpu_d0_arm64 + t);
reg_info_Rt2 = GetRegisterInfo(eRegisterKindLLDB, fpu_d0_arm64 + t2);
} else {
if (!GetRegisterInfo(eRegisterKindLLDB, gpr_x0_arm64 + t, reg_info_Rt))
return false;
if (!GetRegisterInfo(eRegisterKindLLDB, gpr_x0_arm64 + t2, reg_info_Rt2))
return false;
reg_info_Rt = GetRegisterInfo(eRegisterKindLLDB, gpr_x0_arm64 + t);
reg_info_Rt2 = GetRegisterInfo(eRegisterKindLLDB, gpr_x0_arm64 + t2);
}
if (!reg_info_Rt || !reg_info_Rt2)
return false;
bool success = false;
if (n == 31) {
// CheckSPAlignment();
@ -818,29 +820,30 @@ bool EmulateInstructionARM64::EmulateLDPSTP(const uint32_t opcode) {
context_t.type = eContextRegisterStore;
context_t2.type = eContextRegisterStore;
}
context_t.SetRegisterToRegisterPlusOffset(reg_info_Rt, reg_info_base, 0);
context_t2.SetRegisterToRegisterPlusOffset(reg_info_Rt2, reg_info_base,
context_t.SetRegisterToRegisterPlusOffset(*reg_info_Rt, *reg_info_base, 0);
context_t2.SetRegisterToRegisterPlusOffset(*reg_info_Rt2, *reg_info_base,
size);
if (!ReadRegister(&reg_info_Rt, data_Rt))
if (!ReadRegister(&(*reg_info_Rt), data_Rt))
return false;
if (data_Rt.GetAsMemoryData(&reg_info_Rt, buffer, reg_info_Rt.byte_size,
if (data_Rt.GetAsMemoryData(&(*reg_info_Rt), buffer, reg_info_Rt->byte_size,
eByteOrderLittle, error) == 0)
return false;
if (!WriteMemory(context_t, address + 0, buffer, reg_info_Rt.byte_size))
if (!WriteMemory(context_t, address + 0, buffer, reg_info_Rt->byte_size))
return false;
if (!ReadRegister(&reg_info_Rt2, data_Rt2))
if (!ReadRegister(&(*reg_info_Rt2), data_Rt2))
return false;
if (data_Rt2.GetAsMemoryData(&reg_info_Rt2, buffer, reg_info_Rt2.byte_size,
eByteOrderLittle, error) == 0)
if (data_Rt2.GetAsMemoryData(&(*reg_info_Rt2), buffer,
reg_info_Rt2->byte_size, eByteOrderLittle,
error) == 0)
return false;
if (!WriteMemory(context_t2, address + size, buffer,
reg_info_Rt2.byte_size))
reg_info_Rt2->byte_size))
return false;
} break;
@ -859,37 +862,38 @@ bool EmulateInstructionARM64::EmulateLDPSTP(const uint32_t opcode) {
context_t2.SetAddress(address + size);
if (rt_unknown)
memset(buffer, 'U', reg_info_Rt.byte_size);
memset(buffer, 'U', reg_info_Rt->byte_size);
else {
if (!ReadMemory(context_t, address, buffer, reg_info_Rt.byte_size))
if (!ReadMemory(context_t, address, buffer, reg_info_Rt->byte_size))
return false;
}
if (data_Rt.SetFromMemoryData(&reg_info_Rt, buffer, reg_info_Rt.byte_size,
eByteOrderLittle, error) == 0)
if (data_Rt.SetFromMemoryData(&(*reg_info_Rt), buffer,
reg_info_Rt->byte_size, eByteOrderLittle,
error) == 0)
return false;
if (!vector && is_signed && !data_Rt.SignExtend(datasize))
return false;
if (!WriteRegister(context_t, &reg_info_Rt, data_Rt))
if (!WriteRegister(context_t, &(*reg_info_Rt), data_Rt))
return false;
if (!rt_unknown) {
if (!ReadMemory(context_t2, address + size, buffer,
reg_info_Rt2.byte_size))
reg_info_Rt2->byte_size))
return false;
}
if (data_Rt2.SetFromMemoryData(&reg_info_Rt2, buffer,
reg_info_Rt2.byte_size, eByteOrderLittle,
if (data_Rt2.SetFromMemoryData(&(*reg_info_Rt2), buffer,
reg_info_Rt2->byte_size, eByteOrderLittle,
error) == 0)
return false;
if (!vector && is_signed && !data_Rt2.SignExtend(datasize))
return false;
if (!WriteRegister(context_t2, &reg_info_Rt2, data_Rt2))
if (!WriteRegister(context_t2, &(*reg_info_Rt2), data_Rt2))
return false;
} break;
@ -906,7 +910,7 @@ bool EmulateInstructionARM64::EmulateLDPSTP(const uint32_t opcode) {
context.type = eContextAdjustStackPointer;
else
context.type = eContextAdjustBaseRegister;
WriteRegisterUnsigned(context, &reg_info_base, wb_address);
WriteRegisterUnsigned(context, &(*reg_info_base), wb_address);
}
return true;
}
@ -969,12 +973,14 @@ bool EmulateInstructionARM64::EmulateLDRSTRImm(const uint32_t opcode) {
if (!postindex)
address += offset;
RegisterInfo reg_info_base;
if (!GetRegisterInfo(eRegisterKindLLDB, gpr_x0_arm64 + n, reg_info_base))
llvm::Optional<RegisterInfo> reg_info_base =
GetRegisterInfo(eRegisterKindLLDB, gpr_x0_arm64 + n);
if (!reg_info_base)
return false;
RegisterInfo reg_info_Rt;
if (!GetRegisterInfo(eRegisterKindLLDB, gpr_x0_arm64 + t, reg_info_Rt))
llvm::Optional<RegisterInfo> reg_info_Rt =
GetRegisterInfo(eRegisterKindLLDB, gpr_x0_arm64 + t);
if (!reg_info_Rt)
return false;
Context context;
@ -986,17 +992,17 @@ bool EmulateInstructionARM64::EmulateLDRSTRImm(const uint32_t opcode) {
context.type = eContextPushRegisterOnStack;
else
context.type = eContextRegisterStore;
context.SetRegisterToRegisterPlusOffset(reg_info_Rt, reg_info_base,
context.SetRegisterToRegisterPlusOffset(*reg_info_Rt, *reg_info_base,
postindex ? 0 : offset);
if (!ReadRegister(&reg_info_Rt, data_Rt))
if (!ReadRegister(&(*reg_info_Rt), data_Rt))
return false;
if (data_Rt.GetAsMemoryData(&reg_info_Rt, buffer, reg_info_Rt.byte_size,
if (data_Rt.GetAsMemoryData(&(*reg_info_Rt), buffer, reg_info_Rt->byte_size,
eByteOrderLittle, error) == 0)
return false;
if (!WriteMemory(context, address, buffer, reg_info_Rt.byte_size))
if (!WriteMemory(context, address, buffer, reg_info_Rt->byte_size))
return false;
break;
@ -1009,14 +1015,15 @@ bool EmulateInstructionARM64::EmulateLDRSTRImm(const uint32_t opcode) {
context.type = eContextRegisterLoad;
context.SetAddress(address);
if (!ReadMemory(context, address, buffer, reg_info_Rt.byte_size))
if (!ReadMemory(context, address, buffer, reg_info_Rt->byte_size))
return false;
if (data_Rt.SetFromMemoryData(&reg_info_Rt, buffer, reg_info_Rt.byte_size,
eByteOrderLittle, error) == 0)
if (data_Rt.SetFromMemoryData(&(*reg_info_Rt), buffer,
reg_info_Rt->byte_size, eByteOrderLittle,
error) == 0)
return false;
if (!WriteRegister(context, &reg_info_Rt, data_Rt))
if (!WriteRegister(context, &(*reg_info_Rt), data_Rt))
return false;
break;
default:
@ -1033,7 +1040,7 @@ bool EmulateInstructionARM64::EmulateLDRSTRImm(const uint32_t opcode) {
context.type = eContextAdjustBaseRegister;
context.SetImmediateSigned(offset);
if (!WriteRegisterUnsigned(context, &reg_info_base, address))
if (!WriteRegisterUnsigned(context, &(*reg_info_base), address))
return false;
}
return true;