From c877d8f44c13963db39f7c2df9451c1106cdf16f Mon Sep 17 00:00:00 2001
From: Chris Lattner <sabre@nondot.org>
Date: Mon, 15 Nov 2010 04:51:55 +0000
Subject: [PATCH] add basic encoding support for immediates and registers,
 allowing us to encode all of these instructions correctly (for example):

        mflr r0                         ; encoding: [0x7c,0x08,0x02,0xa6]
        stw r0, 8(r1)                   ; encoding: [0x90,0x01,0x00,0x08]
        stwu r1, -64(r1)                ; encoding: [0x94,0x21,0xff,0xc0]

llvm-svn: 119118
---
 llvm/lib/Target/PowerPC/PPCInstrInfo.td      | 5 +----
 llvm/lib/Target/PowerPC/PPCMCCodeEmitter.cpp | 7 +++++++
 2 files changed, 8 insertions(+), 4 deletions(-)

diff --git a/llvm/lib/Target/PowerPC/PPCInstrInfo.td b/llvm/lib/Target/PowerPC/PPCInstrInfo.td
index 8d9fa471322e..05fdbeb8633c 100644
--- a/llvm/lib/Target/PowerPC/PPCInstrInfo.td
+++ b/llvm/lib/Target/PowerPC/PPCInstrInfo.td
@@ -295,9 +295,7 @@ def calltarget : Operand<iPTR> {
 def aaddr : Operand<iPTR> {
   let PrintMethod = "printAbsAddrOperand";
 }
-def piclabel: Operand<iPTR> {
-  let PrintMethod = "printPICLabel";
-}
+def piclabel: Operand<iPTR> {}
 def symbolHi: Operand<i32> {
   let PrintMethod = "printSymbolHi";
 }
@@ -321,7 +319,6 @@ def memrix : Operand<iPTR> {   // memri where the imm is shifted 2 bits.
   let MIOperandInfo = (ops i32imm:$imm, ptr_rc:$reg);
 }
 def tocentry : Operand<iPTR> {
-  let PrintMethod = "printTOCEntryLabel";
   let MIOperandInfo = (ops i32imm:$imm);
 }
 
diff --git a/llvm/lib/Target/PowerPC/PPCMCCodeEmitter.cpp b/llvm/lib/Target/PowerPC/PPCMCCodeEmitter.cpp
index 889fe0f046d3..fd98f4dfb131 100644
--- a/llvm/lib/Target/PowerPC/PPCMCCodeEmitter.cpp
+++ b/llvm/lib/Target/PowerPC/PPCMCCodeEmitter.cpp
@@ -13,6 +13,7 @@
 
 #define DEBUG_TYPE "mccodeemitter"
 #include "PPC.h"
+#include "PPCRegisterInfo.h"
 #include "llvm/MC/MCCodeEmitter.h"
 #include "llvm/MC/MCInst.h"
 #include "llvm/ADT/Statistic.h"
@@ -91,6 +92,12 @@ MCCodeEmitter *llvm::createPPCMCCodeEmitter(const Target &, TargetMachine &TM,
 unsigned PPCMCCodeEmitter::
 getMachineOpValue(const MCInst &MI, const MCOperand &MO,
                   SmallVectorImpl<MCFixup> &Fixups) const {
+  if (MO.isReg())
+    return PPCRegisterInfo::getRegisterNumbering(MO.getReg());
+  
+  if (MO.isImm())
+    return MO.getImm();
+  
   // FIXME.
   return 0;
 }