forked from OSchip/llvm-project
parent
652e0139da
commit
c84ded88ea
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@ -1358,7 +1358,7 @@ private:
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// Becoming a new entering range.
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// Becoming a new entering range.
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assert(BR[LI->reg].Dead == 0 && BR[LI->reg].Def == 0 &&
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assert(BR[LI->reg].Dead == 0 && BR[LI->reg].Def == 0 &&
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"Bundle shouldn't be re-defining reg mid-range.");
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"Bundle shouldn't be re-defining reg mid-range.");
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assert(BR[LI->reg].Use == 0 || BR[LI->reg].Use == LR &&
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assert((BR[LI->reg].Use == 0 || BR[LI->reg].Use == LR) &&
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"Bundle shouldn't have different use range for same reg.");
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"Bundle shouldn't have different use range for same reg.");
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LR->end = LastUse.getRegSlot();
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LR->end = LastUse.getRegSlot();
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BR[LI->reg].Use = LR;
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BR[LI->reg].Use = LR;
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