forked from OSchip/llvm-project
[ARM] Fix CTTZ not generating correct instructions MVE
CTTZ intrinsic should have been set to Custom, not Expand llvm-svn: 372401
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2672051495
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c84722ff27
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@ -262,7 +262,7 @@ void ARMTargetLowering::addMVEVectorTypes(bool HasMVEFP) {
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setOperationAction(ISD::MLOAD, VT, Custom);
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setOperationAction(ISD::MSTORE, VT, Legal);
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setOperationAction(ISD::CTLZ, VT, Legal);
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setOperationAction(ISD::CTTZ, VT, Expand);
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setOperationAction(ISD::CTTZ, VT, Custom);
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setOperationAction(ISD::BITREVERSE, VT, Legal);
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setOperationAction(ISD::BSWAP, VT, Legal);
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@ -44,12 +44,9 @@ entry:
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define arm_aapcs_vfpcc <4 x i32> @cttz_4i32_0_t(<4 x i32> %src){
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; CHECK-LABEL: cttz_4i32_0_t:
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; CHECK: @ %bb.0: @ %entry
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; CHECK-NEXT: vmov.i32 q1, #0x1
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; CHECK-NEXT: vsub.i32 q1, q0, q1
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; CHECK-NEXT: vbic q0, q1, q0
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; CHECK-NEXT: vmov.i32 q1, #0x20
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; CHECK-NEXT: movs r0, #32
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; CHECK-NEXT: vbrsr.32 q0, q0, r0
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; CHECK-NEXT: vclz.i32 q0, q0
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; CHECK-NEXT: vsub.i32 q0, q1, q0
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; CHECK-NEXT: bx lr
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entry:
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%0 = call <4 x i32> @llvm.cttz.v4i32(<4 x i32> %src, i1 0)
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@ -59,12 +56,9 @@ entry:
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define arm_aapcs_vfpcc <8 x i16> @cttz_8i16_0_t(<8 x i16> %src){
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; CHECK-LABEL: cttz_8i16_0_t:
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; CHECK: @ %bb.0: @ %entry
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; CHECK-NEXT: vmov.i16 q1, #0x1
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; CHECK-NEXT: vsub.i16 q1, q0, q1
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; CHECK-NEXT: vbic q0, q1, q0
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; CHECK-NEXT: vmov.i16 q1, #0x10
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; CHECK-NEXT: movs r0, #16
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; CHECK-NEXT: vbrsr.16 q0, q0, r0
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; CHECK-NEXT: vclz.i16 q0, q0
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; CHECK-NEXT: vsub.i16 q0, q1, q0
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; CHECK-NEXT: bx lr
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entry:
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%0 = call <8 x i16> @llvm.cttz.v8i16(<8 x i16> %src, i1 0)
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@ -74,12 +68,9 @@ entry:
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define arm_aapcs_vfpcc <16 x i8> @cttz_16i8_0_t(<16 x i8> %src) {
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; CHECK-LABEL: cttz_16i8_0_t:
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; CHECK: @ %bb.0: @ %entry
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; CHECK-NEXT: vmov.i8 q1, #0x1
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; CHECK-NEXT: vsub.i8 q1, q0, q1
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; CHECK-NEXT: vbic q0, q1, q0
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; CHECK-NEXT: vmov.i8 q1, #0x8
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; CHECK-NEXT: movs r0, #8
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; CHECK-NEXT: vbrsr.8 q0, q0, r0
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; CHECK-NEXT: vclz.i8 q0, q0
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; CHECK-NEXT: vsub.i8 q0, q1, q0
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; CHECK-NEXT: bx lr
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entry:
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%0 = call <16 x i8> @llvm.cttz.v16i8(<16 x i8> %src, i1 0)
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@ -129,12 +120,9 @@ entry:
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define arm_aapcs_vfpcc <4 x i32> @cttz_4i32_1_t(<4 x i32> %src){
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; CHECK-LABEL: cttz_4i32_1_t:
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; CHECK: @ %bb.0: @ %entry
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; CHECK-NEXT: vmov.i32 q1, #0x1
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; CHECK-NEXT: vsub.i32 q1, q0, q1
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; CHECK-NEXT: vbic q0, q1, q0
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; CHECK-NEXT: vmov.i32 q1, #0x20
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; CHECK-NEXT: movs r0, #32
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; CHECK-NEXT: vbrsr.32 q0, q0, r0
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; CHECK-NEXT: vclz.i32 q0, q0
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; CHECK-NEXT: vsub.i32 q0, q1, q0
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; CHECK-NEXT: bx lr
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entry:
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%0 = call <4 x i32> @llvm.cttz.v4i32(<4 x i32> %src, i1 1)
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@ -144,12 +132,9 @@ entry:
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define arm_aapcs_vfpcc <8 x i16> @cttz_8i16_1_t(<8 x i16> %src){
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; CHECK-LABEL: cttz_8i16_1_t:
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; CHECK: @ %bb.0: @ %entry
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; CHECK-NEXT: vmov.i16 q1, #0x1
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; CHECK-NEXT: vsub.i16 q1, q0, q1
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; CHECK-NEXT: vbic q0, q1, q0
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; CHECK-NEXT: vmov.i16 q1, #0x10
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; CHECK-NEXT: movs r0, #16
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; CHECK-NEXT: vbrsr.16 q0, q0, r0
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; CHECK-NEXT: vclz.i16 q0, q0
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; CHECK-NEXT: vsub.i16 q0, q1, q0
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; CHECK-NEXT: bx lr
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entry:
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%0 = call <8 x i16> @llvm.cttz.v8i16(<8 x i16> %src, i1 1)
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@ -159,12 +144,9 @@ entry:
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define arm_aapcs_vfpcc <16 x i8> @cttz_16i8_1_t(<16 x i8> %src) {
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; CHECK-LABEL: cttz_16i8_1_t:
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; CHECK: @ %bb.0: @ %entry
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; CHECK-NEXT: vmov.i8 q1, #0x1
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; CHECK-NEXT: vsub.i8 q1, q0, q1
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; CHECK-NEXT: vbic q0, q1, q0
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; CHECK-NEXT: vmov.i8 q1, #0x8
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; CHECK-NEXT: movs r0, #8
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; CHECK-NEXT: vbrsr.8 q0, q0, r0
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; CHECK-NEXT: vclz.i8 q0, q0
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; CHECK-NEXT: vsub.i8 q0, q1, q0
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; CHECK-NEXT: bx lr
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entry:
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%0 = call <16 x i8> @llvm.cttz.v16i8(<16 x i8> %src, i1 1)
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