From c83c267b84c2f9986fa67cd62e738da7d9a76137 Mon Sep 17 00:00:00 2001
From: Krzysztof Parzyszek <kparzysz@codeaurora.org>
Date: Tue, 13 Jun 2017 16:21:57 +0000
Subject: [PATCH] [Hexagon] Generate multiply-high instruction in isel

llvm-svn: 305302
---
 llvm/lib/Target/Hexagon/HexagonPatterns.td |  5 ++++
 llvm/test/CodeGen/Hexagon/mulh.ll          | 27 ++++++++++++++++++++++
 2 files changed, 32 insertions(+)
 create mode 100644 llvm/test/CodeGen/Hexagon/mulh.ll

diff --git a/llvm/lib/Target/Hexagon/HexagonPatterns.td b/llvm/lib/Target/Hexagon/HexagonPatterns.td
index f269b74fc447..a8c5658337b4 100644
--- a/llvm/lib/Target/Hexagon/HexagonPatterns.td
+++ b/llvm/lib/Target/Hexagon/HexagonPatterns.td
@@ -401,6 +401,11 @@ def Aext64: PatFrag<(ops node:$Rs), (i64 (anyext node:$Rs))>;
 def Zext64: PatFrag<(ops node:$Rs), (i64 (zext node:$Rs))>;
 def Sext64: PatLeaf<(i64 Usxtw:$Rs)>;
 
+def: Pat<(i32 (trunc (sra (mul Sext64:$Rs, Sext64:$Rt), (i32 32)))),
+         (M2_mpy_up (LoReg Sext64:$Rs), (LoReg Sext64:$Rt))>;
+def: Pat<(i32 (trunc (srl (mul Sext64:$Rs, Sext64:$Rt), (i32 32)))),
+         (M2_mpy_up (LoReg Sext64:$Rs), (LoReg Sext64:$Rt))>;
+
 def: Pat<(mul (Aext64 I32:$Rs), (Aext64 I32:$Rt)),
          (M2_dpmpyuu_s0 I32:$Rs, I32:$Rt)>;
 
diff --git a/llvm/test/CodeGen/Hexagon/mulh.ll b/llvm/test/CodeGen/Hexagon/mulh.ll
new file mode 100644
index 000000000000..0442e28d4089
--- /dev/null
+++ b/llvm/test/CodeGen/Hexagon/mulh.ll
@@ -0,0 +1,27 @@
+; RUN: llc -march=hexagon < %s | FileCheck %s
+
+target triple = "hexagon"
+
+; CHECK-LABEL: danny:
+; CHECK: r{{[0-9]+}} = mpy(r0,r1)  
+define i32 @danny(i32 %a0, i32 %a1) {
+b2:
+  %v3 = sext i32 %a0 to i64
+  %v4 = sext i32 %a1 to i64
+  %v5 = mul nsw i64 %v3, %v4
+  %v6 = ashr i64 %v5, 32
+  %v7 = trunc i64 %v6 to i32
+  ret i32 %v7
+}
+
+; CHECK-LABEL: sammy:
+; CHECK: r{{[0-9]+}} = mpy(r0,r1)
+define i32 @sammy(i32 %a0, i32 %a1) {
+b2:
+  %v3 = sext i32 %a0 to i64
+  %v4 = sext i32 %a1 to i64
+  %v5 = mul nsw i64 %v3, %v4
+  %v6 = lshr i64 %v5, 32
+  %v7 = trunc i64 %v6 to i32
+  ret i32 %v7
+}