forked from OSchip/llvm-project
[globalisel][tablegen] Tests for r319691
I forgot to 'svn add' the test files. llvm-svn: 319698
This commit is contained in:
Daniel Sanders
parent
ad142fd8d3
commit
c83977fc21
|
|
@ -0,0 +1,91 @@
|
|||
# RUN: llc -O0 -run-pass=legalizer -global-isel %s -o - | FileCheck %s
|
||||
|
||||
--- |
|
||||
target datalayout = "e-m:o-i64:64-i128:128-n32:64-S128"
|
||||
target triple = "aarch64--"
|
||||
define void @test_load(i8* %addr) {
|
||||
entry:
|
||||
ret void
|
||||
}
|
||||
define void @test_store(i8* %addr) {
|
||||
entry:
|
||||
ret void
|
||||
}
|
||||
...
|
||||
|
||||
---
|
||||
name: test_load
|
||||
registers:
|
||||
- { id: 0, class: _ }
|
||||
- { id: 1, class: _ }
|
||||
- { id: 2, class: _ }
|
||||
- { id: 3, class: _ }
|
||||
- { id: 4, class: _ }
|
||||
- { id: 5, class: _ }
|
||||
- { id: 6, class: _ }
|
||||
body: |
|
||||
bb.0.entry:
|
||||
liveins: %x0, %x1, %x2, %x3
|
||||
; CHECK-LABEL: name: test_load
|
||||
%0(p0) = COPY %x0
|
||||
|
||||
; CHECK: %1:_(s8) = G_ATOMIC_LOAD %0(p0) :: (load unordered 1 from %ir.addr)
|
||||
%1(s8) = G_ATOMIC_LOAD %0 :: (load unordered 1 from %ir.addr)
|
||||
%10:_(s32) = G_ANYEXT %1
|
||||
%w0 = COPY %10
|
||||
|
||||
; CHECK: %2:_(s16) = G_ATOMIC_LOAD %0(p0) :: (load unordered 2 from %ir.addr)
|
||||
%2(s16) = G_ATOMIC_LOAD %0 :: (load unordered 2 from %ir.addr)
|
||||
%11:_(s32) = G_ANYEXT %2
|
||||
%w0 = COPY %11
|
||||
|
||||
; CHECK: %3:_(s32) = G_ATOMIC_LOAD %0(p0) :: (load unordered 4 from %ir.addr)
|
||||
%3(s32) = G_ATOMIC_LOAD %0 :: (load unordered 4 from %ir.addr)
|
||||
%w0 = COPY %3
|
||||
|
||||
; CHECK: %4:_(s64) = G_ATOMIC_LOAD %0(p0) :: (load unordered 8 from %ir.addr)
|
||||
%4(s64) = G_ATOMIC_LOAD %0 :: (load unordered 8 from %ir.addr)
|
||||
%x0 = COPY %4
|
||||
|
||||
%5(p0) = G_ATOMIC_LOAD %0(p0) :: (load unordered 8 from %ir.addr)
|
||||
%12:_(s64) = G_PTRTOINT %5
|
||||
%x0 = COPY %12
|
||||
...
|
||||
|
||||
---
|
||||
name: test_store
|
||||
registers:
|
||||
- { id: 0, class: _ }
|
||||
- { id: 1, class: _ }
|
||||
- { id: 2, class: _ }
|
||||
- { id: 3, class: _ }
|
||||
- { id: 4, class: _ }
|
||||
- { id: 5, class: _ }
|
||||
- { id: 6, class: _ }
|
||||
- { id: 7, class: _ }
|
||||
body: |
|
||||
bb.0.entry:
|
||||
liveins: %x0, %x1, %x2, %x3
|
||||
; CHECK-LABEL: name: test_store
|
||||
|
||||
%0(p0) = COPY %x0
|
||||
%1(s32) = COPY %w1
|
||||
|
||||
; CHECK: G_ATOMIC_STORE %2(s8), %0(p0) :: (store unordered 1 into %ir.addr)
|
||||
%2(s8) = G_TRUNC %1
|
||||
G_ATOMIC_STORE %2, %0 :: (store unordered 1 into %ir.addr)
|
||||
|
||||
; CHECK: G_ATOMIC_STORE %3(s16), %0(p0) :: (store unordered 2 into %ir.addr)
|
||||
%3(s16) = G_TRUNC %1
|
||||
G_ATOMIC_STORE %3, %0 :: (store unordered 2 into %ir.addr)
|
||||
|
||||
; CHECK: G_ATOMIC_STORE %1(s32), %0(p0) :: (store unordered 4 into %ir.addr)
|
||||
G_ATOMIC_STORE %1, %0 :: (store unordered 4 into %ir.addr)
|
||||
|
||||
; CHECK: G_ATOMIC_STORE %4(s64), %0(p0) :: (store unordered 8 into %ir.addr)
|
||||
%4(s64) = G_PTRTOINT %0(p0)
|
||||
G_ATOMIC_STORE %4, %0 :: (store unordered 8 into %ir.addr)
|
||||
|
||||
; CHECK: G_ATOMIC_STORE %0(p0), %0(p0) :: (store unordered 8 into %ir.addr)
|
||||
G_ATOMIC_STORE %0(p0), %0(p0) :: (store unordered 8 into %ir.addr)
|
||||
...
|
||||
|
|
@ -0,0 +1,431 @@
|
|||
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
|
||||
# RUN: llc -mtriple=aarch64-- -run-pass=instruction-select -verify-machineinstrs -global-isel %s -o - | FileCheck %s
|
||||
|
||||
--- |
|
||||
target datalayout = "e-m:o-i64:64-i128:128-n32:64-S128"
|
||||
|
||||
define void @load_s8_gpr_unordered(i64* %addr) { ret void }
|
||||
define void @load_s8_gpr_monotonic(i64* %addr) { ret void }
|
||||
define void @load_s8_gpr_acquire(i64* %addr) { ret void }
|
||||
define void @load_s8_gpr_release(i64* %addr) { ret void }
|
||||
define void @load_s8_gpr_acq_rel(i64* %addr) { ret void }
|
||||
define void @load_s8_gpr_seq_cst(i64* %addr) { ret void }
|
||||
|
||||
define void @load_s32_gpr_unordered(i64* %addr) { ret void }
|
||||
define void @load_s32_gpr_monotonic(i64* %addr) { ret void }
|
||||
define void @load_s32_gpr_acquire(i64* %addr) { ret void }
|
||||
define void @load_s32_gpr_release(i64* %addr) { ret void }
|
||||
define void @load_s32_gpr_acq_rel(i64* %addr) { ret void }
|
||||
define void @load_s32_gpr_seq_cst(i64* %addr) { ret void }
|
||||
|
||||
define void @load_s64_gpr_unordered(i64* %addr) { ret void }
|
||||
define void @load_s64_gpr_monotonic(i64* %addr) { ret void }
|
||||
define void @load_s64_gpr_acquire(i64* %addr) { ret void }
|
||||
define void @load_s64_gpr_release(i64* %addr) { ret void }
|
||||
define void @load_s64_gpr_acq_rel(i64* %addr) { ret void }
|
||||
define void @load_s64_gpr_seq_cst(i64* %addr) { ret void }
|
||||
...
|
||||
|
||||
---
|
||||
name: load_s8_gpr_unordered
|
||||
legalized: true
|
||||
regBankSelected: true
|
||||
|
||||
registers:
|
||||
- { id: 0, class: gpr }
|
||||
- { id: 1, class: gpr }
|
||||
|
||||
body: |
|
||||
bb.0:
|
||||
liveins: %x0
|
||||
|
||||
; CHECK-LABEL: name: load_s8_gpr_unordered
|
||||
; CHECK: [[COPY:%[0-9]+]]:gpr64sp = COPY %x0
|
||||
; CHECK: [[T0:%[0-9]+]]:gpr32 = LDRBBui [[COPY]], 0 :: (load release 4 from %ir.addr)
|
||||
; CHECK: %x0 = COPY [[T0]]
|
||||
%0(p0) = COPY %x0
|
||||
%1(s8) = G_ATOMIC_LOAD %0 :: (load release 4 from %ir.addr)
|
||||
%2:gpr(s32) = G_ANYEXT %1
|
||||
%x0 = COPY %2(s32)
|
||||
...
|
||||
|
||||
---
|
||||
name: load_s8_gpr_monotonic
|
||||
legalized: true
|
||||
regBankSelected: true
|
||||
|
||||
registers:
|
||||
- { id: 0, class: gpr }
|
||||
- { id: 1, class: gpr }
|
||||
|
||||
body: |
|
||||
bb.0:
|
||||
liveins: %x0
|
||||
|
||||
; CHECK-LABEL: name: load_s8_gpr_monotonic
|
||||
; CHECK: [[COPY:%[0-9]+]]:gpr64sp = COPY %x0
|
||||
; CHECK: [[T0:%[0-9]+]]:gpr32 = LDRBBui [[COPY]], 0 :: (load release 4 from %ir.addr)
|
||||
; CHECK: %x0 = COPY [[T0]]
|
||||
%0(p0) = COPY %x0
|
||||
%1(s8) = G_ATOMIC_LOAD %0 :: (load release 4 from %ir.addr)
|
||||
%2:gpr(s32) = G_ANYEXT %1
|
||||
%x0 = COPY %2(s32)
|
||||
...
|
||||
|
||||
---
|
||||
name: load_s8_gpr_acquire
|
||||
legalized: true
|
||||
regBankSelected: true
|
||||
|
||||
registers:
|
||||
- { id: 0, class: gpr }
|
||||
- { id: 1, class: gpr }
|
||||
|
||||
body: |
|
||||
bb.0:
|
||||
liveins: %x0
|
||||
|
||||
; CHECK-LABEL: name: load_s8_gpr_acquire
|
||||
; CHECK: [[COPY:%[0-9]+]]:gpr64sp = COPY %x0
|
||||
; CHECK: [[T0:%[0-9]+]]:gpr32 = LDARB [[COPY]] :: (load acquire 1 from %ir.addr)
|
||||
; CHECK: %x0 = COPY [[T0]]
|
||||
%0(p0) = COPY %x0
|
||||
%1(s8) = G_ATOMIC_LOAD %0 :: (load acquire 1 from %ir.addr)
|
||||
%2:gpr(s32) = G_ANYEXT %1
|
||||
%x0 = COPY %2(s32)
|
||||
...
|
||||
|
||||
---
|
||||
name: load_s8_gpr_release
|
||||
legalized: true
|
||||
regBankSelected: true
|
||||
|
||||
registers:
|
||||
- { id: 0, class: gpr }
|
||||
- { id: 1, class: gpr }
|
||||
|
||||
body: |
|
||||
bb.0:
|
||||
liveins: %x0
|
||||
|
||||
; CHECK-LABEL: name: load_s8_gpr_release
|
||||
; CHECK: [[COPY:%[0-9]+]]:gpr64sp = COPY %x0
|
||||
; CHECK: [[T0:%[0-9]+]]:gpr32 = LDRBBui [[COPY]], 0 :: (load release 1 from %ir.addr)
|
||||
; CHECK: %x0 = COPY [[T0]]
|
||||
%0(p0) = COPY %x0
|
||||
%1(s8) = G_ATOMIC_LOAD %0 :: (load release 1 from %ir.addr)
|
||||
%2:gpr(s32) = G_ANYEXT %1
|
||||
%x0 = COPY %2(s32)
|
||||
...
|
||||
|
||||
---
|
||||
name: load_s8_gpr_acq_rel
|
||||
legalized: true
|
||||
regBankSelected: true
|
||||
|
||||
registers:
|
||||
- { id: 0, class: gpr }
|
||||
- { id: 1, class: gpr }
|
||||
|
||||
body: |
|
||||
bb.0:
|
||||
liveins: %x0
|
||||
|
||||
; CHECK-LABEL: name: load_s8_gpr_acq_rel
|
||||
; CHECK: [[COPY:%[0-9]+]]:gpr64sp = COPY %x0
|
||||
; CHECK: [[T0:%[0-9]+]]:gpr32 = LDARB [[COPY]] :: (load acq_rel 1 from %ir.addr)
|
||||
; CHECK: %x0 = COPY [[T0]]
|
||||
%0(p0) = COPY %x0
|
||||
%1(s8) = G_ATOMIC_LOAD %0 :: (load acq_rel 1 from %ir.addr)
|
||||
%2:gpr(s32) = G_ANYEXT %1
|
||||
%x0 = COPY %2(s32)
|
||||
...
|
||||
|
||||
---
|
||||
name: load_s8_gpr_seq_cst
|
||||
legalized: true
|
||||
regBankSelected: true
|
||||
|
||||
registers:
|
||||
- { id: 0, class: gpr }
|
||||
- { id: 1, class: gpr }
|
||||
|
||||
body: |
|
||||
bb.0:
|
||||
liveins: %x0
|
||||
|
||||
; CHECK-LABEL: name: load_s8_gpr_seq_cst
|
||||
; CHECK: [[COPY:%[0-9]+]]:gpr64sp = COPY %x0
|
||||
; CHECK: [[T0:%[0-9]+]]:gpr32 = LDARB [[COPY]] :: (load seq_cst 1 from %ir.addr)
|
||||
; CHECK: %x0 = COPY [[T0]]
|
||||
%0(p0) = COPY %x0
|
||||
%1(s8) = G_ATOMIC_LOAD %0 :: (load seq_cst 1 from %ir.addr)
|
||||
%2:gpr(s32) = G_ANYEXT %1
|
||||
%x0 = COPY %2(s32)
|
||||
...
|
||||
|
||||
---
|
||||
name: load_s32_gpr_unordered
|
||||
legalized: true
|
||||
regBankSelected: true
|
||||
|
||||
registers:
|
||||
- { id: 0, class: gpr }
|
||||
- { id: 1, class: gpr }
|
||||
|
||||
body: |
|
||||
bb.0:
|
||||
liveins: %x0
|
||||
|
||||
; CHECK-LABEL: name: load_s32_gpr_unordered
|
||||
; CHECK: [[COPY:%[0-9]+]]:gpr64sp = COPY %x0
|
||||
; CHECK: [[T0:%[0-9]+]]:gpr32 = LDRWui [[COPY]], 0 :: (load release 4 from %ir.addr)
|
||||
; CHECK: %x0 = COPY [[T0]]
|
||||
%0(p0) = COPY %x0
|
||||
%1(s32) = G_ATOMIC_LOAD %0 :: (load release 4 from %ir.addr)
|
||||
%x0 = COPY %1(s32)
|
||||
...
|
||||
|
||||
---
|
||||
name: load_s32_gpr_monotonic
|
||||
legalized: true
|
||||
regBankSelected: true
|
||||
|
||||
registers:
|
||||
- { id: 0, class: gpr }
|
||||
- { id: 1, class: gpr }
|
||||
|
||||
body: |
|
||||
bb.0:
|
||||
liveins: %x0
|
||||
|
||||
; CHECK-LABEL: name: load_s32_gpr_monotonic
|
||||
; CHECK: [[COPY:%[0-9]+]]:gpr64sp = COPY %x0
|
||||
; CHECK: [[T0:%[0-9]+]]:gpr32 = LDRWui [[COPY]], 0 :: (load release 4 from %ir.addr)
|
||||
; CHECK: %x0 = COPY [[T0]]
|
||||
%0(p0) = COPY %x0
|
||||
%1(s32) = G_ATOMIC_LOAD %0 :: (load release 4 from %ir.addr)
|
||||
%x0 = COPY %1(s32)
|
||||
...
|
||||
|
||||
---
|
||||
name: load_s32_gpr_acquire
|
||||
legalized: true
|
||||
regBankSelected: true
|
||||
|
||||
registers:
|
||||
- { id: 0, class: gpr }
|
||||
- { id: 1, class: gpr }
|
||||
|
||||
body: |
|
||||
bb.0:
|
||||
liveins: %x0
|
||||
|
||||
; CHECK-LABEL: name: load_s32_gpr_acquire
|
||||
; CHECK: [[COPY:%[0-9]+]]:gpr64sp = COPY %x0
|
||||
; CHECK: [[T0:%[0-9]+]]:gpr32 = LDARW [[COPY]] :: (load acquire 4 from %ir.addr)
|
||||
; CHECK: %x0 = COPY [[T0]]
|
||||
%0(p0) = COPY %x0
|
||||
%1(s32) = G_ATOMIC_LOAD %0 :: (load acquire 4 from %ir.addr)
|
||||
%x0 = COPY %1(s32)
|
||||
...
|
||||
|
||||
---
|
||||
name: load_s32_gpr_release
|
||||
legalized: true
|
||||
regBankSelected: true
|
||||
|
||||
registers:
|
||||
- { id: 0, class: gpr }
|
||||
- { id: 1, class: gpr }
|
||||
|
||||
body: |
|
||||
bb.0:
|
||||
liveins: %x0
|
||||
|
||||
; CHECK-LABEL: name: load_s32_gpr_release
|
||||
; CHECK: [[COPY:%[0-9]+]]:gpr64sp = COPY %x0
|
||||
; CHECK: [[T0:%[0-9]+]]:gpr32 = LDRWui [[COPY]], 0 :: (load release 4 from %ir.addr)
|
||||
; CHECK: %x0 = COPY [[T0]]
|
||||
%0(p0) = COPY %x0
|
||||
%1(s32) = G_ATOMIC_LOAD %0 :: (load release 4 from %ir.addr)
|
||||
%x0 = COPY %1(s32)
|
||||
...
|
||||
|
||||
---
|
||||
name: load_s32_gpr_acq_rel
|
||||
legalized: true
|
||||
regBankSelected: true
|
||||
|
||||
registers:
|
||||
- { id: 0, class: gpr }
|
||||
- { id: 1, class: gpr }
|
||||
|
||||
body: |
|
||||
bb.0:
|
||||
liveins: %x0
|
||||
|
||||
; CHECK-LABEL: name: load_s32_gpr_acq_rel
|
||||
; CHECK: [[COPY:%[0-9]+]]:gpr64sp = COPY %x0
|
||||
; CHECK: [[T0:%[0-9]+]]:gpr32 = LDARW [[COPY]] :: (load acq_rel 4 from %ir.addr)
|
||||
; CHECK: %x0 = COPY [[T0]]
|
||||
%0(p0) = COPY %x0
|
||||
%1(s32) = G_ATOMIC_LOAD %0 :: (load acq_rel 4 from %ir.addr)
|
||||
%x0 = COPY %1(s32)
|
||||
...
|
||||
|
||||
---
|
||||
name: load_s32_gpr_seq_cst
|
||||
legalized: true
|
||||
regBankSelected: true
|
||||
|
||||
registers:
|
||||
- { id: 0, class: gpr }
|
||||
- { id: 1, class: gpr }
|
||||
|
||||
body: |
|
||||
bb.0:
|
||||
liveins: %x0
|
||||
|
||||
; CHECK-LABEL: name: load_s32_gpr_seq_cst
|
||||
; CHECK: [[COPY:%[0-9]+]]:gpr64sp = COPY %x0
|
||||
; CHECK: [[T0:%[0-9]+]]:gpr32 = LDARW [[COPY]] :: (load seq_cst 4 from %ir.addr)
|
||||
; CHECK: %x0 = COPY [[T0]]
|
||||
%0(p0) = COPY %x0
|
||||
%1(s32) = G_ATOMIC_LOAD %0 :: (load seq_cst 4 from %ir.addr)
|
||||
%x0 = COPY %1(s32)
|
||||
...
|
||||
|
||||
|
||||
---
|
||||
name: load_s64_gpr_unordered
|
||||
legalized: true
|
||||
regBankSelected: true
|
||||
|
||||
registers:
|
||||
- { id: 0, class: gpr }
|
||||
- { id: 1, class: gpr }
|
||||
|
||||
body: |
|
||||
bb.0:
|
||||
liveins: %x0
|
||||
|
||||
; CHECK-LABEL: name: load_s64_gpr_unordered
|
||||
; CHECK: [[COPY:%[0-9]+]]:gpr64sp = COPY %x0
|
||||
; CHECK: [[LDRXui:%[0-9]+]]:gpr64 = LDRXui [[COPY]], 0 :: (load release 8 from %ir.addr)
|
||||
; CHECK: %x0 = COPY [[LDRXui]]
|
||||
%0(p0) = COPY %x0
|
||||
%1(s64) = G_ATOMIC_LOAD %0 :: (load release 8 from %ir.addr)
|
||||
%x0 = COPY %1(s64)
|
||||
...
|
||||
|
||||
---
|
||||
name: load_s64_gpr_monotonic
|
||||
legalized: true
|
||||
regBankSelected: true
|
||||
|
||||
registers:
|
||||
- { id: 0, class: gpr }
|
||||
- { id: 1, class: gpr }
|
||||
|
||||
body: |
|
||||
bb.0:
|
||||
liveins: %x0
|
||||
|
||||
; CHECK-LABEL: name: load_s64_gpr_monotonic
|
||||
; CHECK: [[COPY:%[0-9]+]]:gpr64sp = COPY %x0
|
||||
; CHECK: [[LDRXui:%[0-9]+]]:gpr64 = LDRXui [[COPY]], 0 :: (load release 8 from %ir.addr)
|
||||
; CHECK: %x0 = COPY [[LDRXui]]
|
||||
%0(p0) = COPY %x0
|
||||
%1(s64) = G_ATOMIC_LOAD %0 :: (load release 8 from %ir.addr)
|
||||
%x0 = COPY %1(s64)
|
||||
...
|
||||
|
||||
---
|
||||
name: load_s64_gpr_acquire
|
||||
legalized: true
|
||||
regBankSelected: true
|
||||
|
||||
registers:
|
||||
- { id: 0, class: gpr }
|
||||
- { id: 1, class: gpr }
|
||||
|
||||
body: |
|
||||
bb.0:
|
||||
liveins: %x0
|
||||
|
||||
; CHECK-LABEL: name: load_s64_gpr_acquire
|
||||
; CHECK: [[COPY:%[0-9]+]]:gpr64sp = COPY %x0
|
||||
; CHECK: [[LDRXui:%[0-9]+]]:gpr64 = LDARX [[COPY]] :: (load acquire 8 from %ir.addr)
|
||||
; CHECK: %x0 = COPY [[LDRXui]]
|
||||
%0(p0) = COPY %x0
|
||||
%1(s64) = G_ATOMIC_LOAD %0 :: (load acquire 8 from %ir.addr)
|
||||
%x0 = COPY %1(s64)
|
||||
...
|
||||
|
||||
---
|
||||
name: load_s64_gpr_release
|
||||
legalized: true
|
||||
regBankSelected: true
|
||||
|
||||
registers:
|
||||
- { id: 0, class: gpr }
|
||||
- { id: 1, class: gpr }
|
||||
|
||||
body: |
|
||||
bb.0:
|
||||
liveins: %x0
|
||||
|
||||
; CHECK-LABEL: name: load_s64_gpr_release
|
||||
; CHECK: [[COPY:%[0-9]+]]:gpr64sp = COPY %x0
|
||||
; CHECK: [[LDRXui:%[0-9]+]]:gpr64 = LDRXui [[COPY]], 0 :: (load release 8 from %ir.addr)
|
||||
; CHECK: %x0 = COPY [[LDRXui]]
|
||||
%0(p0) = COPY %x0
|
||||
%1(s64) = G_ATOMIC_LOAD %0 :: (load release 8 from %ir.addr)
|
||||
%x0 = COPY %1(s64)
|
||||
...
|
||||
|
||||
---
|
||||
name: load_s64_gpr_acq_rel
|
||||
legalized: true
|
||||
regBankSelected: true
|
||||
|
||||
registers:
|
||||
- { id: 0, class: gpr }
|
||||
- { id: 1, class: gpr }
|
||||
|
||||
body: |
|
||||
bb.0:
|
||||
liveins: %x0
|
||||
|
||||
; CHECK-LABEL: name: load_s64_gpr_acq_rel
|
||||
; CHECK: [[COPY:%[0-9]+]]:gpr64sp = COPY %x0
|
||||
; CHECK: [[LDRXui:%[0-9]+]]:gpr64 = LDARX [[COPY]] :: (load acq_rel 8 from %ir.addr)
|
||||
; CHECK: %x0 = COPY [[LDRXui]]
|
||||
%0(p0) = COPY %x0
|
||||
%1(s64) = G_ATOMIC_LOAD %0 :: (load acq_rel 8 from %ir.addr)
|
||||
%x0 = COPY %1(s64)
|
||||
...
|
||||
|
||||
---
|
||||
name: load_s64_gpr_seq_cst
|
||||
legalized: true
|
||||
regBankSelected: true
|
||||
|
||||
registers:
|
||||
- { id: 0, class: gpr }
|
||||
- { id: 1, class: gpr }
|
||||
|
||||
body: |
|
||||
bb.0:
|
||||
liveins: %x0
|
||||
|
||||
; CHECK-LABEL: name: load_s64_gpr_seq_cst
|
||||
; CHECK: [[COPY:%[0-9]+]]:gpr64sp = COPY %x0
|
||||
; CHECK: [[LDRXui:%[0-9]+]]:gpr64 = LDARX [[COPY]] :: (load seq_cst 8 from %ir.addr)
|
||||
; CHECK: %x0 = COPY [[LDRXui]]
|
||||
%0(p0) = COPY %x0
|
||||
%1(s64) = G_ATOMIC_LOAD %0 :: (load seq_cst 8 from %ir.addr)
|
||||
%x0 = COPY %1(s64)
|
||||
...
|
||||
|
||||
Loading…
Reference in New Issue