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Don't use register classes larger than TLI->getRegClassFor(VT). 

In Thumb mode we cannot handle GPR virtual registers, even though some
instructions can. When isel is lowering a CopyFromReg, it should limit
itself to subclasses of getRegClassFor(VT).

<rdar://problem/9624323>

llvm-svn: 133210
This commit is contained in:
Jakob Stoklund Olesen 2011-06-16 22:50:38 +00:00
parent d9bc6c3f59
commit c826df9506
2 changed files with 31 additions and 2 deletions
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9
llvm/lib/CodeGen/SelectionDAG/InstrEmitter.cpp
View File

@ -76,6 +76,12 @@ EmitCopyFromReg(SDNode *Node, unsigned ResNo, bool IsClone, bool IsCloned,
// the CopyToReg'd destination register instead of creating a new vreg.
bool MatchReg = true;
const TargetRegisterClass *UseRC = NULL;
EVT VT = Node->getValueType(ResNo);
// Stick to the preferred register classes for legal types.
if (TLI->isTypeLegal(VT))
UseRC = TLI->getRegClassFor(VT);
if (!IsClone && !IsCloned)
for (SDNode::use_iterator UI = Node->use_begin(), E = Node->use_end();
UI != E; ++UI) {
@ -121,10 +127,9 @@ EmitCopyFromReg(SDNode *Node, unsigned ResNo, bool IsClone, bool IsCloned,
break;
}
EVT VT = Node->getValueType(ResNo);
const TargetRegisterClass *SrcRC = 0, *DstRC = 0;
SrcRC = TRI->getMinimalPhysRegClass(SrcReg, VT);
// Figure out the register class to create for the destreg.
if (VRBase) {
DstRC = MRI->getRegClass(VRBase);

24
llvm/test/CodeGen/Thumb/2011-06-16-NoGPRs.ll Normal file
View File

@ -0,0 +1,24 @@
; RUN: llc < %s
;
; This test would crash because isel creates a GPR register for the return
; value from f1. The register is only used by tBLXr_r9 which accepts a full GPR
; register, but we cannot have live GPRs in thumb mode because we don't know how
; to spill them.
;
; <rdar://problem/9624323>
target datalayout = "e-p:32:32:32-i1:8:32-i8:8:32-i16:16:32-i32:32:32-i64:32:32-f32:32:32-f64:32:32-v64:32:64-v128:32:128-a0:0:32-n32"
target triple = "thumbv6-apple-darwin10"
%0 = type opaque
declare i8* (i8*, i8*, ...)* @f1(i8*, i8*) optsize
declare i8* @f2(i8*, i8*, ...)
define internal void @f(i8* %self, i8* %_cmd, %0* %inObjects, %0* %inIndexes) optsize ssp {
entry:
%call14 = tail call i8* (i8*, i8*, ...)* (i8*, i8*)* @f1(i8* undef, i8* %_cmd) optsize
%0 = bitcast i8* (i8*, i8*, ...)* %call14 to void (i8*, i8*, %0*, %0*)*
tail call void %0(i8* %self, i8* %_cmd, %0* %inObjects, %0* %inIndexes) optsize
tail call void bitcast (i8* (i8*, i8*, ...)* @f2 to void (i8*, i8*, i32, %0*, %0*)*)(i8* %self, i8* undef, i32 2, %0* %inIndexes, %0* undef) optsize
ret void
}