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[AArch64][GlobalISel] Lower G_SHUFFLE_VECTOR with 1 elt src and 1 elt mask. 

Again, it's weird that these are allowed. Since lowering support was added in
r368709 we started crashing on compiling the neon intrinsics test in the test
suite. This fixes the lowering to fold the 1 elt src/mask case into copies.

llvm-svn: 369135
This commit is contained in:
Amara Emerson 2019-08-16 18:06:53 +00:00
parent 8ff1b7de4d
commit c809230a69
2 changed files with 43 additions and 1 deletions
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18
llvm/lib/CodeGen/GlobalISel/LegalizerHelper.cpp
View File

@ -3823,7 +3823,6 @@ LegalizerHelper::lowerShuffleVector(MachineInstr &MI) {
Register Src1Reg = MI.getOperand(2).getReg();
LLT Src0Ty = MRI.getType(Src0Reg);
LLT DstTy = MRI.getType(DstReg);
LLT EltTy = DstTy.getElementType();
LLT IdxTy = LLT::scalar(32);
const Constant *ShufMask = MI.getOperand(3).getShuffleMask();
@ -3831,8 +3830,25 @@ LegalizerHelper::lowerShuffleVector(MachineInstr &MI) {
SmallVector<int, 32> Mask;
ShuffleVectorInst::getShuffleMask(ShufMask, Mask);
if (DstTy.isScalar()) {
if (Src0Ty.isVector())
return UnableToLegalize;
// This is just a SELECT.
assert(Mask.size() == 1 && "Expected a single mask element");
Register Val;
if (Mask[0] < 0 || Mask[0] > 1)
Val = MIRBuilder.buildUndef(DstTy).getReg(0);
else
Val = Mask[0] == 0 ? Src0Reg : Src1Reg;
MIRBuilder.buildCopy(DstReg, Val);
MI.eraseFromParent();
return Legalized;
}
Register Undef;
SmallVector<Register, 32> BuildVec;
LLT EltTy = DstTy.getElementType();
for (int Idx : Mask) {
if (Idx < 0) {

26
llvm/test/CodeGen/AArch64/GlobalISel/legalize-shuffle-vector.mir
View File

@ -44,3 +44,29 @@ body: |
RET_ReallyLR implicit $q0
...
---
name: shuffle_1elt_mask
alignment: 2
tracksRegLiveness: true
body: |
bb.1:
liveins: $d0, $d1
; CHECK-LABEL: name: shuffle_1elt_mask
; CHECK: liveins: $d0, $d1
; CHECK: [[COPY:%[0-9]+]]:_(s64) = COPY $d0
; CHECK: [[COPY1:%[0-9]+]]:_(s64) = COPY $d1
; CHECK: [[COPY2:%[0-9]+]]:_(s64) = COPY [[COPY]](s64)
; CHECK: [[COPY3:%[0-9]+]]:_(s64) = COPY [[COPY1]](s64)
; CHECK: $d0 = COPY [[COPY2]](s64)
; CHECK: $d1 = COPY [[COPY3]](s64)
; CHECK: RET_ReallyLR implicit $d0, implicit $d1
%0:_(s64) = COPY $d0
%1:_(s64) = COPY $d1
%3:_(s64) = G_SHUFFLE_VECTOR %0:_(s64), %1:_, shufflemask(0)
%4:_(s64) = G_SHUFFLE_VECTOR %0:_(s64), %1:_, shufflemask(1)
$d0 = COPY %3(s64)
$d1 = COPY %4(s64)
RET_ReallyLR implicit $d0, implicit $d1
...