forked from OSchip/llvm-project
[AMDGPU][MC][NFC] Split large asm tests into smaller chunks
The following large tests have been split into smaller parts by instruction formats:
gfx7_asm_all.s
gfx8_asm_all.s
gfx9_asm_all.s
gfx10_asm_all.s
This change results in noticeable lit testing speedup.
For example, on a debug Windows build, split asm tests are run 3.5 times faster.
This commit is contained in:
Dmitry Preobrazhensky
parent
38bfa25387
commit
c7ff2c0da1
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// RUN: llvm-mc -arch=amdgcn -mcpu=gfx1010 -mattr=+wavefrontsize32,-wavefrontsize64 -show-encoding %s | FileCheck --check-prefixes=GFX10,W32 %s
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// RUN: llvm-mc -arch=amdgcn -mcpu=gfx1010 -mattr=-wavefrontsize32,+wavefrontsize64 -show-encoding %s | FileCheck --check-prefixes=GFX10,W64 %s
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//===----------------------------------------------------------------------===//
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// ENC_FLAT.
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//===----------------------------------------------------------------------===//
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flat_load_ubyte v5, v[1:2]
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// GFX10: encoding: [0x00,0x00,0x20,0xdc,0x01,0x00,0x7d,0x05]
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flat_load_sbyte v5, v[1:2]
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// GFX10: encoding: [0x00,0x00,0x24,0xdc,0x01,0x00,0x7d,0x05]
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flat_load_ushort v5, v[1:2]
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// GFX10: encoding: [0x00,0x00,0x28,0xdc,0x01,0x00,0x7d,0x05]
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flat_load_sshort v5, v[1:2]
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// GFX10: encoding: [0x00,0x00,0x2c,0xdc,0x01,0x00,0x7d,0x05]
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flat_load_dword v5, v[1:2]
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// GFX10: encoding: [0x00,0x00,0x30,0xdc,0x01,0x00,0x7d,0x05]
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flat_load_dwordx2 v[5:6], v[1:2]
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// GFX10: encoding: [0x00,0x00,0x34,0xdc,0x01,0x00,0x7d,0x05]
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flat_load_dwordx3 v[5:7], v[1:2]
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// GFX10: encoding: [0x00,0x00,0x3c,0xdc,0x01,0x00,0x7d,0x05]
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flat_load_dwordx4 v[5:8], v[1:2]
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// GFX10: encoding: [0x00,0x00,0x38,0xdc,0x01,0x00,0x7d,0x05]
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flat_store_byte v[1:2], v2
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// GFX10: encoding: [0x00,0x00,0x60,0xdc,0x01,0x02,0x7d,0x00]
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flat_store_short v[1:2], v2
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// GFX10: encoding: [0x00,0x00,0x68,0xdc,0x01,0x02,0x7d,0x00]
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flat_store_dword v[1:2], v2
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// GFX10: encoding: [0x00,0x00,0x70,0xdc,0x01,0x02,0x7d,0x00]
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flat_store_dwordx2 v[1:2], v[2:3]
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// GFX10: encoding: [0x00,0x00,0x74,0xdc,0x01,0x02,0x7d,0x00]
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flat_store_dwordx3 v[1:2], v[2:4]
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// GFX10: encoding: [0x00,0x00,0x7c,0xdc,0x01,0x02,0x7d,0x00]
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flat_store_dwordx4 v[1:2], v[2:5]
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// GFX10: encoding: [0x00,0x00,0x78,0xdc,0x01,0x02,0x7d,0x00]
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flat_atomic_swap v[1:2], v2
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// GFX10: encoding: [0x00,0x00,0xc0,0xdc,0x01,0x02,0x7d,0x00]
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flat_atomic_cmpswap v[1:2], v[2:3]
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// GFX10: encoding: [0x00,0x00,0xc4,0xdc,0x01,0x02,0x7d,0x00]
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flat_atomic_add v[1:2], v2
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// GFX10: encoding: [0x00,0x00,0xc8,0xdc,0x01,0x02,0x7d,0x00]
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flat_atomic_sub v[1:2], v2
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// GFX10: encoding: [0x00,0x00,0xcc,0xdc,0x01,0x02,0x7d,0x00]
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flat_atomic_smin v[1:2], v2
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// GFX10: encoding: [0x00,0x00,0xd4,0xdc,0x01,0x02,0x7d,0x00]
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flat_atomic_umin v[1:2], v2
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// GFX10: encoding: [0x00,0x00,0xd8,0xdc,0x01,0x02,0x7d,0x00]
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flat_atomic_smax v[1:2], v2
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// GFX10: encoding: [0x00,0x00,0xdc,0xdc,0x01,0x02,0x7d,0x00]
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flat_atomic_umax v[1:2], v2
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// GFX10: encoding: [0x00,0x00,0xe0,0xdc,0x01,0x02,0x7d,0x00]
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flat_atomic_and v[1:2], v2
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// GFX10: encoding: [0x00,0x00,0xe4,0xdc,0x01,0x02,0x7d,0x00]
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flat_atomic_or v[1:2], v2
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// GFX10: encoding: [0x00,0x00,0xe8,0xdc,0x01,0x02,0x7d,0x00]
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flat_atomic_xor v[1:2], v2
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// GFX10: encoding: [0x00,0x00,0xec,0xdc,0x01,0x02,0x7d,0x00]
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flat_atomic_inc v[1:2], v2
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// GFX10: encoding: [0x00,0x00,0xf0,0xdc,0x01,0x02,0x7d,0x00]
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flat_atomic_dec v[1:2], v2
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// GFX10: encoding: [0x00,0x00,0xf4,0xdc,0x01,0x02,0x7d,0x00]
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flat_atomic_swap_x2 v[1:2], v[2:3]
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// GFX10: encoding: [0x00,0x00,0x40,0xdd,0x01,0x02,0x7d,0x00]
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flat_atomic_cmpswap_x2 v[1:2], v[2:5]
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// GFX10: encoding: [0x00,0x00,0x44,0xdd,0x01,0x02,0x7d,0x00]
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flat_atomic_add_x2 v[1:2], v[2:3]
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// GFX10: encoding: [0x00,0x00,0x48,0xdd,0x01,0x02,0x7d,0x00]
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flat_atomic_sub_x2 v[1:2], v[2:3]
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// GFX10: encoding: [0x00,0x00,0x4c,0xdd,0x01,0x02,0x7d,0x00]
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flat_atomic_smin_x2 v[1:2], v[2:3]
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// GFX10: encoding: [0x00,0x00,0x54,0xdd,0x01,0x02,0x7d,0x00]
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flat_atomic_umin_x2 v[1:2], v[2:3]
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// GFX10: encoding: [0x00,0x00,0x58,0xdd,0x01,0x02,0x7d,0x00]
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flat_atomic_smax_x2 v[1:2], v[2:3]
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// GFX10: encoding: [0x00,0x00,0x5c,0xdd,0x01,0x02,0x7d,0x00]
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flat_atomic_umax_x2 v[1:2], v[2:3]
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// GFX10: encoding: [0x00,0x00,0x60,0xdd,0x01,0x02,0x7d,0x00]
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flat_atomic_and_x2 v[1:2], v[2:3]
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// GFX10: encoding: [0x00,0x00,0x64,0xdd,0x01,0x02,0x7d,0x00]
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flat_atomic_or_x2 v[1:2], v[2:3]
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// GFX10: encoding: [0x00,0x00,0x68,0xdd,0x01,0x02,0x7d,0x00]
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flat_atomic_xor_x2 v[1:2], v[2:3]
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// GFX10: encoding: [0x00,0x00,0x6c,0xdd,0x01,0x02,0x7d,0x00]
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flat_atomic_inc_x2 v[1:2], v[2:3]
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// GFX10: encoding: [0x00,0x00,0x70,0xdd,0x01,0x02,0x7d,0x00]
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flat_atomic_dec_x2 v[1:2], v[2:3]
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// GFX10: encoding: [0x00,0x00,0x74,0xdd,0x01,0x02,0x7d,0x00]
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// Also see flat-gfx10.s, flat-global.s, flat-scratch-instructions.s.
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File diff suppressed because it is too large
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File diff suppressed because it is too large
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File diff suppressed because it is too large
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File diff suppressed because it is too large
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File diff suppressed because it is too large
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@ -0,0 +1,82 @@
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// RUN: llvm-mc -arch=amdgcn -mcpu=bonaire -show-encoding %s | FileCheck %s
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exp mrt0 v0, v0, v0, v0
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// CHECK: [0x0f,0x00,0x00,0xf8,0x00,0x00,0x00,0x00]
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exp mrtz v0, v0, v0, v0
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// CHECK: [0x8f,0x00,0x00,0xf8,0x00,0x00,0x00,0x00]
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exp null v0, v0, v0, v0
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// CHECK: [0x9f,0x00,0x00,0xf8,0x00,0x00,0x00,0x00]
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exp pos0 v0, v0, v0, v0
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// CHECK: [0xcf,0x00,0x00,0xf8,0x00,0x00,0x00,0x00]
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exp param0 v0, v0, v0, v0
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// CHECK: [0x0f,0x02,0x00,0xf8,0x00,0x00,0x00,0x00]
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exp mrt0 v255, v0, v0, v0
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// CHECK: [0x0f,0x00,0x00,0xf8,0xff,0x00,0x00,0x00]
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exp mrt0 v0, v255, v0, v0
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// CHECK: [0x0f,0x00,0x00,0xf8,0x00,0xff,0x00,0x00]
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exp mrt0 v0, v0, v255, v0
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// CHECK: [0x0f,0x00,0x00,0xf8,0x00,0x00,0xff,0x00]
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exp mrt0 v0, v0, v0, v255
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// CHECK: [0x0f,0x00,0x00,0xf8,0x00,0x00,0x00,0xff]
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exp mrt0 v0, off, off, off
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// CHECK: [0x01,0x00,0x00,0xf8,0x00,0x00,0x00,0x00]
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exp mrt0 off, v0, off, off
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// CHECK: [0x02,0x00,0x00,0xf8,0x00,0x00,0x00,0x00]
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exp mrt0 v0, v0, off, off
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// CHECK: [0x03,0x00,0x00,0xf8,0x00,0x00,0x00,0x00]
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exp mrt0 off, off, v0, off
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// CHECK: [0x04,0x00,0x00,0xf8,0x00,0x00,0x00,0x00]
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exp mrt0 v0, off, v0, off
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// CHECK: [0x05,0x00,0x00,0xf8,0x00,0x00,0x00,0x00]
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exp mrt0 off, v0, v0, off
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// CHECK: [0x06,0x00,0x00,0xf8,0x00,0x00,0x00,0x00]
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exp mrt0 v0, v0, v0, off
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// CHECK: [0x07,0x00,0x00,0xf8,0x00,0x00,0x00,0x00]
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exp mrt0 off, off, off, v0
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// CHECK: [0x08,0x00,0x00,0xf8,0x00,0x00,0x00,0x00]
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exp mrt0 v0, off, off, v0
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// CHECK: [0x09,0x00,0x00,0xf8,0x00,0x00,0x00,0x00]
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exp mrt0 off, v0, off, v0
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// CHECK: [0x0a,0x00,0x00,0xf8,0x00,0x00,0x00,0x00]
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exp mrt0 v0, v0, off, v0
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// CHECK: [0x0b,0x00,0x00,0xf8,0x00,0x00,0x00,0x00]
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exp mrt0 off, off, v0, v0
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// CHECK: [0x0c,0x00,0x00,0xf8,0x00,0x00,0x00,0x00]
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exp mrt0 v0, off, v0, v0
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// CHECK: [0x0d,0x00,0x00,0xf8,0x00,0x00,0x00,0x00]
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exp mrt0 off, v0, v0, v0
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// CHECK: [0x0e,0x00,0x00,0xf8,0x00,0x00,0x00,0x00]
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exp mrt0 off, off, off, off
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// CHECK: [0x00,0x00,0x00,0xf8,0x00,0x00,0x00,0x00]
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exp mrt0 v0, v0, v0, v0 done
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// CHECK: [0x0f,0x08,0x00,0xf8,0x00,0x00,0x00,0x00]
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exp mrt0 v0, v0, v0, v0 compr
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// CHECK: [0x0f,0x04,0x00,0xf8,0x00,0x00,0x00,0x00]
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exp mrt0 v0, v0, v0, v0 vm
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// CHECK: [0x0f,0x10,0x00,0xf8,0x00,0x00,0x00,0x00]
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// RUN: llvm-mc -arch=amdgcn -mcpu=bonaire -show-encoding %s | FileCheck %s
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flat_load_ubyte v5, v[1:2]
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// CHECK: [0x00,0x00,0x20,0xdc,0x01,0x00,0x00,0x05]
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flat_load_ubyte v255, v[1:2]
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// CHECK: [0x00,0x00,0x20,0xdc,0x01,0x00,0x00,0xff]
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flat_load_ubyte v5, v[254:255]
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// CHECK: [0x00,0x00,0x20,0xdc,0xfe,0x00,0x00,0x05]
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flat_load_ubyte v5, v[1:2] glc
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// CHECK: [0x00,0x00,0x21,0xdc,0x01,0x00,0x00,0x05]
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flat_load_ubyte v5, v[1:2] slc
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// CHECK: [0x00,0x00,0x22,0xdc,0x01,0x00,0x00,0x05]
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flat_load_sbyte v5, v[1:2]
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// CHECK: [0x00,0x00,0x24,0xdc,0x01,0x00,0x00,0x05]
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flat_load_sbyte v255, v[1:2]
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// CHECK: [0x00,0x00,0x24,0xdc,0x01,0x00,0x00,0xff]
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flat_load_sbyte v5, v[254:255]
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// CHECK: [0x00,0x00,0x24,0xdc,0xfe,0x00,0x00,0x05]
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flat_load_sbyte v5, v[1:2] glc
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// CHECK: [0x00,0x00,0x25,0xdc,0x01,0x00,0x00,0x05]
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flat_load_sbyte v5, v[1:2] slc
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// CHECK: [0x00,0x00,0x26,0xdc,0x01,0x00,0x00,0x05]
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flat_load_ushort v5, v[1:2]
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// CHECK: [0x00,0x00,0x28,0xdc,0x01,0x00,0x00,0x05]
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flat_load_ushort v255, v[1:2]
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// CHECK: [0x00,0x00,0x28,0xdc,0x01,0x00,0x00,0xff]
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flat_load_ushort v5, v[254:255]
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// CHECK: [0x00,0x00,0x28,0xdc,0xfe,0x00,0x00,0x05]
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flat_load_ushort v5, v[1:2] glc
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// CHECK: [0x00,0x00,0x29,0xdc,0x01,0x00,0x00,0x05]
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flat_load_ushort v5, v[1:2] slc
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// CHECK: [0x00,0x00,0x2a,0xdc,0x01,0x00,0x00,0x05]
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flat_load_sshort v5, v[1:2]
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// CHECK: [0x00,0x00,0x2c,0xdc,0x01,0x00,0x00,0x05]
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flat_load_sshort v255, v[1:2]
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// CHECK: [0x00,0x00,0x2c,0xdc,0x01,0x00,0x00,0xff]
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flat_load_sshort v5, v[254:255]
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// CHECK: [0x00,0x00,0x2c,0xdc,0xfe,0x00,0x00,0x05]
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flat_load_sshort v5, v[1:2] glc
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// CHECK: [0x00,0x00,0x2d,0xdc,0x01,0x00,0x00,0x05]
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flat_load_sshort v5, v[1:2] slc
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// CHECK: [0x00,0x00,0x2e,0xdc,0x01,0x00,0x00,0x05]
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flat_load_dword v5, v[1:2]
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// CHECK: [0x00,0x00,0x30,0xdc,0x01,0x00,0x00,0x05]
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flat_load_dword v255, v[1:2]
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// CHECK: [0x00,0x00,0x30,0xdc,0x01,0x00,0x00,0xff]
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flat_load_dword v5, v[254:255]
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// CHECK: [0x00,0x00,0x30,0xdc,0xfe,0x00,0x00,0x05]
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flat_load_dword v5, v[1:2] glc
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// CHECK: [0x00,0x00,0x31,0xdc,0x01,0x00,0x00,0x05]
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flat_load_dword v5, v[1:2] slc
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// CHECK: [0x00,0x00,0x32,0xdc,0x01,0x00,0x00,0x05]
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flat_load_dwordx2 v[5:6], v[1:2]
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// CHECK: [0x00,0x00,0x34,0xdc,0x01,0x00,0x00,0x05]
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flat_load_dwordx2 v[254:255], v[1:2]
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// CHECK: [0x00,0x00,0x34,0xdc,0x01,0x00,0x00,0xfe]
|
||||
|
||||
flat_load_dwordx2 v[5:6], v[254:255]
|
||||
// CHECK: [0x00,0x00,0x34,0xdc,0xfe,0x00,0x00,0x05]
|
||||
|
||||
flat_load_dwordx2 v[5:6], v[1:2] glc
|
||||
// CHECK: [0x00,0x00,0x35,0xdc,0x01,0x00,0x00,0x05]
|
||||
|
||||
flat_load_dwordx2 v[5:6], v[1:2] slc
|
||||
// CHECK: [0x00,0x00,0x36,0xdc,0x01,0x00,0x00,0x05]
|
||||
|
||||
flat_load_dwordx4 v[5:8], v[1:2]
|
||||
// CHECK: [0x00,0x00,0x38,0xdc,0x01,0x00,0x00,0x05]
|
||||
|
||||
flat_load_dwordx4 v[252:255], v[1:2]
|
||||
// CHECK: [0x00,0x00,0x38,0xdc,0x01,0x00,0x00,0xfc]
|
||||
|
||||
flat_load_dwordx4 v[5:8], v[254:255]
|
||||
// CHECK: [0x00,0x00,0x38,0xdc,0xfe,0x00,0x00,0x05]
|
||||
|
||||
flat_load_dwordx4 v[5:8], v[1:2] glc
|
||||
// CHECK: [0x00,0x00,0x39,0xdc,0x01,0x00,0x00,0x05]
|
||||
|
||||
flat_load_dwordx4 v[5:8], v[1:2] slc
|
||||
// CHECK: [0x00,0x00,0x3a,0xdc,0x01,0x00,0x00,0x05]
|
||||
|
||||
flat_load_dwordx3 v[5:7], v[1:2]
|
||||
// CHECK: [0x00,0x00,0x3c,0xdc,0x01,0x00,0x00,0x05]
|
||||
|
||||
flat_load_dwordx3 v[253:255], v[1:2]
|
||||
// CHECK: [0x00,0x00,0x3c,0xdc,0x01,0x00,0x00,0xfd]
|
||||
|
||||
flat_load_dwordx3 v[5:7], v[254:255]
|
||||
// CHECK: [0x00,0x00,0x3c,0xdc,0xfe,0x00,0x00,0x05]
|
||||
|
||||
flat_load_dwordx3 v[5:7], v[1:2] glc
|
||||
// CHECK: [0x00,0x00,0x3d,0xdc,0x01,0x00,0x00,0x05]
|
||||
|
||||
flat_load_dwordx3 v[5:7], v[1:2] slc
|
||||
// CHECK: [0x00,0x00,0x3e,0xdc,0x01,0x00,0x00,0x05]
|
||||
|
||||
flat_store_byte v[1:2], v2
|
||||
// CHECK: [0x00,0x00,0x60,0xdc,0x01,0x02,0x00,0x00]
|
||||
|
||||
flat_store_byte v[254:255], v2
|
||||
// CHECK: [0x00,0x00,0x60,0xdc,0xfe,0x02,0x00,0x00]
|
||||
|
||||
flat_store_byte v[1:2], v255
|
||||
// CHECK: [0x00,0x00,0x60,0xdc,0x01,0xff,0x00,0x00]
|
||||
|
||||
flat_store_byte v[1:2], v2 glc
|
||||
// CHECK: [0x00,0x00,0x61,0xdc,0x01,0x02,0x00,0x00]
|
||||
|
||||
flat_store_byte v[1:2], v2 slc
|
||||
// CHECK: [0x00,0x00,0x62,0xdc,0x01,0x02,0x00,0x00]
|
||||
|
||||
flat_store_short v[1:2], v2
|
||||
// CHECK: [0x00,0x00,0x68,0xdc,0x01,0x02,0x00,0x00]
|
||||
|
||||
flat_store_short v[254:255], v2
|
||||
// CHECK: [0x00,0x00,0x68,0xdc,0xfe,0x02,0x00,0x00]
|
||||
|
||||
flat_store_short v[1:2], v255
|
||||
// CHECK: [0x00,0x00,0x68,0xdc,0x01,0xff,0x00,0x00]
|
||||
|
||||
flat_store_short v[1:2], v2 glc
|
||||
// CHECK: [0x00,0x00,0x69,0xdc,0x01,0x02,0x00,0x00]
|
||||
|
||||
flat_store_short v[1:2], v2 slc
|
||||
// CHECK: [0x00,0x00,0x6a,0xdc,0x01,0x02,0x00,0x00]
|
||||
|
||||
flat_store_dword v[1:2], v2
|
||||
// CHECK: [0x00,0x00,0x70,0xdc,0x01,0x02,0x00,0x00]
|
||||
|
||||
flat_store_dword v[254:255], v2
|
||||
// CHECK: [0x00,0x00,0x70,0xdc,0xfe,0x02,0x00,0x00]
|
||||
|
||||
flat_store_dword v[1:2], v255
|
||||
// CHECK: [0x00,0x00,0x70,0xdc,0x01,0xff,0x00,0x00]
|
||||
|
||||
flat_store_dword v[1:2], v2 glc
|
||||
// CHECK: [0x00,0x00,0x71,0xdc,0x01,0x02,0x00,0x00]
|
||||
|
||||
flat_store_dword v[1:2], v2 slc
|
||||
// CHECK: [0x00,0x00,0x72,0xdc,0x01,0x02,0x00,0x00]
|
||||
|
||||
flat_store_dwordx2 v[1:2], v[2:3]
|
||||
// CHECK: [0x00,0x00,0x74,0xdc,0x01,0x02,0x00,0x00]
|
||||
|
||||
flat_store_dwordx2 v[254:255], v[2:3]
|
||||
// CHECK: [0x00,0x00,0x74,0xdc,0xfe,0x02,0x00,0x00]
|
||||
|
||||
flat_store_dwordx2 v[1:2], v[254:255]
|
||||
// CHECK: [0x00,0x00,0x74,0xdc,0x01,0xfe,0x00,0x00]
|
||||
|
||||
flat_store_dwordx2 v[1:2], v[2:3] glc
|
||||
// CHECK: [0x00,0x00,0x75,0xdc,0x01,0x02,0x00,0x00]
|
||||
|
||||
flat_store_dwordx2 v[1:2], v[2:3] slc
|
||||
// CHECK: [0x00,0x00,0x76,0xdc,0x01,0x02,0x00,0x00]
|
||||
|
||||
flat_store_dwordx4 v[1:2], v[2:5]
|
||||
// CHECK: [0x00,0x00,0x78,0xdc,0x01,0x02,0x00,0x00]
|
||||
|
||||
flat_store_dwordx4 v[254:255], v[2:5]
|
||||
// CHECK: [0x00,0x00,0x78,0xdc,0xfe,0x02,0x00,0x00]
|
||||
|
||||
flat_store_dwordx4 v[1:2], v[252:255]
|
||||
// CHECK: [0x00,0x00,0x78,0xdc,0x01,0xfc,0x00,0x00]
|
||||
|
||||
flat_store_dwordx4 v[1:2], v[2:5] glc
|
||||
// CHECK: [0x00,0x00,0x79,0xdc,0x01,0x02,0x00,0x00]
|
||||
|
||||
flat_store_dwordx4 v[1:2], v[2:5] slc
|
||||
// CHECK: [0x00,0x00,0x7a,0xdc,0x01,0x02,0x00,0x00]
|
||||
|
||||
flat_store_dwordx3 v[1:2], v[2:4]
|
||||
// CHECK: [0x00,0x00,0x7c,0xdc,0x01,0x02,0x00,0x00]
|
||||
|
||||
flat_store_dwordx3 v[254:255], v[2:4]
|
||||
// CHECK: [0x00,0x00,0x7c,0xdc,0xfe,0x02,0x00,0x00]
|
||||
|
||||
flat_store_dwordx3 v[1:2], v[253:255]
|
||||
// CHECK: [0x00,0x00,0x7c,0xdc,0x01,0xfd,0x00,0x00]
|
||||
|
||||
flat_store_dwordx3 v[1:2], v[2:4] glc
|
||||
// CHECK: [0x00,0x00,0x7d,0xdc,0x01,0x02,0x00,0x00]
|
||||
|
||||
flat_store_dwordx3 v[1:2], v[2:4] slc
|
||||
// CHECK: [0x00,0x00,0x7e,0xdc,0x01,0x02,0x00,0x00]
|
||||
|
||||
flat_atomic_swap v[1:2], v2
|
||||
// CHECK: [0x00,0x00,0xc0,0xdc,0x01,0x02,0x00,0x00]
|
||||
|
||||
flat_atomic_swap v[254:255], v2
|
||||
// CHECK: [0x00,0x00,0xc0,0xdc,0xfe,0x02,0x00,0x00]
|
||||
|
||||
flat_atomic_swap v[1:2], v255
|
||||
// CHECK: [0x00,0x00,0xc0,0xdc,0x01,0xff,0x00,0x00]
|
||||
|
||||
flat_atomic_swap v0, v[1:2], v2 glc
|
||||
// CHECK: [0x00,0x00,0xc1,0xdc,0x01,0x02,0x00,0x00]
|
||||
|
||||
flat_atomic_swap v[1:2], v2 slc
|
||||
// CHECK: [0x00,0x00,0xc2,0xdc,0x01,0x02,0x00,0x00]
|
||||
|
||||
flat_atomic_cmpswap v[1:2], v[2:3]
|
||||
// CHECK: [0x00,0x00,0xc4,0xdc,0x01,0x02,0x00,0x00]
|
||||
|
||||
flat_atomic_cmpswap v[254:255], v[2:3]
|
||||
// CHECK: [0x00,0x00,0xc4,0xdc,0xfe,0x02,0x00,0x00]
|
||||
|
||||
flat_atomic_cmpswap v[1:2], v[254:255]
|
||||
// CHECK: [0x00,0x00,0xc4,0xdc,0x01,0xfe,0x00,0x00]
|
||||
|
||||
flat_atomic_cmpswap v0, v[1:2], v[2:3] glc
|
||||
// CHECK: [0x00,0x00,0xc5,0xdc,0x01,0x02,0x00,0x00]
|
||||
|
||||
flat_atomic_cmpswap v[1:2], v[2:3] slc
|
||||
// CHECK: [0x00,0x00,0xc6,0xdc,0x01,0x02,0x00,0x00]
|
||||
|
||||
flat_atomic_add v[1:2], v2
|
||||
// CHECK: [0x00,0x00,0xc8,0xdc,0x01,0x02,0x00,0x00]
|
||||
|
||||
flat_atomic_add v[254:255], v2
|
||||
// CHECK: [0x00,0x00,0xc8,0xdc,0xfe,0x02,0x00,0x00]
|
||||
|
||||
flat_atomic_add v[1:2], v255
|
||||
// CHECK: [0x00,0x00,0xc8,0xdc,0x01,0xff,0x00,0x00]
|
||||
|
||||
flat_atomic_add v0, v[1:2], v2 glc
|
||||
// CHECK: [0x00,0x00,0xc9,0xdc,0x01,0x02,0x00,0x00]
|
||||
|
||||
flat_atomic_add v[1:2], v2 slc
|
||||
// CHECK: [0x00,0x00,0xca,0xdc,0x01,0x02,0x00,0x00]
|
||||
|
||||
flat_atomic_sub v[1:2], v2
|
||||
// CHECK: [0x00,0x00,0xcc,0xdc,0x01,0x02,0x00,0x00]
|
||||
|
||||
flat_atomic_sub v[254:255], v2
|
||||
// CHECK: [0x00,0x00,0xcc,0xdc,0xfe,0x02,0x00,0x00]
|
||||
|
||||
flat_atomic_sub v[1:2], v255
|
||||
// CHECK: [0x00,0x00,0xcc,0xdc,0x01,0xff,0x00,0x00]
|
||||
|
||||
flat_atomic_sub v0, v[1:2], v2 glc
|
||||
// CHECK: [0x00,0x00,0xcd,0xdc,0x01,0x02,0x00,0x00]
|
||||
|
||||
flat_atomic_sub v[1:2], v2 slc
|
||||
// CHECK: [0x00,0x00,0xce,0xdc,0x01,0x02,0x00,0x00]
|
||||
|
||||
flat_atomic_smin v[1:2], v2
|
||||
// CHECK: [0x00,0x00,0xd4,0xdc,0x01,0x02,0x00,0x00]
|
||||
|
||||
flat_atomic_smin v[254:255], v2
|
||||
// CHECK: [0x00,0x00,0xd4,0xdc,0xfe,0x02,0x00,0x00]
|
||||
|
||||
flat_atomic_smin v[1:2], v255
|
||||
// CHECK: [0x00,0x00,0xd4,0xdc,0x01,0xff,0x00,0x00]
|
||||
|
||||
flat_atomic_smin v0, v[1:2], v2 glc
|
||||
// CHECK: [0x00,0x00,0xd5,0xdc,0x01,0x02,0x00,0x00]
|
||||
|
||||
flat_atomic_smin v[1:2], v2 slc
|
||||
// CHECK: [0x00,0x00,0xd6,0xdc,0x01,0x02,0x00,0x00]
|
||||
|
||||
flat_atomic_umin v[1:2], v2
|
||||
// CHECK: [0x00,0x00,0xd8,0xdc,0x01,0x02,0x00,0x00]
|
||||
|
||||
flat_atomic_umin v[254:255], v2
|
||||
// CHECK: [0x00,0x00,0xd8,0xdc,0xfe,0x02,0x00,0x00]
|
||||
|
||||
flat_atomic_umin v[1:2], v255
|
||||
// CHECK: [0x00,0x00,0xd8,0xdc,0x01,0xff,0x00,0x00]
|
||||
|
||||
flat_atomic_umin v0, v[1:2], v2 glc
|
||||
// CHECK: [0x00,0x00,0xd9,0xdc,0x01,0x02,0x00,0x00]
|
||||
|
||||
flat_atomic_umin v[1:2], v2 slc
|
||||
// CHECK: [0x00,0x00,0xda,0xdc,0x01,0x02,0x00,0x00]
|
||||
|
||||
flat_atomic_smax v[1:2], v2
|
||||
// CHECK: [0x00,0x00,0xdc,0xdc,0x01,0x02,0x00,0x00]
|
||||
|
||||
flat_atomic_smax v[254:255], v2
|
||||
// CHECK: [0x00,0x00,0xdc,0xdc,0xfe,0x02,0x00,0x00]
|
||||
|
||||
flat_atomic_smax v[1:2], v255
|
||||
// CHECK: [0x00,0x00,0xdc,0xdc,0x01,0xff,0x00,0x00]
|
||||
|
||||
flat_atomic_smax v0, v[1:2], v2 glc
|
||||
// CHECK: [0x00,0x00,0xdd,0xdc,0x01,0x02,0x00,0x00]
|
||||
|
||||
flat_atomic_smax v[1:2], v2 slc
|
||||
// CHECK: [0x00,0x00,0xde,0xdc,0x01,0x02,0x00,0x00]
|
||||
|
||||
flat_atomic_umax v[1:2], v2
|
||||
// CHECK: [0x00,0x00,0xe0,0xdc,0x01,0x02,0x00,0x00]
|
||||
|
||||
flat_atomic_umax v[254:255], v2
|
||||
// CHECK: [0x00,0x00,0xe0,0xdc,0xfe,0x02,0x00,0x00]
|
||||
|
||||
flat_atomic_umax v[1:2], v255
|
||||
// CHECK: [0x00,0x00,0xe0,0xdc,0x01,0xff,0x00,0x00]
|
||||
|
||||
flat_atomic_umax v0, v[1:2], v2 glc
|
||||
// CHECK: [0x00,0x00,0xe1,0xdc,0x01,0x02,0x00,0x00]
|
||||
|
||||
flat_atomic_umax v[1:2], v2 slc
|
||||
// CHECK: [0x00,0x00,0xe2,0xdc,0x01,0x02,0x00,0x00]
|
||||
|
||||
flat_atomic_and v[1:2], v2
|
||||
// CHECK: [0x00,0x00,0xe4,0xdc,0x01,0x02,0x00,0x00]
|
||||
|
||||
flat_atomic_and v[254:255], v2
|
||||
// CHECK: [0x00,0x00,0xe4,0xdc,0xfe,0x02,0x00,0x00]
|
||||
|
||||
flat_atomic_and v[1:2], v255
|
||||
// CHECK: [0x00,0x00,0xe4,0xdc,0x01,0xff,0x00,0x00]
|
||||
|
||||
flat_atomic_and v0, v[1:2], v2 glc
|
||||
// CHECK: [0x00,0x00,0xe5,0xdc,0x01,0x02,0x00,0x00]
|
||||
|
||||
flat_atomic_and v[1:2], v2 slc
|
||||
// CHECK: [0x00,0x00,0xe6,0xdc,0x01,0x02,0x00,0x00]
|
||||
|
||||
flat_atomic_or v[1:2], v2
|
||||
// CHECK: [0x00,0x00,0xe8,0xdc,0x01,0x02,0x00,0x00]
|
||||
|
||||
flat_atomic_or v[254:255], v2
|
||||
// CHECK: [0x00,0x00,0xe8,0xdc,0xfe,0x02,0x00,0x00]
|
||||
|
||||
flat_atomic_or v[1:2], v255
|
||||
// CHECK: [0x00,0x00,0xe8,0xdc,0x01,0xff,0x00,0x00]
|
||||
|
||||
flat_atomic_or v0, v[1:2], v2 glc
|
||||
// CHECK: [0x00,0x00,0xe9,0xdc,0x01,0x02,0x00,0x00]
|
||||
|
||||
flat_atomic_or v[1:2], v2 slc
|
||||
// CHECK: [0x00,0x00,0xea,0xdc,0x01,0x02,0x00,0x00]
|
||||
|
||||
flat_atomic_xor v[1:2], v2
|
||||
// CHECK: [0x00,0x00,0xec,0xdc,0x01,0x02,0x00,0x00]
|
||||
|
||||
flat_atomic_xor v[254:255], v2
|
||||
// CHECK: [0x00,0x00,0xec,0xdc,0xfe,0x02,0x00,0x00]
|
||||
|
||||
flat_atomic_xor v[1:2], v255
|
||||
// CHECK: [0x00,0x00,0xec,0xdc,0x01,0xff,0x00,0x00]
|
||||
|
||||
flat_atomic_xor v0, v[1:2], v2 glc
|
||||
// CHECK: [0x00,0x00,0xed,0xdc,0x01,0x02,0x00,0x00]
|
||||
|
||||
flat_atomic_xor v[1:2], v2 slc
|
||||
// CHECK: [0x00,0x00,0xee,0xdc,0x01,0x02,0x00,0x00]
|
||||
|
||||
flat_atomic_inc v[1:2], v2
|
||||
// CHECK: [0x00,0x00,0xf0,0xdc,0x01,0x02,0x00,0x00]
|
||||
|
||||
flat_atomic_inc v[254:255], v2
|
||||
// CHECK: [0x00,0x00,0xf0,0xdc,0xfe,0x02,0x00,0x00]
|
||||
|
||||
flat_atomic_inc v[1:2], v255
|
||||
// CHECK: [0x00,0x00,0xf0,0xdc,0x01,0xff,0x00,0x00]
|
||||
|
||||
flat_atomic_inc v0, v[1:2], v2 glc
|
||||
// CHECK: [0x00,0x00,0xf1,0xdc,0x01,0x02,0x00,0x00]
|
||||
|
||||
flat_atomic_inc v[1:2], v2 slc
|
||||
// CHECK: [0x00,0x00,0xf2,0xdc,0x01,0x02,0x00,0x00]
|
||||
|
||||
flat_atomic_dec v[1:2], v2
|
||||
// CHECK: [0x00,0x00,0xf4,0xdc,0x01,0x02,0x00,0x00]
|
||||
|
||||
flat_atomic_dec v[254:255], v2
|
||||
// CHECK: [0x00,0x00,0xf4,0xdc,0xfe,0x02,0x00,0x00]
|
||||
|
||||
flat_atomic_dec v[1:2], v255
|
||||
// CHECK: [0x00,0x00,0xf4,0xdc,0x01,0xff,0x00,0x00]
|
||||
|
||||
flat_atomic_dec v0, v[1:2], v2 glc
|
||||
// CHECK: [0x00,0x00,0xf5,0xdc,0x01,0x02,0x00,0x00]
|
||||
|
||||
flat_atomic_dec v[1:2], v2 slc
|
||||
// CHECK: [0x00,0x00,0xf6,0xdc,0x01,0x02,0x00,0x00]
|
||||
|
||||
flat_atomic_fcmpswap v[1:2], v[2:3]
|
||||
// CHECK: [0x00,0x00,0xf8,0xdc,0x01,0x02,0x00,0x00]
|
||||
|
||||
flat_atomic_fcmpswap v[254:255], v[2:3]
|
||||
// CHECK: [0x00,0x00,0xf8,0xdc,0xfe,0x02,0x00,0x00]
|
||||
|
||||
flat_atomic_fcmpswap v[1:2], v[254:255]
|
||||
// CHECK: [0x00,0x00,0xf8,0xdc,0x01,0xfe,0x00,0x00]
|
||||
|
||||
flat_atomic_fcmpswap v0, v[1:2], v[2:3] glc
|
||||
// CHECK: [0x00,0x00,0xf9,0xdc,0x01,0x02,0x00,0x00]
|
||||
|
||||
flat_atomic_fcmpswap v[1:2], v[2:3] slc
|
||||
// CHECK: [0x00,0x00,0xfa,0xdc,0x01,0x02,0x00,0x00]
|
||||
|
||||
flat_atomic_fmin v[1:2], v2
|
||||
// CHECK: [0x00,0x00,0xfc,0xdc,0x01,0x02,0x00,0x00]
|
||||
|
||||
flat_atomic_fmin v[254:255], v2
|
||||
// CHECK: [0x00,0x00,0xfc,0xdc,0xfe,0x02,0x00,0x00]
|
||||
|
||||
flat_atomic_fmin v[1:2], v255
|
||||
// CHECK: [0x00,0x00,0xfc,0xdc,0x01,0xff,0x00,0x00]
|
||||
|
||||
flat_atomic_fmin v0, v[1:2], v2 glc
|
||||
// CHECK: [0x00,0x00,0xfd,0xdc,0x01,0x02,0x00,0x00]
|
||||
|
||||
flat_atomic_fmin v[1:2], v2 slc
|
||||
// CHECK: [0x00,0x00,0xfe,0xdc,0x01,0x02,0x00,0x00]
|
||||
|
||||
flat_atomic_fmax v[1:2], v2
|
||||
// CHECK: [0x00,0x00,0x00,0xdd,0x01,0x02,0x00,0x00]
|
||||
|
||||
flat_atomic_fmax v[254:255], v2
|
||||
// CHECK: [0x00,0x00,0x00,0xdd,0xfe,0x02,0x00,0x00]
|
||||
|
||||
flat_atomic_fmax v[1:2], v255
|
||||
// CHECK: [0x00,0x00,0x00,0xdd,0x01,0xff,0x00,0x00]
|
||||
|
||||
flat_atomic_fmax v0, v[1:2], v2 glc
|
||||
// CHECK: [0x00,0x00,0x01,0xdd,0x01,0x02,0x00,0x00]
|
||||
|
||||
flat_atomic_fmax v[1:2], v2 slc
|
||||
// CHECK: [0x00,0x00,0x02,0xdd,0x01,0x02,0x00,0x00]
|
||||
|
||||
flat_atomic_swap_x2 v[1:2], v[2:3]
|
||||
// CHECK: [0x00,0x00,0x40,0xdd,0x01,0x02,0x00,0x00]
|
||||
|
||||
flat_atomic_swap_x2 v[254:255], v[2:3]
|
||||
// CHECK: [0x00,0x00,0x40,0xdd,0xfe,0x02,0x00,0x00]
|
||||
|
||||
flat_atomic_swap_x2 v[1:2], v[254:255]
|
||||
// CHECK: [0x00,0x00,0x40,0xdd,0x01,0xfe,0x00,0x00]
|
||||
|
||||
flat_atomic_swap_x2 v[0:1], v[1:2], v[2:3] glc
|
||||
// CHECK: [0x00,0x00,0x41,0xdd,0x01,0x02,0x00,0x00]
|
||||
|
||||
flat_atomic_swap_x2 v[1:2], v[2:3] slc
|
||||
// CHECK: [0x00,0x00,0x42,0xdd,0x01,0x02,0x00,0x00]
|
||||
|
||||
flat_atomic_cmpswap_x2 v[1:2], v[2:5]
|
||||
// CHECK: [0x00,0x00,0x44,0xdd,0x01,0x02,0x00,0x00]
|
||||
|
||||
flat_atomic_cmpswap_x2 v[254:255], v[2:5]
|
||||
// CHECK: [0x00,0x00,0x44,0xdd,0xfe,0x02,0x00,0x00]
|
||||
|
||||
flat_atomic_cmpswap_x2 v[1:2], v[252:255]
|
||||
// CHECK: [0x00,0x00,0x44,0xdd,0x01,0xfc,0x00,0x00]
|
||||
|
||||
flat_atomic_cmpswap_x2 v[0:1], v[1:2], v[2:5] glc
|
||||
// CHECK: [0x00,0x00,0x45,0xdd,0x01,0x02,0x00,0x00]
|
||||
|
||||
flat_atomic_cmpswap_x2 v[1:2], v[2:5] slc
|
||||
// CHECK: [0x00,0x00,0x46,0xdd,0x01,0x02,0x00,0x00]
|
||||
|
||||
flat_atomic_add_x2 v[1:2], v[2:3]
|
||||
// CHECK: [0x00,0x00,0x48,0xdd,0x01,0x02,0x00,0x00]
|
||||
|
||||
flat_atomic_add_x2 v[254:255], v[2:3]
|
||||
// CHECK: [0x00,0x00,0x48,0xdd,0xfe,0x02,0x00,0x00]
|
||||
|
||||
flat_atomic_add_x2 v[1:2], v[254:255]
|
||||
// CHECK: [0x00,0x00,0x48,0xdd,0x01,0xfe,0x00,0x00]
|
||||
|
||||
flat_atomic_add_x2 v[0:1], v[1:2], v[2:3] glc
|
||||
// CHECK: [0x00,0x00,0x49,0xdd,0x01,0x02,0x00,0x00]
|
||||
|
||||
flat_atomic_add_x2 v[1:2], v[2:3] slc
|
||||
// CHECK: [0x00,0x00,0x4a,0xdd,0x01,0x02,0x00,0x00]
|
||||
|
||||
flat_atomic_sub_x2 v[1:2], v[2:3]
|
||||
// CHECK: [0x00,0x00,0x4c,0xdd,0x01,0x02,0x00,0x00]
|
||||
|
||||
flat_atomic_sub_x2 v[254:255], v[2:3]
|
||||
// CHECK: [0x00,0x00,0x4c,0xdd,0xfe,0x02,0x00,0x00]
|
||||
|
||||
flat_atomic_sub_x2 v[1:2], v[254:255]
|
||||
// CHECK: [0x00,0x00,0x4c,0xdd,0x01,0xfe,0x00,0x00]
|
||||
|
||||
flat_atomic_sub_x2 v[0:1], v[1:2], v[2:3] glc
|
||||
// CHECK: [0x00,0x00,0x4d,0xdd,0x01,0x02,0x00,0x00]
|
||||
|
||||
flat_atomic_sub_x2 v[1:2], v[2:3] slc
|
||||
// CHECK: [0x00,0x00,0x4e,0xdd,0x01,0x02,0x00,0x00]
|
||||
|
||||
flat_atomic_smin_x2 v[1:2], v[2:3]
|
||||
// CHECK: [0x00,0x00,0x54,0xdd,0x01,0x02,0x00,0x00]
|
||||
|
||||
flat_atomic_smin_x2 v[254:255], v[2:3]
|
||||
// CHECK: [0x00,0x00,0x54,0xdd,0xfe,0x02,0x00,0x00]
|
||||
|
||||
flat_atomic_smin_x2 v[1:2], v[254:255]
|
||||
// CHECK: [0x00,0x00,0x54,0xdd,0x01,0xfe,0x00,0x00]
|
||||
|
||||
flat_atomic_smin_x2 v[0:1], v[1:2], v[2:3] glc
|
||||
// CHECK: [0x00,0x00,0x55,0xdd,0x01,0x02,0x00,0x00]
|
||||
|
||||
flat_atomic_smin_x2 v[1:2], v[2:3] slc
|
||||
// CHECK: [0x00,0x00,0x56,0xdd,0x01,0x02,0x00,0x00]
|
||||
|
||||
flat_atomic_umin_x2 v[1:2], v[2:3]
|
||||
// CHECK: [0x00,0x00,0x58,0xdd,0x01,0x02,0x00,0x00]
|
||||
|
||||
flat_atomic_umin_x2 v[254:255], v[2:3]
|
||||
// CHECK: [0x00,0x00,0x58,0xdd,0xfe,0x02,0x00,0x00]
|
||||
|
||||
flat_atomic_umin_x2 v[1:2], v[254:255]
|
||||
// CHECK: [0x00,0x00,0x58,0xdd,0x01,0xfe,0x00,0x00]
|
||||
|
||||
flat_atomic_umin_x2 v[0:1], v[1:2], v[2:3] glc
|
||||
// CHECK: [0x00,0x00,0x59,0xdd,0x01,0x02,0x00,0x00]
|
||||
|
||||
flat_atomic_umin_x2 v[1:2], v[2:3] slc
|
||||
// CHECK: [0x00,0x00,0x5a,0xdd,0x01,0x02,0x00,0x00]
|
||||
|
||||
flat_atomic_smax_x2 v[1:2], v[2:3]
|
||||
// CHECK: [0x00,0x00,0x5c,0xdd,0x01,0x02,0x00,0x00]
|
||||
|
||||
flat_atomic_smax_x2 v[254:255], v[2:3]
|
||||
// CHECK: [0x00,0x00,0x5c,0xdd,0xfe,0x02,0x00,0x00]
|
||||
|
||||
flat_atomic_smax_x2 v[1:2], v[254:255]
|
||||
// CHECK: [0x00,0x00,0x5c,0xdd,0x01,0xfe,0x00,0x00]
|
||||
|
||||
flat_atomic_smax_x2 v[0:1], v[1:2], v[2:3] glc
|
||||
// CHECK: [0x00,0x00,0x5d,0xdd,0x01,0x02,0x00,0x00]
|
||||
|
||||
flat_atomic_smax_x2 v[1:2], v[2:3] slc
|
||||
// CHECK: [0x00,0x00,0x5e,0xdd,0x01,0x02,0x00,0x00]
|
||||
|
||||
flat_atomic_umax_x2 v[1:2], v[2:3]
|
||||
// CHECK: [0x00,0x00,0x60,0xdd,0x01,0x02,0x00,0x00]
|
||||
|
||||
flat_atomic_umax_x2 v[254:255], v[2:3]
|
||||
// CHECK: [0x00,0x00,0x60,0xdd,0xfe,0x02,0x00,0x00]
|
||||
|
||||
flat_atomic_umax_x2 v[1:2], v[254:255]
|
||||
// CHECK: [0x00,0x00,0x60,0xdd,0x01,0xfe,0x00,0x00]
|
||||
|
||||
flat_atomic_umax_x2 v[0:1], v[1:2], v[2:3] glc
|
||||
// CHECK: [0x00,0x00,0x61,0xdd,0x01,0x02,0x00,0x00]
|
||||
|
||||
flat_atomic_umax_x2 v[1:2], v[2:3] slc
|
||||
// CHECK: [0x00,0x00,0x62,0xdd,0x01,0x02,0x00,0x00]
|
||||
|
||||
flat_atomic_and_x2 v[1:2], v[2:3]
|
||||
// CHECK: [0x00,0x00,0x64,0xdd,0x01,0x02,0x00,0x00]
|
||||
|
||||
flat_atomic_and_x2 v[254:255], v[2:3]
|
||||
// CHECK: [0x00,0x00,0x64,0xdd,0xfe,0x02,0x00,0x00]
|
||||
|
||||
flat_atomic_and_x2 v[1:2], v[254:255]
|
||||
// CHECK: [0x00,0x00,0x64,0xdd,0x01,0xfe,0x00,0x00]
|
||||
|
||||
flat_atomic_and_x2 v[0:1], v[1:2], v[2:3] glc
|
||||
// CHECK: [0x00,0x00,0x65,0xdd,0x01,0x02,0x00,0x00]
|
||||
|
||||
flat_atomic_and_x2 v[1:2], v[2:3] slc
|
||||
// CHECK: [0x00,0x00,0x66,0xdd,0x01,0x02,0x00,0x00]
|
||||
|
||||
flat_atomic_or_x2 v[1:2], v[2:3]
|
||||
// CHECK: [0x00,0x00,0x68,0xdd,0x01,0x02,0x00,0x00]
|
||||
|
||||
flat_atomic_or_x2 v[254:255], v[2:3]
|
||||
// CHECK: [0x00,0x00,0x68,0xdd,0xfe,0x02,0x00,0x00]
|
||||
|
||||
flat_atomic_or_x2 v[1:2], v[254:255]
|
||||
// CHECK: [0x00,0x00,0x68,0xdd,0x01,0xfe,0x00,0x00]
|
||||
|
||||
flat_atomic_or_x2 v[0:1], v[1:2], v[2:3] glc
|
||||
// CHECK: [0x00,0x00,0x69,0xdd,0x01,0x02,0x00,0x00]
|
||||
|
||||
flat_atomic_or_x2 v[1:2], v[2:3] slc
|
||||
// CHECK: [0x00,0x00,0x6a,0xdd,0x01,0x02,0x00,0x00]
|
||||
|
||||
flat_atomic_xor_x2 v[1:2], v[2:3]
|
||||
// CHECK: [0x00,0x00,0x6c,0xdd,0x01,0x02,0x00,0x00]
|
||||
|
||||
flat_atomic_xor_x2 v[254:255], v[2:3]
|
||||
// CHECK: [0x00,0x00,0x6c,0xdd,0xfe,0x02,0x00,0x00]
|
||||
|
||||
flat_atomic_xor_x2 v[1:2], v[254:255]
|
||||
// CHECK: [0x00,0x00,0x6c,0xdd,0x01,0xfe,0x00,0x00]
|
||||
|
||||
flat_atomic_xor_x2 v[0:1], v[1:2], v[2:3] glc
|
||||
// CHECK: [0x00,0x00,0x6d,0xdd,0x01,0x02,0x00,0x00]
|
||||
|
||||
flat_atomic_xor_x2 v[1:2], v[2:3] slc
|
||||
// CHECK: [0x00,0x00,0x6e,0xdd,0x01,0x02,0x00,0x00]
|
||||
|
||||
flat_atomic_inc_x2 v[1:2], v[2:3]
|
||||
// CHECK: [0x00,0x00,0x70,0xdd,0x01,0x02,0x00,0x00]
|
||||
|
||||
flat_atomic_inc_x2 v[254:255], v[2:3]
|
||||
// CHECK: [0x00,0x00,0x70,0xdd,0xfe,0x02,0x00,0x00]
|
||||
|
||||
flat_atomic_inc_x2 v[1:2], v[254:255]
|
||||
// CHECK: [0x00,0x00,0x70,0xdd,0x01,0xfe,0x00,0x00]
|
||||
|
||||
flat_atomic_inc_x2 v[0:1], v[1:2], v[2:3] glc
|
||||
// CHECK: [0x00,0x00,0x71,0xdd,0x01,0x02,0x00,0x00]
|
||||
|
||||
flat_atomic_inc_x2 v[1:2], v[2:3] slc
|
||||
// CHECK: [0x00,0x00,0x72,0xdd,0x01,0x02,0x00,0x00]
|
||||
|
||||
flat_atomic_dec_x2 v[1:2], v[2:3]
|
||||
// CHECK: [0x00,0x00,0x74,0xdd,0x01,0x02,0x00,0x00]
|
||||
|
||||
flat_atomic_dec_x2 v[254:255], v[2:3]
|
||||
// CHECK: [0x00,0x00,0x74,0xdd,0xfe,0x02,0x00,0x00]
|
||||
|
||||
flat_atomic_dec_x2 v[1:2], v[254:255]
|
||||
// CHECK: [0x00,0x00,0x74,0xdd,0x01,0xfe,0x00,0x00]
|
||||
|
||||
flat_atomic_dec_x2 v[0:1], v[1:2], v[2:3] glc
|
||||
// CHECK: [0x00,0x00,0x75,0xdd,0x01,0x02,0x00,0x00]
|
||||
|
||||
flat_atomic_dec_x2 v[1:2], v[2:3] slc
|
||||
// CHECK: [0x00,0x00,0x76,0xdd,0x01,0x02,0x00,0x00]
|
||||
|
||||
flat_atomic_fcmpswap_x2 v[1:2], v[2:5]
|
||||
// CHECK: [0x00,0x00,0x78,0xdd,0x01,0x02,0x00,0x00]
|
||||
|
||||
flat_atomic_fcmpswap_x2 v[254:255], v[2:5]
|
||||
// CHECK: [0x00,0x00,0x78,0xdd,0xfe,0x02,0x00,0x00]
|
||||
|
||||
flat_atomic_fcmpswap_x2 v[1:2], v[252:255]
|
||||
// CHECK: [0x00,0x00,0x78,0xdd,0x01,0xfc,0x00,0x00]
|
||||
|
||||
flat_atomic_fcmpswap_x2 v[0:1], v[1:2], v[2:5] glc
|
||||
// CHECK: [0x00,0x00,0x79,0xdd,0x01,0x02,0x00,0x00]
|
||||
|
||||
flat_atomic_fcmpswap_x2 v[1:2], v[2:5] slc
|
||||
// CHECK: [0x00,0x00,0x7a,0xdd,0x01,0x02,0x00,0x00]
|
||||
|
||||
flat_atomic_fmin_x2 v[1:2], v[2:3]
|
||||
// CHECK: [0x00,0x00,0x7c,0xdd,0x01,0x02,0x00,0x00]
|
||||
|
||||
flat_atomic_fmin_x2 v[254:255], v[2:3]
|
||||
// CHECK: [0x00,0x00,0x7c,0xdd,0xfe,0x02,0x00,0x00]
|
||||
|
||||
flat_atomic_fmin_x2 v[1:2], v[254:255]
|
||||
// CHECK: [0x00,0x00,0x7c,0xdd,0x01,0xfe,0x00,0x00]
|
||||
|
||||
flat_atomic_fmin_x2 v[0:1], v[1:2], v[2:3] glc
|
||||
// CHECK: [0x00,0x00,0x7d,0xdd,0x01,0x02,0x00,0x00]
|
||||
|
||||
flat_atomic_fmin_x2 v[1:2], v[2:3] slc
|
||||
// CHECK: [0x00,0x00,0x7e,0xdd,0x01,0x02,0x00,0x00]
|
||||
|
||||
flat_atomic_fmax_x2 v[1:2], v[2:3]
|
||||
// CHECK: [0x00,0x00,0x80,0xdd,0x01,0x02,0x00,0x00]
|
||||
|
||||
flat_atomic_fmax_x2 v[254:255], v[2:3]
|
||||
// CHECK: [0x00,0x00,0x80,0xdd,0xfe,0x02,0x00,0x00]
|
||||
|
||||
flat_atomic_fmax_x2 v[1:2], v[254:255]
|
||||
// CHECK: [0x00,0x00,0x80,0xdd,0x01,0xfe,0x00,0x00]
|
||||
|
||||
flat_atomic_fmax_x2 v[0:1], v[1:2], v[2:3] glc
|
||||
// CHECK: [0x00,0x00,0x81,0xdd,0x01,0x02,0x00,0x00]
|
||||
|
||||
flat_atomic_fmax_x2 v[1:2], v[2:3] slc
|
||||
// CHECK: [0x00,0x00,0x82,0xdd,0x01,0x02,0x00,0x00]
|
||||
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
|
|
@ -0,0 +1,751 @@
|
|||
// RUN: llvm-mc -arch=amdgcn -mcpu=bonaire -show-encoding %s | FileCheck %s
|
||||
|
||||
s_load_dword s5, s[2:3], s2
|
||||
// CHECK: [0x02,0x82,0x02,0xc0]
|
||||
|
||||
s_load_dword s103, s[2:3], s2
|
||||
// CHECK: [0x02,0x82,0x33,0xc0]
|
||||
|
||||
s_load_dword flat_scratch_lo, s[2:3], s2
|
||||
// CHECK: [0x02,0x02,0x34,0xc0]
|
||||
|
||||
s_load_dword flat_scratch_hi, s[2:3], s2
|
||||
// CHECK: [0x02,0x82,0x34,0xc0]
|
||||
|
||||
s_load_dword vcc_lo, s[2:3], s2
|
||||
// CHECK: [0x02,0x02,0x35,0xc0]
|
||||
|
||||
s_load_dword vcc_hi, s[2:3], s2
|
||||
// CHECK: [0x02,0x82,0x35,0xc0]
|
||||
|
||||
s_load_dword tba_lo, s[2:3], s2
|
||||
// CHECK: [0x02,0x02,0x36,0xc0]
|
||||
|
||||
s_load_dword tba_hi, s[2:3], s2
|
||||
// CHECK: [0x02,0x82,0x36,0xc0]
|
||||
|
||||
s_load_dword tma_lo, s[2:3], s2
|
||||
// CHECK: [0x02,0x02,0x37,0xc0]
|
||||
|
||||
s_load_dword tma_hi, s[2:3], s2
|
||||
// CHECK: [0x02,0x82,0x37,0xc0]
|
||||
|
||||
s_load_dword ttmp11, s[2:3], s2
|
||||
// CHECK: [0x02,0x82,0x3d,0xc0]
|
||||
|
||||
s_load_dword s5, s[4:5], s2
|
||||
// CHECK: [0x02,0x84,0x02,0xc0]
|
||||
|
||||
s_load_dword s5, s[102:103], s2
|
||||
// CHECK: [0x02,0xe6,0x02,0xc0]
|
||||
|
||||
s_load_dword s5, flat_scratch, s2
|
||||
// CHECK: [0x02,0xe8,0x02,0xc0]
|
||||
|
||||
s_load_dword s5, vcc, s2
|
||||
// CHECK: [0x02,0xea,0x02,0xc0]
|
||||
|
||||
s_load_dword s5, tba, s2
|
||||
// CHECK: [0x02,0xec,0x02,0xc0]
|
||||
|
||||
s_load_dword s5, tma, s2
|
||||
// CHECK: [0x02,0xee,0x02,0xc0]
|
||||
|
||||
s_load_dword s5, ttmp[10:11], s2
|
||||
// CHECK: [0x02,0xfa,0x02,0xc0]
|
||||
|
||||
s_load_dword s5, s[2:3], s103
|
||||
// CHECK: [0x67,0x82,0x02,0xc0]
|
||||
|
||||
s_load_dword s5, s[2:3], flat_scratch_lo
|
||||
// CHECK: [0x68,0x82,0x02,0xc0]
|
||||
|
||||
s_load_dword s5, s[2:3], flat_scratch_hi
|
||||
// CHECK: [0x69,0x82,0x02,0xc0]
|
||||
|
||||
s_load_dword s5, s[2:3], vcc_lo
|
||||
// CHECK: [0x6a,0x82,0x02,0xc0]
|
||||
|
||||
s_load_dword s5, s[2:3], vcc_hi
|
||||
// CHECK: [0x6b,0x82,0x02,0xc0]
|
||||
|
||||
s_load_dword s5, s[2:3], tba_lo
|
||||
// CHECK: [0x6c,0x82,0x02,0xc0]
|
||||
|
||||
s_load_dword s5, s[2:3], tba_hi
|
||||
// CHECK: [0x6d,0x82,0x02,0xc0]
|
||||
|
||||
s_load_dword s5, s[2:3], tma_lo
|
||||
// CHECK: [0x6e,0x82,0x02,0xc0]
|
||||
|
||||
s_load_dword s5, s[2:3], tma_hi
|
||||
// CHECK: [0x6f,0x82,0x02,0xc0]
|
||||
|
||||
s_load_dword s5, s[2:3], ttmp11
|
||||
// CHECK: [0x7b,0x82,0x02,0xc0]
|
||||
|
||||
s_load_dword s5, s[2:3], 0xaf123456
|
||||
// CHECK: [0xff,0x82,0x02,0xc0,0x56,0x34,0x12,0xaf]
|
||||
|
||||
s_load_dword s5, s[2:3], 0x3f717273
|
||||
// CHECK: [0xff,0x82,0x02,0xc0,0x73,0x72,0x71,0x3f]
|
||||
|
||||
s_load_dword s5, s[2:3], 0x7f
|
||||
// CHECK: [0x7f,0x83,0x02,0xc0]
|
||||
|
||||
s_load_dwordx2 s[10:11], s[2:3], s2
|
||||
// CHECK: [0x02,0x02,0x45,0xc0]
|
||||
|
||||
s_load_dwordx2 s[12:13], s[2:3], s2
|
||||
// CHECK: [0x02,0x02,0x46,0xc0]
|
||||
|
||||
s_load_dwordx2 s[102:103], s[2:3], s2
|
||||
// CHECK: [0x02,0x02,0x73,0xc0]
|
||||
|
||||
s_load_dwordx2 flat_scratch, s[2:3], s2
|
||||
// CHECK: [0x02,0x02,0x74,0xc0]
|
||||
|
||||
s_load_dwordx2 vcc, s[2:3], s2
|
||||
// CHECK: [0x02,0x02,0x75,0xc0]
|
||||
|
||||
s_load_dwordx2 tba, s[2:3], s2
|
||||
// CHECK: [0x02,0x02,0x76,0xc0]
|
||||
|
||||
s_load_dwordx2 tma, s[2:3], s2
|
||||
// CHECK: [0x02,0x02,0x77,0xc0]
|
||||
|
||||
s_load_dwordx2 ttmp[10:11], s[2:3], s2
|
||||
// CHECK: [0x02,0x02,0x7d,0xc0]
|
||||
|
||||
s_load_dwordx2 s[10:11], s[4:5], s2
|
||||
// CHECK: [0x02,0x04,0x45,0xc0]
|
||||
|
||||
s_load_dwordx2 s[10:11], s[102:103], s2
|
||||
// CHECK: [0x02,0x66,0x45,0xc0]
|
||||
|
||||
s_load_dwordx2 s[10:11], flat_scratch, s2
|
||||
// CHECK: [0x02,0x68,0x45,0xc0]
|
||||
|
||||
s_load_dwordx2 s[10:11], vcc, s2
|
||||
// CHECK: [0x02,0x6a,0x45,0xc0]
|
||||
|
||||
s_load_dwordx2 s[10:11], tba, s2
|
||||
// CHECK: [0x02,0x6c,0x45,0xc0]
|
||||
|
||||
s_load_dwordx2 s[10:11], tma, s2
|
||||
// CHECK: [0x02,0x6e,0x45,0xc0]
|
||||
|
||||
s_load_dwordx2 s[10:11], ttmp[10:11], s2
|
||||
// CHECK: [0x02,0x7a,0x45,0xc0]
|
||||
|
||||
s_load_dwordx2 s[10:11], s[2:3], s103
|
||||
// CHECK: [0x67,0x02,0x45,0xc0]
|
||||
|
||||
s_load_dwordx2 s[10:11], s[2:3], flat_scratch_lo
|
||||
// CHECK: [0x68,0x02,0x45,0xc0]
|
||||
|
||||
s_load_dwordx2 s[10:11], s[2:3], flat_scratch_hi
|
||||
// CHECK: [0x69,0x02,0x45,0xc0]
|
||||
|
||||
s_load_dwordx2 s[10:11], s[2:3], vcc_lo
|
||||
// CHECK: [0x6a,0x02,0x45,0xc0]
|
||||
|
||||
s_load_dwordx2 s[10:11], s[2:3], vcc_hi
|
||||
// CHECK: [0x6b,0x02,0x45,0xc0]
|
||||
|
||||
s_load_dwordx2 s[10:11], s[2:3], tba_lo
|
||||
// CHECK: [0x6c,0x02,0x45,0xc0]
|
||||
|
||||
s_load_dwordx2 s[10:11], s[2:3], tba_hi
|
||||
// CHECK: [0x6d,0x02,0x45,0xc0]
|
||||
|
||||
s_load_dwordx2 s[10:11], s[2:3], tma_lo
|
||||
// CHECK: [0x6e,0x02,0x45,0xc0]
|
||||
|
||||
s_load_dwordx2 s[10:11], s[2:3], tma_hi
|
||||
// CHECK: [0x6f,0x02,0x45,0xc0]
|
||||
|
||||
s_load_dwordx2 s[10:11], s[2:3], ttmp11
|
||||
// CHECK: [0x7b,0x02,0x45,0xc0]
|
||||
|
||||
s_load_dwordx2 s[10:11], s[2:3], 0xaf123456
|
||||
// CHECK: [0xff,0x02,0x45,0xc0,0x56,0x34,0x12,0xaf]
|
||||
|
||||
s_load_dwordx2 s[10:11], s[2:3], 0x3f717273
|
||||
// CHECK: [0xff,0x02,0x45,0xc0,0x73,0x72,0x71,0x3f]
|
||||
|
||||
s_load_dwordx2 s[10:11], s[2:3], 0x7f
|
||||
// CHECK: [0x7f,0x03,0x45,0xc0]
|
||||
|
||||
s_load_dwordx4 s[20:23], s[2:3], s2
|
||||
// CHECK: [0x02,0x02,0x8a,0xc0]
|
||||
|
||||
s_load_dwordx4 s[24:27], s[2:3], s2
|
||||
// CHECK: [0x02,0x02,0x8c,0xc0]
|
||||
|
||||
s_load_dwordx4 s[100:103], s[2:3], s2
|
||||
// CHECK: [0x02,0x02,0xb2,0xc0]
|
||||
|
||||
s_load_dwordx4 ttmp[8:11], s[2:3], s2
|
||||
// CHECK: [0x02,0x02,0xbc,0xc0]
|
||||
|
||||
s_load_dwordx4 s[20:23], s[4:5], s2
|
||||
// CHECK: [0x02,0x04,0x8a,0xc0]
|
||||
|
||||
s_load_dwordx4 s[20:23], s[102:103], s2
|
||||
// CHECK: [0x02,0x66,0x8a,0xc0]
|
||||
|
||||
s_load_dwordx4 s[20:23], flat_scratch, s2
|
||||
// CHECK: [0x02,0x68,0x8a,0xc0]
|
||||
|
||||
s_load_dwordx4 s[20:23], vcc, s2
|
||||
// CHECK: [0x02,0x6a,0x8a,0xc0]
|
||||
|
||||
s_load_dwordx4 s[20:23], tba, s2
|
||||
// CHECK: [0x02,0x6c,0x8a,0xc0]
|
||||
|
||||
s_load_dwordx4 s[20:23], tma, s2
|
||||
// CHECK: [0x02,0x6e,0x8a,0xc0]
|
||||
|
||||
s_load_dwordx4 s[20:23], ttmp[10:11], s2
|
||||
// CHECK: [0x02,0x7a,0x8a,0xc0]
|
||||
|
||||
s_load_dwordx4 s[20:23], s[2:3], s103
|
||||
// CHECK: [0x67,0x02,0x8a,0xc0]
|
||||
|
||||
s_load_dwordx4 s[20:23], s[2:3], flat_scratch_lo
|
||||
// CHECK: [0x68,0x02,0x8a,0xc0]
|
||||
|
||||
s_load_dwordx4 s[20:23], s[2:3], flat_scratch_hi
|
||||
// CHECK: [0x69,0x02,0x8a,0xc0]
|
||||
|
||||
s_load_dwordx4 s[20:23], s[2:3], vcc_lo
|
||||
// CHECK: [0x6a,0x02,0x8a,0xc0]
|
||||
|
||||
s_load_dwordx4 s[20:23], s[2:3], vcc_hi
|
||||
// CHECK: [0x6b,0x02,0x8a,0xc0]
|
||||
|
||||
s_load_dwordx4 s[20:23], s[2:3], tba_lo
|
||||
// CHECK: [0x6c,0x02,0x8a,0xc0]
|
||||
|
||||
s_load_dwordx4 s[20:23], s[2:3], tba_hi
|
||||
// CHECK: [0x6d,0x02,0x8a,0xc0]
|
||||
|
||||
s_load_dwordx4 s[20:23], s[2:3], tma_lo
|
||||
// CHECK: [0x6e,0x02,0x8a,0xc0]
|
||||
|
||||
s_load_dwordx4 s[20:23], s[2:3], tma_hi
|
||||
// CHECK: [0x6f,0x02,0x8a,0xc0]
|
||||
|
||||
s_load_dwordx4 s[20:23], s[2:3], ttmp11
|
||||
// CHECK: [0x7b,0x02,0x8a,0xc0]
|
||||
|
||||
s_load_dwordx4 s[20:23], s[2:3], 0xaf123456
|
||||
// CHECK: [0xff,0x02,0x8a,0xc0,0x56,0x34,0x12,0xaf]
|
||||
|
||||
s_load_dwordx4 s[20:23], s[2:3], 0x3f717273
|
||||
// CHECK: [0xff,0x02,0x8a,0xc0,0x73,0x72,0x71,0x3f]
|
||||
|
||||
s_load_dwordx4 s[20:23], s[2:3], 0x7f
|
||||
// CHECK: [0x7f,0x03,0x8a,0xc0]
|
||||
|
||||
s_load_dwordx8 s[20:27], s[2:3], s2
|
||||
// CHECK: [0x02,0x02,0xca,0xc0]
|
||||
|
||||
s_load_dwordx8 s[24:31], s[2:3], s2
|
||||
// CHECK: [0x02,0x02,0xcc,0xc0]
|
||||
|
||||
s_load_dwordx8 s[96:103], s[2:3], s2
|
||||
// CHECK: [0x02,0x02,0xf0,0xc0]
|
||||
|
||||
s_load_dwordx8 ttmp[4:11], s[2:3], s2
|
||||
// CHECK: [0x02,0x02,0xfa,0xc0]
|
||||
|
||||
s_load_dwordx8 s[20:27], s[4:5], s2
|
||||
// CHECK: [0x02,0x04,0xca,0xc0]
|
||||
|
||||
s_load_dwordx8 s[20:27], s[102:103], s2
|
||||
// CHECK: [0x02,0x66,0xca,0xc0]
|
||||
|
||||
s_load_dwordx8 s[20:27], flat_scratch, s2
|
||||
// CHECK: [0x02,0x68,0xca,0xc0]
|
||||
|
||||
s_load_dwordx8 s[20:27], vcc, s2
|
||||
// CHECK: [0x02,0x6a,0xca,0xc0]
|
||||
|
||||
s_load_dwordx8 s[20:27], tba, s2
|
||||
// CHECK: [0x02,0x6c,0xca,0xc0]
|
||||
|
||||
s_load_dwordx8 s[20:27], tma, s2
|
||||
// CHECK: [0x02,0x6e,0xca,0xc0]
|
||||
|
||||
s_load_dwordx8 s[20:27], ttmp[10:11], s2
|
||||
// CHECK: [0x02,0x7a,0xca,0xc0]
|
||||
|
||||
s_load_dwordx8 s[20:27], s[2:3], s103
|
||||
// CHECK: [0x67,0x02,0xca,0xc0]
|
||||
|
||||
s_load_dwordx8 s[20:27], s[2:3], flat_scratch_lo
|
||||
// CHECK: [0x68,0x02,0xca,0xc0]
|
||||
|
||||
s_load_dwordx8 s[20:27], s[2:3], flat_scratch_hi
|
||||
// CHECK: [0x69,0x02,0xca,0xc0]
|
||||
|
||||
s_load_dwordx8 s[20:27], s[2:3], vcc_lo
|
||||
// CHECK: [0x6a,0x02,0xca,0xc0]
|
||||
|
||||
s_load_dwordx8 s[20:27], s[2:3], vcc_hi
|
||||
// CHECK: [0x6b,0x02,0xca,0xc0]
|
||||
|
||||
s_load_dwordx8 s[20:27], s[2:3], tba_lo
|
||||
// CHECK: [0x6c,0x02,0xca,0xc0]
|
||||
|
||||
s_load_dwordx8 s[20:27], s[2:3], tba_hi
|
||||
// CHECK: [0x6d,0x02,0xca,0xc0]
|
||||
|
||||
s_load_dwordx8 s[20:27], s[2:3], tma_lo
|
||||
// CHECK: [0x6e,0x02,0xca,0xc0]
|
||||
|
||||
s_load_dwordx8 s[20:27], s[2:3], tma_hi
|
||||
// CHECK: [0x6f,0x02,0xca,0xc0]
|
||||
|
||||
s_load_dwordx8 s[20:27], s[2:3], ttmp11
|
||||
// CHECK: [0x7b,0x02,0xca,0xc0]
|
||||
|
||||
s_load_dwordx8 s[20:27], s[2:3], 0xaf123456
|
||||
// CHECK: [0xff,0x02,0xca,0xc0,0x56,0x34,0x12,0xaf]
|
||||
|
||||
s_load_dwordx8 s[20:27], s[2:3], 0x3f717273
|
||||
// CHECK: [0xff,0x02,0xca,0xc0,0x73,0x72,0x71,0x3f]
|
||||
|
||||
s_load_dwordx8 s[20:27], s[2:3], 0x7f
|
||||
// CHECK: [0x7f,0x03,0xca,0xc0]
|
||||
|
||||
s_load_dwordx16 s[20:35], s[2:3], s2
|
||||
// CHECK: [0x02,0x02,0x0a,0xc1]
|
||||
|
||||
s_load_dwordx16 s[24:39], s[2:3], s2
|
||||
// CHECK: [0x02,0x02,0x0c,0xc1]
|
||||
|
||||
s_load_dwordx16 s[88:103], s[2:3], s2
|
||||
// CHECK: [0x02,0x02,0x2c,0xc1]
|
||||
|
||||
s_load_dwordx16 s[20:35], s[4:5], s2
|
||||
// CHECK: [0x02,0x04,0x0a,0xc1]
|
||||
|
||||
s_load_dwordx16 s[20:35], s[102:103], s2
|
||||
// CHECK: [0x02,0x66,0x0a,0xc1]
|
||||
|
||||
s_load_dwordx16 s[20:35], flat_scratch, s2
|
||||
// CHECK: [0x02,0x68,0x0a,0xc1]
|
||||
|
||||
s_load_dwordx16 s[20:35], vcc, s2
|
||||
// CHECK: [0x02,0x6a,0x0a,0xc1]
|
||||
|
||||
s_load_dwordx16 s[20:35], tba, s2
|
||||
// CHECK: [0x02,0x6c,0x0a,0xc1]
|
||||
|
||||
s_load_dwordx16 s[20:35], tma, s2
|
||||
// CHECK: [0x02,0x6e,0x0a,0xc1]
|
||||
|
||||
s_load_dwordx16 s[20:35], ttmp[10:11], s2
|
||||
// CHECK: [0x02,0x7a,0x0a,0xc1]
|
||||
|
||||
s_load_dwordx16 s[20:35], s[2:3], s103
|
||||
// CHECK: [0x67,0x02,0x0a,0xc1]
|
||||
|
||||
s_load_dwordx16 s[20:35], s[2:3], flat_scratch_lo
|
||||
// CHECK: [0x68,0x02,0x0a,0xc1]
|
||||
|
||||
s_load_dwordx16 s[20:35], s[2:3], flat_scratch_hi
|
||||
// CHECK: [0x69,0x02,0x0a,0xc1]
|
||||
|
||||
s_load_dwordx16 s[20:35], s[2:3], vcc_lo
|
||||
// CHECK: [0x6a,0x02,0x0a,0xc1]
|
||||
|
||||
s_load_dwordx16 s[20:35], s[2:3], vcc_hi
|
||||
// CHECK: [0x6b,0x02,0x0a,0xc1]
|
||||
|
||||
s_load_dwordx16 s[20:35], s[2:3], tba_lo
|
||||
// CHECK: [0x6c,0x02,0x0a,0xc1]
|
||||
|
||||
s_load_dwordx16 s[20:35], s[2:3], tba_hi
|
||||
// CHECK: [0x6d,0x02,0x0a,0xc1]
|
||||
|
||||
s_load_dwordx16 s[20:35], s[2:3], tma_lo
|
||||
// CHECK: [0x6e,0x02,0x0a,0xc1]
|
||||
|
||||
s_load_dwordx16 s[20:35], s[2:3], tma_hi
|
||||
// CHECK: [0x6f,0x02,0x0a,0xc1]
|
||||
|
||||
s_load_dwordx16 s[20:35], s[2:3], ttmp11
|
||||
// CHECK: [0x7b,0x02,0x0a,0xc1]
|
||||
|
||||
s_load_dwordx16 s[20:35], s[2:3], 0xaf123456
|
||||
// CHECK: [0xff,0x02,0x0a,0xc1,0x56,0x34,0x12,0xaf]
|
||||
|
||||
s_load_dwordx16 s[20:35], s[2:3], 0x3f717273
|
||||
// CHECK: [0xff,0x02,0x0a,0xc1,0x73,0x72,0x71,0x3f]
|
||||
|
||||
s_load_dwordx16 s[20:35], s[2:3], 0x7f
|
||||
// CHECK: [0x7f,0x03,0x0a,0xc1]
|
||||
|
||||
s_buffer_load_dword s5, s[4:7], s2
|
||||
// CHECK: [0x02,0x84,0x02,0xc2]
|
||||
|
||||
s_buffer_load_dword s103, s[4:7], s2
|
||||
// CHECK: [0x02,0x84,0x33,0xc2]
|
||||
|
||||
s_buffer_load_dword flat_scratch_lo, s[4:7], s2
|
||||
// CHECK: [0x02,0x04,0x34,0xc2]
|
||||
|
||||
s_buffer_load_dword flat_scratch_hi, s[4:7], s2
|
||||
// CHECK: [0x02,0x84,0x34,0xc2]
|
||||
|
||||
s_buffer_load_dword vcc_lo, s[4:7], s2
|
||||
// CHECK: [0x02,0x04,0x35,0xc2]
|
||||
|
||||
s_buffer_load_dword vcc_hi, s[4:7], s2
|
||||
// CHECK: [0x02,0x84,0x35,0xc2]
|
||||
|
||||
s_buffer_load_dword tba_lo, s[4:7], s2
|
||||
// CHECK: [0x02,0x04,0x36,0xc2]
|
||||
|
||||
s_buffer_load_dword tba_hi, s[4:7], s2
|
||||
// CHECK: [0x02,0x84,0x36,0xc2]
|
||||
|
||||
s_buffer_load_dword tma_lo, s[4:7], s2
|
||||
// CHECK: [0x02,0x04,0x37,0xc2]
|
||||
|
||||
s_buffer_load_dword tma_hi, s[4:7], s2
|
||||
// CHECK: [0x02,0x84,0x37,0xc2]
|
||||
|
||||
s_buffer_load_dword ttmp11, s[4:7], s2
|
||||
// CHECK: [0x02,0x84,0x3d,0xc2]
|
||||
|
||||
s_buffer_load_dword s5, s[8:11], s2
|
||||
// CHECK: [0x02,0x88,0x02,0xc2]
|
||||
|
||||
s_buffer_load_dword s5, s[100:103], s2
|
||||
// CHECK: [0x02,0xe4,0x02,0xc2]
|
||||
|
||||
s_buffer_load_dword s5, ttmp[8:11], s2
|
||||
// CHECK: [0x02,0xf8,0x02,0xc2]
|
||||
|
||||
s_buffer_load_dword s5, s[4:7], s103
|
||||
// CHECK: [0x67,0x84,0x02,0xc2]
|
||||
|
||||
s_buffer_load_dword s5, s[4:7], flat_scratch_lo
|
||||
// CHECK: [0x68,0x84,0x02,0xc2]
|
||||
|
||||
s_buffer_load_dword s5, s[4:7], flat_scratch_hi
|
||||
// CHECK: [0x69,0x84,0x02,0xc2]
|
||||
|
||||
s_buffer_load_dword s5, s[4:7], vcc_lo
|
||||
// CHECK: [0x6a,0x84,0x02,0xc2]
|
||||
|
||||
s_buffer_load_dword s5, s[4:7], vcc_hi
|
||||
// CHECK: [0x6b,0x84,0x02,0xc2]
|
||||
|
||||
s_buffer_load_dword s5, s[4:7], tba_lo
|
||||
// CHECK: [0x6c,0x84,0x02,0xc2]
|
||||
|
||||
s_buffer_load_dword s5, s[4:7], tba_hi
|
||||
// CHECK: [0x6d,0x84,0x02,0xc2]
|
||||
|
||||
s_buffer_load_dword s5, s[4:7], tma_lo
|
||||
// CHECK: [0x6e,0x84,0x02,0xc2]
|
||||
|
||||
s_buffer_load_dword s5, s[4:7], tma_hi
|
||||
// CHECK: [0x6f,0x84,0x02,0xc2]
|
||||
|
||||
s_buffer_load_dword s5, s[4:7], ttmp11
|
||||
// CHECK: [0x7b,0x84,0x02,0xc2]
|
||||
|
||||
s_buffer_load_dword s5, s[4:7], 0xaf123456
|
||||
// CHECK: [0xff,0x84,0x02,0xc2,0x56,0x34,0x12,0xaf]
|
||||
|
||||
s_buffer_load_dword s5, s[4:7], 0x3f717273
|
||||
// CHECK: [0xff,0x84,0x02,0xc2,0x73,0x72,0x71,0x3f]
|
||||
|
||||
s_buffer_load_dword s5, s[4:7], 0x7f
|
||||
// CHECK: [0x7f,0x85,0x02,0xc2]
|
||||
|
||||
s_buffer_load_dwordx2 s[10:11], s[4:7], s2
|
||||
// CHECK: [0x02,0x04,0x45,0xc2]
|
||||
|
||||
s_buffer_load_dwordx2 s[12:13], s[4:7], s2
|
||||
// CHECK: [0x02,0x04,0x46,0xc2]
|
||||
|
||||
s_buffer_load_dwordx2 s[102:103], s[4:7], s2
|
||||
// CHECK: [0x02,0x04,0x73,0xc2]
|
||||
|
||||
s_buffer_load_dwordx2 flat_scratch, s[4:7], s2
|
||||
// CHECK: [0x02,0x04,0x74,0xc2]
|
||||
|
||||
s_buffer_load_dwordx2 vcc, s[4:7], s2
|
||||
// CHECK: [0x02,0x04,0x75,0xc2]
|
||||
|
||||
s_buffer_load_dwordx2 tba, s[4:7], s2
|
||||
// CHECK: [0x02,0x04,0x76,0xc2]
|
||||
|
||||
s_buffer_load_dwordx2 tma, s[4:7], s2
|
||||
// CHECK: [0x02,0x04,0x77,0xc2]
|
||||
|
||||
s_buffer_load_dwordx2 ttmp[10:11], s[4:7], s2
|
||||
// CHECK: [0x02,0x04,0x7d,0xc2]
|
||||
|
||||
s_buffer_load_dwordx2 s[10:11], s[8:11], s2
|
||||
// CHECK: [0x02,0x08,0x45,0xc2]
|
||||
|
||||
s_buffer_load_dwordx2 s[10:11], s[100:103], s2
|
||||
// CHECK: [0x02,0x64,0x45,0xc2]
|
||||
|
||||
s_buffer_load_dwordx2 s[10:11], ttmp[8:11], s2
|
||||
// CHECK: [0x02,0x78,0x45,0xc2]
|
||||
|
||||
s_buffer_load_dwordx2 s[10:11], s[4:7], s103
|
||||
// CHECK: [0x67,0x04,0x45,0xc2]
|
||||
|
||||
s_buffer_load_dwordx2 s[10:11], s[4:7], flat_scratch_lo
|
||||
// CHECK: [0x68,0x04,0x45,0xc2]
|
||||
|
||||
s_buffer_load_dwordx2 s[10:11], s[4:7], flat_scratch_hi
|
||||
// CHECK: [0x69,0x04,0x45,0xc2]
|
||||
|
||||
s_buffer_load_dwordx2 s[10:11], s[4:7], vcc_lo
|
||||
// CHECK: [0x6a,0x04,0x45,0xc2]
|
||||
|
||||
s_buffer_load_dwordx2 s[10:11], s[4:7], vcc_hi
|
||||
// CHECK: [0x6b,0x04,0x45,0xc2]
|
||||
|
||||
s_buffer_load_dwordx2 s[10:11], s[4:7], tba_lo
|
||||
// CHECK: [0x6c,0x04,0x45,0xc2]
|
||||
|
||||
s_buffer_load_dwordx2 s[10:11], s[4:7], tba_hi
|
||||
// CHECK: [0x6d,0x04,0x45,0xc2]
|
||||
|
||||
s_buffer_load_dwordx2 s[10:11], s[4:7], tma_lo
|
||||
// CHECK: [0x6e,0x04,0x45,0xc2]
|
||||
|
||||
s_buffer_load_dwordx2 s[10:11], s[4:7], tma_hi
|
||||
// CHECK: [0x6f,0x04,0x45,0xc2]
|
||||
|
||||
s_buffer_load_dwordx2 s[10:11], s[4:7], ttmp11
|
||||
// CHECK: [0x7b,0x04,0x45,0xc2]
|
||||
|
||||
s_buffer_load_dwordx2 s[10:11], s[4:7], 0xaf123456
|
||||
// CHECK: [0xff,0x04,0x45,0xc2,0x56,0x34,0x12,0xaf]
|
||||
|
||||
s_buffer_load_dwordx2 s[10:11], s[4:7], 0x3f717273
|
||||
// CHECK: [0xff,0x04,0x45,0xc2,0x73,0x72,0x71,0x3f]
|
||||
|
||||
s_buffer_load_dwordx2 s[10:11], s[4:7], 0x7f
|
||||
// CHECK: [0x7f,0x05,0x45,0xc2]
|
||||
|
||||
s_buffer_load_dwordx4 s[20:23], s[4:7], s2
|
||||
// CHECK: [0x02,0x04,0x8a,0xc2]
|
||||
|
||||
s_buffer_load_dwordx4 s[24:27], s[4:7], s2
|
||||
// CHECK: [0x02,0x04,0x8c,0xc2]
|
||||
|
||||
s_buffer_load_dwordx4 s[100:103], s[4:7], s2
|
||||
// CHECK: [0x02,0x04,0xb2,0xc2]
|
||||
|
||||
s_buffer_load_dwordx4 ttmp[8:11], s[4:7], s2
|
||||
// CHECK: [0x02,0x04,0xbc,0xc2]
|
||||
|
||||
s_buffer_load_dwordx4 s[20:23], s[8:11], s2
|
||||
// CHECK: [0x02,0x08,0x8a,0xc2]
|
||||
|
||||
s_buffer_load_dwordx4 s[20:23], s[100:103], s2
|
||||
// CHECK: [0x02,0x64,0x8a,0xc2]
|
||||
|
||||
s_buffer_load_dwordx4 s[20:23], ttmp[8:11], s2
|
||||
// CHECK: [0x02,0x78,0x8a,0xc2]
|
||||
|
||||
s_buffer_load_dwordx4 s[20:23], s[4:7], s103
|
||||
// CHECK: [0x67,0x04,0x8a,0xc2]
|
||||
|
||||
s_buffer_load_dwordx4 s[20:23], s[4:7], flat_scratch_lo
|
||||
// CHECK: [0x68,0x04,0x8a,0xc2]
|
||||
|
||||
s_buffer_load_dwordx4 s[20:23], s[4:7], flat_scratch_hi
|
||||
// CHECK: [0x69,0x04,0x8a,0xc2]
|
||||
|
||||
s_buffer_load_dwordx4 s[20:23], s[4:7], vcc_lo
|
||||
// CHECK: [0x6a,0x04,0x8a,0xc2]
|
||||
|
||||
s_buffer_load_dwordx4 s[20:23], s[4:7], vcc_hi
|
||||
// CHECK: [0x6b,0x04,0x8a,0xc2]
|
||||
|
||||
s_buffer_load_dwordx4 s[20:23], s[4:7], tba_lo
|
||||
// CHECK: [0x6c,0x04,0x8a,0xc2]
|
||||
|
||||
s_buffer_load_dwordx4 s[20:23], s[4:7], tba_hi
|
||||
// CHECK: [0x6d,0x04,0x8a,0xc2]
|
||||
|
||||
s_buffer_load_dwordx4 s[20:23], s[4:7], tma_lo
|
||||
// CHECK: [0x6e,0x04,0x8a,0xc2]
|
||||
|
||||
s_buffer_load_dwordx4 s[20:23], s[4:7], tma_hi
|
||||
// CHECK: [0x6f,0x04,0x8a,0xc2]
|
||||
|
||||
s_buffer_load_dwordx4 s[20:23], s[4:7], ttmp11
|
||||
// CHECK: [0x7b,0x04,0x8a,0xc2]
|
||||
|
||||
s_buffer_load_dwordx4 s[20:23], s[4:7], 0xaf123456
|
||||
// CHECK: [0xff,0x04,0x8a,0xc2,0x56,0x34,0x12,0xaf]
|
||||
|
||||
s_buffer_load_dwordx4 s[20:23], s[4:7], 0x3f717273
|
||||
// CHECK: [0xff,0x04,0x8a,0xc2,0x73,0x72,0x71,0x3f]
|
||||
|
||||
s_buffer_load_dwordx4 s[20:23], s[4:7], 0x7f
|
||||
// CHECK: [0x7f,0x05,0x8a,0xc2]
|
||||
|
||||
s_buffer_load_dwordx8 s[20:27], s[4:7], s2
|
||||
// CHECK: [0x02,0x04,0xca,0xc2]
|
||||
|
||||
s_buffer_load_dwordx8 s[24:31], s[4:7], s2
|
||||
// CHECK: [0x02,0x04,0xcc,0xc2]
|
||||
|
||||
s_buffer_load_dwordx8 s[96:103], s[4:7], s2
|
||||
// CHECK: [0x02,0x04,0xf0,0xc2]
|
||||
|
||||
s_buffer_load_dwordx8 ttmp[4:11], s[4:7], s2
|
||||
// CHECK: [0x02,0x04,0xfa,0xc2]
|
||||
|
||||
s_buffer_load_dwordx8 s[20:27], s[8:11], s2
|
||||
// CHECK: [0x02,0x08,0xca,0xc2]
|
||||
|
||||
s_buffer_load_dwordx8 s[20:27], s[100:103], s2
|
||||
// CHECK: [0x02,0x64,0xca,0xc2]
|
||||
|
||||
s_buffer_load_dwordx8 s[20:27], ttmp[8:11], s2
|
||||
// CHECK: [0x02,0x78,0xca,0xc2]
|
||||
|
||||
s_buffer_load_dwordx8 s[20:27], s[4:7], s103
|
||||
// CHECK: [0x67,0x04,0xca,0xc2]
|
||||
|
||||
s_buffer_load_dwordx8 s[20:27], s[4:7], flat_scratch_lo
|
||||
// CHECK: [0x68,0x04,0xca,0xc2]
|
||||
|
||||
s_buffer_load_dwordx8 s[20:27], s[4:7], flat_scratch_hi
|
||||
// CHECK: [0x69,0x04,0xca,0xc2]
|
||||
|
||||
s_buffer_load_dwordx8 s[20:27], s[4:7], vcc_lo
|
||||
// CHECK: [0x6a,0x04,0xca,0xc2]
|
||||
|
||||
s_buffer_load_dwordx8 s[20:27], s[4:7], vcc_hi
|
||||
// CHECK: [0x6b,0x04,0xca,0xc2]
|
||||
|
||||
s_buffer_load_dwordx8 s[20:27], s[4:7], tba_lo
|
||||
// CHECK: [0x6c,0x04,0xca,0xc2]
|
||||
|
||||
s_buffer_load_dwordx8 s[20:27], s[4:7], tba_hi
|
||||
// CHECK: [0x6d,0x04,0xca,0xc2]
|
||||
|
||||
s_buffer_load_dwordx8 s[20:27], s[4:7], tma_lo
|
||||
// CHECK: [0x6e,0x04,0xca,0xc2]
|
||||
|
||||
s_buffer_load_dwordx8 s[20:27], s[4:7], tma_hi
|
||||
// CHECK: [0x6f,0x04,0xca,0xc2]
|
||||
|
||||
s_buffer_load_dwordx8 s[20:27], s[4:7], ttmp11
|
||||
// CHECK: [0x7b,0x04,0xca,0xc2]
|
||||
|
||||
s_buffer_load_dwordx8 s[20:27], s[4:7], 0xaf123456
|
||||
// CHECK: [0xff,0x04,0xca,0xc2,0x56,0x34,0x12,0xaf]
|
||||
|
||||
s_buffer_load_dwordx8 s[20:27], s[4:7], 0x3f717273
|
||||
// CHECK: [0xff,0x04,0xca,0xc2,0x73,0x72,0x71,0x3f]
|
||||
|
||||
s_buffer_load_dwordx8 s[20:27], s[4:7], 0x7f
|
||||
// CHECK: [0x7f,0x05,0xca,0xc2]
|
||||
|
||||
s_buffer_load_dwordx16 s[20:35], s[4:7], s2
|
||||
// CHECK: [0x02,0x04,0x0a,0xc3]
|
||||
|
||||
s_buffer_load_dwordx16 s[24:39], s[4:7], s2
|
||||
// CHECK: [0x02,0x04,0x0c,0xc3]
|
||||
|
||||
s_buffer_load_dwordx16 s[88:103], s[4:7], s2
|
||||
// CHECK: [0x02,0x04,0x2c,0xc3]
|
||||
|
||||
s_buffer_load_dwordx16 s[20:35], s[8:11], s2
|
||||
// CHECK: [0x02,0x08,0x0a,0xc3]
|
||||
|
||||
s_buffer_load_dwordx16 s[20:35], s[100:103], s2
|
||||
// CHECK: [0x02,0x64,0x0a,0xc3]
|
||||
|
||||
s_buffer_load_dwordx16 s[20:35], ttmp[8:11], s2
|
||||
// CHECK: [0x02,0x78,0x0a,0xc3]
|
||||
|
||||
s_buffer_load_dwordx16 s[20:35], s[4:7], s103
|
||||
// CHECK: [0x67,0x04,0x0a,0xc3]
|
||||
|
||||
s_buffer_load_dwordx16 s[20:35], s[4:7], flat_scratch_lo
|
||||
// CHECK: [0x68,0x04,0x0a,0xc3]
|
||||
|
||||
s_buffer_load_dwordx16 s[20:35], s[4:7], flat_scratch_hi
|
||||
// CHECK: [0x69,0x04,0x0a,0xc3]
|
||||
|
||||
s_buffer_load_dwordx16 s[20:35], s[4:7], vcc_lo
|
||||
// CHECK: [0x6a,0x04,0x0a,0xc3]
|
||||
|
||||
s_buffer_load_dwordx16 s[20:35], s[4:7], vcc_hi
|
||||
// CHECK: [0x6b,0x04,0x0a,0xc3]
|
||||
|
||||
s_buffer_load_dwordx16 s[20:35], s[4:7], tba_lo
|
||||
// CHECK: [0x6c,0x04,0x0a,0xc3]
|
||||
|
||||
s_buffer_load_dwordx16 s[20:35], s[4:7], tba_hi
|
||||
// CHECK: [0x6d,0x04,0x0a,0xc3]
|
||||
|
||||
s_buffer_load_dwordx16 s[20:35], s[4:7], tma_lo
|
||||
// CHECK: [0x6e,0x04,0x0a,0xc3]
|
||||
|
||||
s_buffer_load_dwordx16 s[20:35], s[4:7], tma_hi
|
||||
// CHECK: [0x6f,0x04,0x0a,0xc3]
|
||||
|
||||
s_buffer_load_dwordx16 s[20:35], s[4:7], ttmp11
|
||||
// CHECK: [0x7b,0x04,0x0a,0xc3]
|
||||
|
||||
s_buffer_load_dwordx16 s[20:35], s[4:7], 0xaf123456
|
||||
// CHECK: [0xff,0x04,0x0a,0xc3,0x56,0x34,0x12,0xaf]
|
||||
|
||||
s_buffer_load_dwordx16 s[20:35], s[4:7], 0x3f717273
|
||||
// CHECK: [0xff,0x04,0x0a,0xc3,0x73,0x72,0x71,0x3f]
|
||||
|
||||
s_buffer_load_dwordx16 s[20:35], s[4:7], 0x7f
|
||||
// CHECK: [0x7f,0x05,0x0a,0xc3]
|
||||
|
||||
s_dcache_inv_vol
|
||||
// CHECK: [0x00,0x00,0x40,0xc7]
|
||||
|
||||
s_memtime s[10:11]
|
||||
// CHECK: [0x00,0x00,0x85,0xc7]
|
||||
|
||||
s_memtime s[12:13]
|
||||
// CHECK: [0x00,0x00,0x86,0xc7]
|
||||
|
||||
s_memtime s[102:103]
|
||||
// CHECK: [0x00,0x00,0xb3,0xc7]
|
||||
|
||||
s_memtime flat_scratch
|
||||
// CHECK: [0x00,0x00,0xb4,0xc7]
|
||||
|
||||
s_memtime vcc
|
||||
// CHECK: [0x00,0x00,0xb5,0xc7]
|
||||
|
||||
s_memtime tba
|
||||
// CHECK: [0x00,0x00,0xb6,0xc7]
|
||||
|
||||
s_memtime tma
|
||||
// CHECK: [0x00,0x00,0xb7,0xc7]
|
||||
|
||||
s_memtime ttmp[10:11]
|
||||
// CHECK: [0x00,0x00,0xbd,0xc7]
|
||||
|
||||
s_dcache_inv
|
||||
// CHECK: [0x00,0x00,0xc0,0xc7]
|
||||
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
|
|
@ -0,0 +1,850 @@
|
|||
// RUN: llvm-mc -arch=amdgcn -mcpu=bonaire -show-encoding %s | FileCheck %s
|
||||
|
||||
s_movk_i32 s5, 0x3141
|
||||
// CHECK: [0x41,0x31,0x05,0xb0]
|
||||
|
||||
s_movk_i32 s103, 0x3141
|
||||
// CHECK: [0x41,0x31,0x67,0xb0]
|
||||
|
||||
s_movk_i32 flat_scratch_lo, 0x3141
|
||||
// CHECK: [0x41,0x31,0x68,0xb0]
|
||||
|
||||
s_movk_i32 flat_scratch_hi, 0x3141
|
||||
// CHECK: [0x41,0x31,0x69,0xb0]
|
||||
|
||||
s_movk_i32 vcc_lo, 0x3141
|
||||
// CHECK: [0x41,0x31,0x6a,0xb0]
|
||||
|
||||
s_movk_i32 vcc_hi, 0x3141
|
||||
// CHECK: [0x41,0x31,0x6b,0xb0]
|
||||
|
||||
s_movk_i32 tba_lo, 0x3141
|
||||
// CHECK: [0x41,0x31,0x6c,0xb0]
|
||||
|
||||
s_movk_i32 tba_hi, 0x3141
|
||||
// CHECK: [0x41,0x31,0x6d,0xb0]
|
||||
|
||||
s_movk_i32 tma_lo, 0x3141
|
||||
// CHECK: [0x41,0x31,0x6e,0xb0]
|
||||
|
||||
s_movk_i32 tma_hi, 0x3141
|
||||
// CHECK: [0x41,0x31,0x6f,0xb0]
|
||||
|
||||
s_movk_i32 ttmp11, 0x3141
|
||||
// CHECK: [0x41,0x31,0x7b,0xb0]
|
||||
|
||||
s_movk_i32 m0, 0x3141
|
||||
// CHECK: [0x41,0x31,0x7c,0xb0]
|
||||
|
||||
s_movk_i32 exec_lo, 0x3141
|
||||
// CHECK: [0x41,0x31,0x7e,0xb0]
|
||||
|
||||
s_movk_i32 exec_hi, 0x3141
|
||||
// CHECK: [0x41,0x31,0x7f,0xb0]
|
||||
|
||||
s_movk_i32 s5, 0xc1d1
|
||||
// CHECK: [0xd1,0xc1,0x05,0xb0]
|
||||
|
||||
s_cmovk_i32 s5, 0x3141
|
||||
// CHECK: [0x41,0x31,0x05,0xb1]
|
||||
|
||||
s_cmovk_i32 s103, 0x3141
|
||||
// CHECK: [0x41,0x31,0x67,0xb1]
|
||||
|
||||
s_cmovk_i32 flat_scratch_lo, 0x3141
|
||||
// CHECK: [0x41,0x31,0x68,0xb1]
|
||||
|
||||
s_cmovk_i32 flat_scratch_hi, 0x3141
|
||||
// CHECK: [0x41,0x31,0x69,0xb1]
|
||||
|
||||
s_cmovk_i32 vcc_lo, 0x3141
|
||||
// CHECK: [0x41,0x31,0x6a,0xb1]
|
||||
|
||||
s_cmovk_i32 vcc_hi, 0x3141
|
||||
// CHECK: [0x41,0x31,0x6b,0xb1]
|
||||
|
||||
s_cmovk_i32 tba_lo, 0x3141
|
||||
// CHECK: [0x41,0x31,0x6c,0xb1]
|
||||
|
||||
s_cmovk_i32 tba_hi, 0x3141
|
||||
// CHECK: [0x41,0x31,0x6d,0xb1]
|
||||
|
||||
s_cmovk_i32 tma_lo, 0x3141
|
||||
// CHECK: [0x41,0x31,0x6e,0xb1]
|
||||
|
||||
s_cmovk_i32 tma_hi, 0x3141
|
||||
// CHECK: [0x41,0x31,0x6f,0xb1]
|
||||
|
||||
s_cmovk_i32 ttmp11, 0x3141
|
||||
// CHECK: [0x41,0x31,0x7b,0xb1]
|
||||
|
||||
s_cmovk_i32 m0, 0x3141
|
||||
// CHECK: [0x41,0x31,0x7c,0xb1]
|
||||
|
||||
s_cmovk_i32 exec_lo, 0x3141
|
||||
// CHECK: [0x41,0x31,0x7e,0xb1]
|
||||
|
||||
s_cmovk_i32 exec_hi, 0x3141
|
||||
// CHECK: [0x41,0x31,0x7f,0xb1]
|
||||
|
||||
s_cmovk_i32 s5, 0xc1d1
|
||||
// CHECK: [0xd1,0xc1,0x05,0xb1]
|
||||
|
||||
s_cmpk_eq_i32 s1, 0x3141
|
||||
// CHECK: [0x41,0x31,0x81,0xb1]
|
||||
|
||||
s_cmpk_eq_i32 s103, 0x3141
|
||||
// CHECK: [0x41,0x31,0xe7,0xb1]
|
||||
|
||||
s_cmpk_eq_i32 flat_scratch_lo, 0x3141
|
||||
// CHECK: [0x41,0x31,0xe8,0xb1]
|
||||
|
||||
s_cmpk_eq_i32 flat_scratch_hi, 0x3141
|
||||
// CHECK: [0x41,0x31,0xe9,0xb1]
|
||||
|
||||
s_cmpk_eq_i32 vcc_lo, 0x3141
|
||||
// CHECK: [0x41,0x31,0xea,0xb1]
|
||||
|
||||
s_cmpk_eq_i32 vcc_hi, 0x3141
|
||||
// CHECK: [0x41,0x31,0xeb,0xb1]
|
||||
|
||||
s_cmpk_eq_i32 tba_lo, 0x3141
|
||||
// CHECK: [0x41,0x31,0xec,0xb1]
|
||||
|
||||
s_cmpk_eq_i32 tba_hi, 0x3141
|
||||
// CHECK: [0x41,0x31,0xed,0xb1]
|
||||
|
||||
s_cmpk_eq_i32 tma_lo, 0x3141
|
||||
// CHECK: [0x41,0x31,0xee,0xb1]
|
||||
|
||||
s_cmpk_eq_i32 tma_hi, 0x3141
|
||||
// CHECK: [0x41,0x31,0xef,0xb1]
|
||||
|
||||
s_cmpk_eq_i32 ttmp11, 0x3141
|
||||
// CHECK: [0x41,0x31,0xfb,0xb1]
|
||||
|
||||
s_cmpk_eq_i32 m0, 0x3141
|
||||
// CHECK: [0x41,0x31,0xfc,0xb1]
|
||||
|
||||
s_cmpk_eq_i32 exec_lo, 0x3141
|
||||
// CHECK: [0x41,0x31,0xfe,0xb1]
|
||||
|
||||
s_cmpk_eq_i32 exec_hi, 0x3141
|
||||
// CHECK: [0x41,0x31,0xff,0xb1]
|
||||
|
||||
s_cmpk_eq_i32 s1, 0xc1d1
|
||||
// CHECK: [0xd1,0xc1,0x81,0xb1]
|
||||
|
||||
s_cmpk_lg_i32 s1, 0x3141
|
||||
// CHECK: [0x41,0x31,0x01,0xb2]
|
||||
|
||||
s_cmpk_lg_i32 s103, 0x3141
|
||||
// CHECK: [0x41,0x31,0x67,0xb2]
|
||||
|
||||
s_cmpk_lg_i32 flat_scratch_lo, 0x3141
|
||||
// CHECK: [0x41,0x31,0x68,0xb2]
|
||||
|
||||
s_cmpk_lg_i32 flat_scratch_hi, 0x3141
|
||||
// CHECK: [0x41,0x31,0x69,0xb2]
|
||||
|
||||
s_cmpk_lg_i32 vcc_lo, 0x3141
|
||||
// CHECK: [0x41,0x31,0x6a,0xb2]
|
||||
|
||||
s_cmpk_lg_i32 vcc_hi, 0x3141
|
||||
// CHECK: [0x41,0x31,0x6b,0xb2]
|
||||
|
||||
s_cmpk_lg_i32 tba_lo, 0x3141
|
||||
// CHECK: [0x41,0x31,0x6c,0xb2]
|
||||
|
||||
s_cmpk_lg_i32 tba_hi, 0x3141
|
||||
// CHECK: [0x41,0x31,0x6d,0xb2]
|
||||
|
||||
s_cmpk_lg_i32 tma_lo, 0x3141
|
||||
// CHECK: [0x41,0x31,0x6e,0xb2]
|
||||
|
||||
s_cmpk_lg_i32 tma_hi, 0x3141
|
||||
// CHECK: [0x41,0x31,0x6f,0xb2]
|
||||
|
||||
s_cmpk_lg_i32 ttmp11, 0x3141
|
||||
// CHECK: [0x41,0x31,0x7b,0xb2]
|
||||
|
||||
s_cmpk_lg_i32 m0, 0x3141
|
||||
// CHECK: [0x41,0x31,0x7c,0xb2]
|
||||
|
||||
s_cmpk_lg_i32 exec_lo, 0x3141
|
||||
// CHECK: [0x41,0x31,0x7e,0xb2]
|
||||
|
||||
s_cmpk_lg_i32 exec_hi, 0x3141
|
||||
// CHECK: [0x41,0x31,0x7f,0xb2]
|
||||
|
||||
s_cmpk_lg_i32 s1, 0xc1d1
|
||||
// CHECK: [0xd1,0xc1,0x01,0xb2]
|
||||
|
||||
s_cmpk_gt_i32 s1, 0x3141
|
||||
// CHECK: [0x41,0x31,0x81,0xb2]
|
||||
|
||||
s_cmpk_gt_i32 s103, 0x3141
|
||||
// CHECK: [0x41,0x31,0xe7,0xb2]
|
||||
|
||||
s_cmpk_gt_i32 flat_scratch_lo, 0x3141
|
||||
// CHECK: [0x41,0x31,0xe8,0xb2]
|
||||
|
||||
s_cmpk_gt_i32 flat_scratch_hi, 0x3141
|
||||
// CHECK: [0x41,0x31,0xe9,0xb2]
|
||||
|
||||
s_cmpk_gt_i32 vcc_lo, 0x3141
|
||||
// CHECK: [0x41,0x31,0xea,0xb2]
|
||||
|
||||
s_cmpk_gt_i32 vcc_hi, 0x3141
|
||||
// CHECK: [0x41,0x31,0xeb,0xb2]
|
||||
|
||||
s_cmpk_gt_i32 tba_lo, 0x3141
|
||||
// CHECK: [0x41,0x31,0xec,0xb2]
|
||||
|
||||
s_cmpk_gt_i32 tba_hi, 0x3141
|
||||
// CHECK: [0x41,0x31,0xed,0xb2]
|
||||
|
||||
s_cmpk_gt_i32 tma_lo, 0x3141
|
||||
// CHECK: [0x41,0x31,0xee,0xb2]
|
||||
|
||||
s_cmpk_gt_i32 tma_hi, 0x3141
|
||||
// CHECK: [0x41,0x31,0xef,0xb2]
|
||||
|
||||
s_cmpk_gt_i32 ttmp11, 0x3141
|
||||
// CHECK: [0x41,0x31,0xfb,0xb2]
|
||||
|
||||
s_cmpk_gt_i32 m0, 0x3141
|
||||
// CHECK: [0x41,0x31,0xfc,0xb2]
|
||||
|
||||
s_cmpk_gt_i32 exec_lo, 0x3141
|
||||
// CHECK: [0x41,0x31,0xfe,0xb2]
|
||||
|
||||
s_cmpk_gt_i32 exec_hi, 0x3141
|
||||
// CHECK: [0x41,0x31,0xff,0xb2]
|
||||
|
||||
s_cmpk_gt_i32 s1, 0xc1d1
|
||||
// CHECK: [0xd1,0xc1,0x81,0xb2]
|
||||
|
||||
s_cmpk_ge_i32 s1, 0x3141
|
||||
// CHECK: [0x41,0x31,0x01,0xb3]
|
||||
|
||||
s_cmpk_ge_i32 s103, 0x3141
|
||||
// CHECK: [0x41,0x31,0x67,0xb3]
|
||||
|
||||
s_cmpk_ge_i32 flat_scratch_lo, 0x3141
|
||||
// CHECK: [0x41,0x31,0x68,0xb3]
|
||||
|
||||
s_cmpk_ge_i32 flat_scratch_hi, 0x3141
|
||||
// CHECK: [0x41,0x31,0x69,0xb3]
|
||||
|
||||
s_cmpk_ge_i32 vcc_lo, 0x3141
|
||||
// CHECK: [0x41,0x31,0x6a,0xb3]
|
||||
|
||||
s_cmpk_ge_i32 vcc_hi, 0x3141
|
||||
// CHECK: [0x41,0x31,0x6b,0xb3]
|
||||
|
||||
s_cmpk_ge_i32 tba_lo, 0x3141
|
||||
// CHECK: [0x41,0x31,0x6c,0xb3]
|
||||
|
||||
s_cmpk_ge_i32 tba_hi, 0x3141
|
||||
// CHECK: [0x41,0x31,0x6d,0xb3]
|
||||
|
||||
s_cmpk_ge_i32 tma_lo, 0x3141
|
||||
// CHECK: [0x41,0x31,0x6e,0xb3]
|
||||
|
||||
s_cmpk_ge_i32 tma_hi, 0x3141
|
||||
// CHECK: [0x41,0x31,0x6f,0xb3]
|
||||
|
||||
s_cmpk_ge_i32 ttmp11, 0x3141
|
||||
// CHECK: [0x41,0x31,0x7b,0xb3]
|
||||
|
||||
s_cmpk_ge_i32 m0, 0x3141
|
||||
// CHECK: [0x41,0x31,0x7c,0xb3]
|
||||
|
||||
s_cmpk_ge_i32 exec_lo, 0x3141
|
||||
// CHECK: [0x41,0x31,0x7e,0xb3]
|
||||
|
||||
s_cmpk_ge_i32 exec_hi, 0x3141
|
||||
// CHECK: [0x41,0x31,0x7f,0xb3]
|
||||
|
||||
s_cmpk_ge_i32 s1, 0xc1d1
|
||||
// CHECK: [0xd1,0xc1,0x01,0xb3]
|
||||
|
||||
s_cmpk_lt_i32 s1, 0x3141
|
||||
// CHECK: [0x41,0x31,0x81,0xb3]
|
||||
|
||||
s_cmpk_lt_i32 s103, 0x3141
|
||||
// CHECK: [0x41,0x31,0xe7,0xb3]
|
||||
|
||||
s_cmpk_lt_i32 flat_scratch_lo, 0x3141
|
||||
// CHECK: [0x41,0x31,0xe8,0xb3]
|
||||
|
||||
s_cmpk_lt_i32 flat_scratch_hi, 0x3141
|
||||
// CHECK: [0x41,0x31,0xe9,0xb3]
|
||||
|
||||
s_cmpk_lt_i32 vcc_lo, 0x3141
|
||||
// CHECK: [0x41,0x31,0xea,0xb3]
|
||||
|
||||
s_cmpk_lt_i32 vcc_hi, 0x3141
|
||||
// CHECK: [0x41,0x31,0xeb,0xb3]
|
||||
|
||||
s_cmpk_lt_i32 tba_lo, 0x3141
|
||||
// CHECK: [0x41,0x31,0xec,0xb3]
|
||||
|
||||
s_cmpk_lt_i32 tba_hi, 0x3141
|
||||
// CHECK: [0x41,0x31,0xed,0xb3]
|
||||
|
||||
s_cmpk_lt_i32 tma_lo, 0x3141
|
||||
// CHECK: [0x41,0x31,0xee,0xb3]
|
||||
|
||||
s_cmpk_lt_i32 tma_hi, 0x3141
|
||||
// CHECK: [0x41,0x31,0xef,0xb3]
|
||||
|
||||
s_cmpk_lt_i32 ttmp11, 0x3141
|
||||
// CHECK: [0x41,0x31,0xfb,0xb3]
|
||||
|
||||
s_cmpk_lt_i32 m0, 0x3141
|
||||
// CHECK: [0x41,0x31,0xfc,0xb3]
|
||||
|
||||
s_cmpk_lt_i32 exec_lo, 0x3141
|
||||
// CHECK: [0x41,0x31,0xfe,0xb3]
|
||||
|
||||
s_cmpk_lt_i32 exec_hi, 0x3141
|
||||
// CHECK: [0x41,0x31,0xff,0xb3]
|
||||
|
||||
s_cmpk_lt_i32 s1, 0xc1d1
|
||||
// CHECK: [0xd1,0xc1,0x81,0xb3]
|
||||
|
||||
s_cmpk_le_i32 s1, 0x3141
|
||||
// CHECK: [0x41,0x31,0x01,0xb4]
|
||||
|
||||
s_cmpk_le_i32 s103, 0x3141
|
||||
// CHECK: [0x41,0x31,0x67,0xb4]
|
||||
|
||||
s_cmpk_le_i32 flat_scratch_lo, 0x3141
|
||||
// CHECK: [0x41,0x31,0x68,0xb4]
|
||||
|
||||
s_cmpk_le_i32 flat_scratch_hi, 0x3141
|
||||
// CHECK: [0x41,0x31,0x69,0xb4]
|
||||
|
||||
s_cmpk_le_i32 vcc_lo, 0x3141
|
||||
// CHECK: [0x41,0x31,0x6a,0xb4]
|
||||
|
||||
s_cmpk_le_i32 vcc_hi, 0x3141
|
||||
// CHECK: [0x41,0x31,0x6b,0xb4]
|
||||
|
||||
s_cmpk_le_i32 tba_lo, 0x3141
|
||||
// CHECK: [0x41,0x31,0x6c,0xb4]
|
||||
|
||||
s_cmpk_le_i32 tba_hi, 0x3141
|
||||
// CHECK: [0x41,0x31,0x6d,0xb4]
|
||||
|
||||
s_cmpk_le_i32 tma_lo, 0x3141
|
||||
// CHECK: [0x41,0x31,0x6e,0xb4]
|
||||
|
||||
s_cmpk_le_i32 tma_hi, 0x3141
|
||||
// CHECK: [0x41,0x31,0x6f,0xb4]
|
||||
|
||||
s_cmpk_le_i32 ttmp11, 0x3141
|
||||
// CHECK: [0x41,0x31,0x7b,0xb4]
|
||||
|
||||
s_cmpk_le_i32 m0, 0x3141
|
||||
// CHECK: [0x41,0x31,0x7c,0xb4]
|
||||
|
||||
s_cmpk_le_i32 exec_lo, 0x3141
|
||||
// CHECK: [0x41,0x31,0x7e,0xb4]
|
||||
|
||||
s_cmpk_le_i32 exec_hi, 0x3141
|
||||
// CHECK: [0x41,0x31,0x7f,0xb4]
|
||||
|
||||
s_cmpk_le_i32 s1, 0xc1d1
|
||||
// CHECK: [0xd1,0xc1,0x01,0xb4]
|
||||
|
||||
s_cmpk_eq_u32 s1, 0x3141
|
||||
// CHECK: [0x41,0x31,0x81,0xb4]
|
||||
|
||||
s_cmpk_eq_u32 s103, 0x3141
|
||||
// CHECK: [0x41,0x31,0xe7,0xb4]
|
||||
|
||||
s_cmpk_eq_u32 flat_scratch_lo, 0x3141
|
||||
// CHECK: [0x41,0x31,0xe8,0xb4]
|
||||
|
||||
s_cmpk_eq_u32 flat_scratch_hi, 0x3141
|
||||
// CHECK: [0x41,0x31,0xe9,0xb4]
|
||||
|
||||
s_cmpk_eq_u32 vcc_lo, 0x3141
|
||||
// CHECK: [0x41,0x31,0xea,0xb4]
|
||||
|
||||
s_cmpk_eq_u32 vcc_hi, 0x3141
|
||||
// CHECK: [0x41,0x31,0xeb,0xb4]
|
||||
|
||||
s_cmpk_eq_u32 tba_lo, 0x3141
|
||||
// CHECK: [0x41,0x31,0xec,0xb4]
|
||||
|
||||
s_cmpk_eq_u32 tba_hi, 0x3141
|
||||
// CHECK: [0x41,0x31,0xed,0xb4]
|
||||
|
||||
s_cmpk_eq_u32 tma_lo, 0x3141
|
||||
// CHECK: [0x41,0x31,0xee,0xb4]
|
||||
|
||||
s_cmpk_eq_u32 tma_hi, 0x3141
|
||||
// CHECK: [0x41,0x31,0xef,0xb4]
|
||||
|
||||
s_cmpk_eq_u32 ttmp11, 0x3141
|
||||
// CHECK: [0x41,0x31,0xfb,0xb4]
|
||||
|
||||
s_cmpk_eq_u32 m0, 0x3141
|
||||
// CHECK: [0x41,0x31,0xfc,0xb4]
|
||||
|
||||
s_cmpk_eq_u32 exec_lo, 0x3141
|
||||
// CHECK: [0x41,0x31,0xfe,0xb4]
|
||||
|
||||
s_cmpk_eq_u32 exec_hi, 0x3141
|
||||
// CHECK: [0x41,0x31,0xff,0xb4]
|
||||
|
||||
s_cmpk_eq_u32 s1, 0xc1d1
|
||||
// CHECK: [0xd1,0xc1,0x81,0xb4]
|
||||
|
||||
s_cmpk_lg_u32 s1, 0x3141
|
||||
// CHECK: [0x41,0x31,0x01,0xb5]
|
||||
|
||||
s_cmpk_lg_u32 s103, 0x3141
|
||||
// CHECK: [0x41,0x31,0x67,0xb5]
|
||||
|
||||
s_cmpk_lg_u32 flat_scratch_lo, 0x3141
|
||||
// CHECK: [0x41,0x31,0x68,0xb5]
|
||||
|
||||
s_cmpk_lg_u32 flat_scratch_hi, 0x3141
|
||||
// CHECK: [0x41,0x31,0x69,0xb5]
|
||||
|
||||
s_cmpk_lg_u32 vcc_lo, 0x3141
|
||||
// CHECK: [0x41,0x31,0x6a,0xb5]
|
||||
|
||||
s_cmpk_lg_u32 vcc_hi, 0x3141
|
||||
// CHECK: [0x41,0x31,0x6b,0xb5]
|
||||
|
||||
s_cmpk_lg_u32 tba_lo, 0x3141
|
||||
// CHECK: [0x41,0x31,0x6c,0xb5]
|
||||
|
||||
s_cmpk_lg_u32 tba_hi, 0x3141
|
||||
// CHECK: [0x41,0x31,0x6d,0xb5]
|
||||
|
||||
s_cmpk_lg_u32 tma_lo, 0x3141
|
||||
// CHECK: [0x41,0x31,0x6e,0xb5]
|
||||
|
||||
s_cmpk_lg_u32 tma_hi, 0x3141
|
||||
// CHECK: [0x41,0x31,0x6f,0xb5]
|
||||
|
||||
s_cmpk_lg_u32 ttmp11, 0x3141
|
||||
// CHECK: [0x41,0x31,0x7b,0xb5]
|
||||
|
||||
s_cmpk_lg_u32 m0, 0x3141
|
||||
// CHECK: [0x41,0x31,0x7c,0xb5]
|
||||
|
||||
s_cmpk_lg_u32 exec_lo, 0x3141
|
||||
// CHECK: [0x41,0x31,0x7e,0xb5]
|
||||
|
||||
s_cmpk_lg_u32 exec_hi, 0x3141
|
||||
// CHECK: [0x41,0x31,0x7f,0xb5]
|
||||
|
||||
s_cmpk_lg_u32 s1, 0xc1d1
|
||||
// CHECK: [0xd1,0xc1,0x01,0xb5]
|
||||
|
||||
s_cmpk_gt_u32 s1, 0x3141
|
||||
// CHECK: [0x41,0x31,0x81,0xb5]
|
||||
|
||||
s_cmpk_gt_u32 s103, 0x3141
|
||||
// CHECK: [0x41,0x31,0xe7,0xb5]
|
||||
|
||||
s_cmpk_gt_u32 flat_scratch_lo, 0x3141
|
||||
// CHECK: [0x41,0x31,0xe8,0xb5]
|
||||
|
||||
s_cmpk_gt_u32 flat_scratch_hi, 0x3141
|
||||
// CHECK: [0x41,0x31,0xe9,0xb5]
|
||||
|
||||
s_cmpk_gt_u32 vcc_lo, 0x3141
|
||||
// CHECK: [0x41,0x31,0xea,0xb5]
|
||||
|
||||
s_cmpk_gt_u32 vcc_hi, 0x3141
|
||||
// CHECK: [0x41,0x31,0xeb,0xb5]
|
||||
|
||||
s_cmpk_gt_u32 tba_lo, 0x3141
|
||||
// CHECK: [0x41,0x31,0xec,0xb5]
|
||||
|
||||
s_cmpk_gt_u32 tba_hi, 0x3141
|
||||
// CHECK: [0x41,0x31,0xed,0xb5]
|
||||
|
||||
s_cmpk_gt_u32 tma_lo, 0x3141
|
||||
// CHECK: [0x41,0x31,0xee,0xb5]
|
||||
|
||||
s_cmpk_gt_u32 tma_hi, 0x3141
|
||||
// CHECK: [0x41,0x31,0xef,0xb5]
|
||||
|
||||
s_cmpk_gt_u32 ttmp11, 0x3141
|
||||
// CHECK: [0x41,0x31,0xfb,0xb5]
|
||||
|
||||
s_cmpk_gt_u32 m0, 0x3141
|
||||
// CHECK: [0x41,0x31,0xfc,0xb5]
|
||||
|
||||
s_cmpk_gt_u32 exec_lo, 0x3141
|
||||
// CHECK: [0x41,0x31,0xfe,0xb5]
|
||||
|
||||
s_cmpk_gt_u32 exec_hi, 0x3141
|
||||
// CHECK: [0x41,0x31,0xff,0xb5]
|
||||
|
||||
s_cmpk_gt_u32 s1, 0xc1d1
|
||||
// CHECK: [0xd1,0xc1,0x81,0xb5]
|
||||
|
||||
s_cmpk_ge_u32 s1, 0x3141
|
||||
// CHECK: [0x41,0x31,0x01,0xb6]
|
||||
|
||||
s_cmpk_ge_u32 s103, 0x3141
|
||||
// CHECK: [0x41,0x31,0x67,0xb6]
|
||||
|
||||
s_cmpk_ge_u32 flat_scratch_lo, 0x3141
|
||||
// CHECK: [0x41,0x31,0x68,0xb6]
|
||||
|
||||
s_cmpk_ge_u32 flat_scratch_hi, 0x3141
|
||||
// CHECK: [0x41,0x31,0x69,0xb6]
|
||||
|
||||
s_cmpk_ge_u32 vcc_lo, 0x3141
|
||||
// CHECK: [0x41,0x31,0x6a,0xb6]
|
||||
|
||||
s_cmpk_ge_u32 vcc_hi, 0x3141
|
||||
// CHECK: [0x41,0x31,0x6b,0xb6]
|
||||
|
||||
s_cmpk_ge_u32 tba_lo, 0x3141
|
||||
// CHECK: [0x41,0x31,0x6c,0xb6]
|
||||
|
||||
s_cmpk_ge_u32 tba_hi, 0x3141
|
||||
// CHECK: [0x41,0x31,0x6d,0xb6]
|
||||
|
||||
s_cmpk_ge_u32 tma_lo, 0x3141
|
||||
// CHECK: [0x41,0x31,0x6e,0xb6]
|
||||
|
||||
s_cmpk_ge_u32 tma_hi, 0x3141
|
||||
// CHECK: [0x41,0x31,0x6f,0xb6]
|
||||
|
||||
s_cmpk_ge_u32 ttmp11, 0x3141
|
||||
// CHECK: [0x41,0x31,0x7b,0xb6]
|
||||
|
||||
s_cmpk_ge_u32 m0, 0x3141
|
||||
// CHECK: [0x41,0x31,0x7c,0xb6]
|
||||
|
||||
s_cmpk_ge_u32 exec_lo, 0x3141
|
||||
// CHECK: [0x41,0x31,0x7e,0xb6]
|
||||
|
||||
s_cmpk_ge_u32 exec_hi, 0x3141
|
||||
// CHECK: [0x41,0x31,0x7f,0xb6]
|
||||
|
||||
s_cmpk_ge_u32 s1, 0xc1d1
|
||||
// CHECK: [0xd1,0xc1,0x01,0xb6]
|
||||
|
||||
s_cmpk_lt_u32 s1, 0x3141
|
||||
// CHECK: [0x41,0x31,0x81,0xb6]
|
||||
|
||||
s_cmpk_lt_u32 s103, 0x3141
|
||||
// CHECK: [0x41,0x31,0xe7,0xb6]
|
||||
|
||||
s_cmpk_lt_u32 flat_scratch_lo, 0x3141
|
||||
// CHECK: [0x41,0x31,0xe8,0xb6]
|
||||
|
||||
s_cmpk_lt_u32 flat_scratch_hi, 0x3141
|
||||
// CHECK: [0x41,0x31,0xe9,0xb6]
|
||||
|
||||
s_cmpk_lt_u32 vcc_lo, 0x3141
|
||||
// CHECK: [0x41,0x31,0xea,0xb6]
|
||||
|
||||
s_cmpk_lt_u32 vcc_hi, 0x3141
|
||||
// CHECK: [0x41,0x31,0xeb,0xb6]
|
||||
|
||||
s_cmpk_lt_u32 tba_lo, 0x3141
|
||||
// CHECK: [0x41,0x31,0xec,0xb6]
|
||||
|
||||
s_cmpk_lt_u32 tba_hi, 0x3141
|
||||
// CHECK: [0x41,0x31,0xed,0xb6]
|
||||
|
||||
s_cmpk_lt_u32 tma_lo, 0x3141
|
||||
// CHECK: [0x41,0x31,0xee,0xb6]
|
||||
|
||||
s_cmpk_lt_u32 tma_hi, 0x3141
|
||||
// CHECK: [0x41,0x31,0xef,0xb6]
|
||||
|
||||
s_cmpk_lt_u32 ttmp11, 0x3141
|
||||
// CHECK: [0x41,0x31,0xfb,0xb6]
|
||||
|
||||
s_cmpk_lt_u32 m0, 0x3141
|
||||
// CHECK: [0x41,0x31,0xfc,0xb6]
|
||||
|
||||
s_cmpk_lt_u32 exec_lo, 0x3141
|
||||
// CHECK: [0x41,0x31,0xfe,0xb6]
|
||||
|
||||
s_cmpk_lt_u32 exec_hi, 0x3141
|
||||
// CHECK: [0x41,0x31,0xff,0xb6]
|
||||
|
||||
s_cmpk_lt_u32 s1, 0xc1d1
|
||||
// CHECK: [0xd1,0xc1,0x81,0xb6]
|
||||
|
||||
s_cmpk_le_u32 s1, 0x3141
|
||||
// CHECK: [0x41,0x31,0x01,0xb7]
|
||||
|
||||
s_cmpk_le_u32 s103, 0x3141
|
||||
// CHECK: [0x41,0x31,0x67,0xb7]
|
||||
|
||||
s_cmpk_le_u32 flat_scratch_lo, 0x3141
|
||||
// CHECK: [0x41,0x31,0x68,0xb7]
|
||||
|
||||
s_cmpk_le_u32 flat_scratch_hi, 0x3141
|
||||
// CHECK: [0x41,0x31,0x69,0xb7]
|
||||
|
||||
s_cmpk_le_u32 vcc_lo, 0x3141
|
||||
// CHECK: [0x41,0x31,0x6a,0xb7]
|
||||
|
||||
s_cmpk_le_u32 vcc_hi, 0x3141
|
||||
// CHECK: [0x41,0x31,0x6b,0xb7]
|
||||
|
||||
s_cmpk_le_u32 tba_lo, 0x3141
|
||||
// CHECK: [0x41,0x31,0x6c,0xb7]
|
||||
|
||||
s_cmpk_le_u32 tba_hi, 0x3141
|
||||
// CHECK: [0x41,0x31,0x6d,0xb7]
|
||||
|
||||
s_cmpk_le_u32 tma_lo, 0x3141
|
||||
// CHECK: [0x41,0x31,0x6e,0xb7]
|
||||
|
||||
s_cmpk_le_u32 tma_hi, 0x3141
|
||||
// CHECK: [0x41,0x31,0x6f,0xb7]
|
||||
|
||||
s_cmpk_le_u32 ttmp11, 0x3141
|
||||
// CHECK: [0x41,0x31,0x7b,0xb7]
|
||||
|
||||
s_cmpk_le_u32 m0, 0x3141
|
||||
// CHECK: [0x41,0x31,0x7c,0xb7]
|
||||
|
||||
s_cmpk_le_u32 exec_lo, 0x3141
|
||||
// CHECK: [0x41,0x31,0x7e,0xb7]
|
||||
|
||||
s_cmpk_le_u32 exec_hi, 0x3141
|
||||
// CHECK: [0x41,0x31,0x7f,0xb7]
|
||||
|
||||
s_cmpk_le_u32 s1, 0xc1d1
|
||||
// CHECK: [0xd1,0xc1,0x01,0xb7]
|
||||
|
||||
s_addk_i32 s5, 0x3141
|
||||
// CHECK: [0x41,0x31,0x85,0xb7]
|
||||
|
||||
s_addk_i32 s103, 0x3141
|
||||
// CHECK: [0x41,0x31,0xe7,0xb7]
|
||||
|
||||
s_addk_i32 flat_scratch_lo, 0x3141
|
||||
// CHECK: [0x41,0x31,0xe8,0xb7]
|
||||
|
||||
s_addk_i32 flat_scratch_hi, 0x3141
|
||||
// CHECK: [0x41,0x31,0xe9,0xb7]
|
||||
|
||||
s_addk_i32 vcc_lo, 0x3141
|
||||
// CHECK: [0x41,0x31,0xea,0xb7]
|
||||
|
||||
s_addk_i32 vcc_hi, 0x3141
|
||||
// CHECK: [0x41,0x31,0xeb,0xb7]
|
||||
|
||||
s_addk_i32 tba_lo, 0x3141
|
||||
// CHECK: [0x41,0x31,0xec,0xb7]
|
||||
|
||||
s_addk_i32 tba_hi, 0x3141
|
||||
// CHECK: [0x41,0x31,0xed,0xb7]
|
||||
|
||||
s_addk_i32 tma_lo, 0x3141
|
||||
// CHECK: [0x41,0x31,0xee,0xb7]
|
||||
|
||||
s_addk_i32 tma_hi, 0x3141
|
||||
// CHECK: [0x41,0x31,0xef,0xb7]
|
||||
|
||||
s_addk_i32 ttmp11, 0x3141
|
||||
// CHECK: [0x41,0x31,0xfb,0xb7]
|
||||
|
||||
s_addk_i32 m0, 0x3141
|
||||
// CHECK: [0x41,0x31,0xfc,0xb7]
|
||||
|
||||
s_addk_i32 exec_lo, 0x3141
|
||||
// CHECK: [0x41,0x31,0xfe,0xb7]
|
||||
|
||||
s_addk_i32 exec_hi, 0x3141
|
||||
// CHECK: [0x41,0x31,0xff,0xb7]
|
||||
|
||||
s_addk_i32 s5, 0xc1d1
|
||||
// CHECK: [0xd1,0xc1,0x85,0xb7]
|
||||
|
||||
s_mulk_i32 s5, 0x3141
|
||||
// CHECK: [0x41,0x31,0x05,0xb8]
|
||||
|
||||
s_mulk_i32 s103, 0x3141
|
||||
// CHECK: [0x41,0x31,0x67,0xb8]
|
||||
|
||||
s_mulk_i32 flat_scratch_lo, 0x3141
|
||||
// CHECK: [0x41,0x31,0x68,0xb8]
|
||||
|
||||
s_mulk_i32 flat_scratch_hi, 0x3141
|
||||
// CHECK: [0x41,0x31,0x69,0xb8]
|
||||
|
||||
s_mulk_i32 vcc_lo, 0x3141
|
||||
// CHECK: [0x41,0x31,0x6a,0xb8]
|
||||
|
||||
s_mulk_i32 vcc_hi, 0x3141
|
||||
// CHECK: [0x41,0x31,0x6b,0xb8]
|
||||
|
||||
s_mulk_i32 tba_lo, 0x3141
|
||||
// CHECK: [0x41,0x31,0x6c,0xb8]
|
||||
|
||||
s_mulk_i32 tba_hi, 0x3141
|
||||
// CHECK: [0x41,0x31,0x6d,0xb8]
|
||||
|
||||
s_mulk_i32 tma_lo, 0x3141
|
||||
// CHECK: [0x41,0x31,0x6e,0xb8]
|
||||
|
||||
s_mulk_i32 tma_hi, 0x3141
|
||||
// CHECK: [0x41,0x31,0x6f,0xb8]
|
||||
|
||||
s_mulk_i32 ttmp11, 0x3141
|
||||
// CHECK: [0x41,0x31,0x7b,0xb8]
|
||||
|
||||
s_mulk_i32 m0, 0x3141
|
||||
// CHECK: [0x41,0x31,0x7c,0xb8]
|
||||
|
||||
s_mulk_i32 exec_lo, 0x3141
|
||||
// CHECK: [0x41,0x31,0x7e,0xb8]
|
||||
|
||||
s_mulk_i32 exec_hi, 0x3141
|
||||
// CHECK: [0x41,0x31,0x7f,0xb8]
|
||||
|
||||
s_mulk_i32 s5, 0xc1d1
|
||||
// CHECK: [0xd1,0xc1,0x05,0xb8]
|
||||
|
||||
s_cbranch_i_fork s[2:3], 12609
|
||||
// CHECK: [0x41,0x31,0x82,0xb8]
|
||||
|
||||
s_cbranch_i_fork s[4:5], 12609
|
||||
// CHECK: [0x41,0x31,0x84,0xb8]
|
||||
|
||||
s_cbranch_i_fork s[102:103], 12609
|
||||
// CHECK: [0x41,0x31,0xe6,0xb8]
|
||||
|
||||
s_cbranch_i_fork flat_scratch, 12609
|
||||
// CHECK: [0x41,0x31,0xe8,0xb8]
|
||||
|
||||
s_cbranch_i_fork vcc, 12609
|
||||
// CHECK: [0x41,0x31,0xea,0xb8]
|
||||
|
||||
s_cbranch_i_fork tba, 12609
|
||||
// CHECK: [0x41,0x31,0xec,0xb8]
|
||||
|
||||
s_cbranch_i_fork tma, 12609
|
||||
// CHECK: [0x41,0x31,0xee,0xb8]
|
||||
|
||||
s_cbranch_i_fork ttmp[10:11], 12609
|
||||
// CHECK: [0x41,0x31,0xfa,0xb8]
|
||||
|
||||
s_cbranch_i_fork exec, 12609
|
||||
// CHECK: [0x41,0x31,0xfe,0xb8]
|
||||
|
||||
s_cbranch_i_fork s[2:3], 49617
|
||||
// CHECK: [0xd1,0xc1,0x82,0xb8]
|
||||
|
||||
s_getreg_b32 s5, 0x3141
|
||||
// CHECK: [0x41,0x31,0x05,0xb9]
|
||||
|
||||
s_getreg_b32 s103, 0x3141
|
||||
// CHECK: [0x41,0x31,0x67,0xb9]
|
||||
|
||||
s_getreg_b32 flat_scratch_lo, 0x3141
|
||||
// CHECK: [0x41,0x31,0x68,0xb9]
|
||||
|
||||
s_getreg_b32 flat_scratch_hi, 0x3141
|
||||
// CHECK: [0x41,0x31,0x69,0xb9]
|
||||
|
||||
s_getreg_b32 vcc_lo, 0x3141
|
||||
// CHECK: [0x41,0x31,0x6a,0xb9]
|
||||
|
||||
s_getreg_b32 vcc_hi, 0x3141
|
||||
// CHECK: [0x41,0x31,0x6b,0xb9]
|
||||
|
||||
s_getreg_b32 tba_lo, 0x3141
|
||||
// CHECK: [0x41,0x31,0x6c,0xb9]
|
||||
|
||||
s_getreg_b32 tba_hi, 0x3141
|
||||
// CHECK: [0x41,0x31,0x6d,0xb9]
|
||||
|
||||
s_getreg_b32 tma_lo, 0x3141
|
||||
// CHECK: [0x41,0x31,0x6e,0xb9]
|
||||
|
||||
s_getreg_b32 tma_hi, 0x3141
|
||||
// CHECK: [0x41,0x31,0x6f,0xb9]
|
||||
|
||||
s_getreg_b32 ttmp11, 0x3141
|
||||
// CHECK: [0x41,0x31,0x7b,0xb9]
|
||||
|
||||
s_getreg_b32 m0, 0x3141
|
||||
// CHECK: [0x41,0x31,0x7c,0xb9]
|
||||
|
||||
s_getreg_b32 exec_lo, 0x3141
|
||||
// CHECK: [0x41,0x31,0x7e,0xb9]
|
||||
|
||||
s_getreg_b32 exec_hi, 0x3141
|
||||
// CHECK: [0x41,0x31,0x7f,0xb9]
|
||||
|
||||
s_getreg_b32 s5, 0xc1d1
|
||||
// CHECK: [0xd1,0xc1,0x05,0xb9]
|
||||
|
||||
s_setreg_b32 0x3141, s1
|
||||
// CHECK: [0x41,0x31,0x81,0xb9]
|
||||
|
||||
s_setreg_b32 0xc1d1, s1
|
||||
// CHECK: [0xd1,0xc1,0x81,0xb9]
|
||||
|
||||
s_setreg_b32 0x3141, s103
|
||||
// CHECK: [0x41,0x31,0xe7,0xb9]
|
||||
|
||||
s_setreg_b32 0x3141, flat_scratch_lo
|
||||
// CHECK: [0x41,0x31,0xe8,0xb9]
|
||||
|
||||
s_setreg_b32 0x3141, flat_scratch_hi
|
||||
// CHECK: [0x41,0x31,0xe9,0xb9]
|
||||
|
||||
s_setreg_b32 0x3141, vcc_lo
|
||||
// CHECK: [0x41,0x31,0xea,0xb9]
|
||||
|
||||
s_setreg_b32 0x3141, vcc_hi
|
||||
// CHECK: [0x41,0x31,0xeb,0xb9]
|
||||
|
||||
s_setreg_b32 0x3141, tba_lo
|
||||
// CHECK: [0x41,0x31,0xec,0xb9]
|
||||
|
||||
s_setreg_b32 0x3141, tba_hi
|
||||
// CHECK: [0x41,0x31,0xed,0xb9]
|
||||
|
||||
s_setreg_b32 0x3141, tma_lo
|
||||
// CHECK: [0x41,0x31,0xee,0xb9]
|
||||
|
||||
s_setreg_b32 0x3141, tma_hi
|
||||
// CHECK: [0x41,0x31,0xef,0xb9]
|
||||
|
||||
s_setreg_b32 0x3141, ttmp11
|
||||
// CHECK: [0x41,0x31,0xfb,0xb9]
|
||||
|
||||
s_setreg_b32 0x3141, m0
|
||||
// CHECK: [0x41,0x31,0xfc,0xb9]
|
||||
|
||||
s_setreg_b32 0x3141, exec_lo
|
||||
// CHECK: [0x41,0x31,0xfe,0xb9]
|
||||
|
||||
s_setreg_b32 0x3141, exec_hi
|
||||
// CHECK: [0x41,0x31,0xff,0xb9]
|
||||
|
||||
s_setreg_imm32_b32 0x3141, 0x11213141
|
||||
// CHECK: [0x41,0x31,0x80,0xba,0x41,0x31,0x21,0x11]
|
||||
|
||||
s_setreg_imm32_b32 0xc1d1, 0x11213141
|
||||
// CHECK: [0xd1,0xc1,0x80,0xba,0x41,0x31,0x21,0x11]
|
||||
|
||||
s_setreg_imm32_b32 0x3141, 0xa1b1c1d1
|
||||
// CHECK: [0x41,0x31,0x80,0xba,0xd1,0xc1,0xb1,0xa1]
|
||||
|
|
@ -0,0 +1,145 @@
|
|||
// RUN: llvm-mc -arch=amdgcn -mcpu=bonaire -show-encoding %s | FileCheck %s
|
||||
|
||||
s_nop 0x3141
|
||||
// CHECK: [0x41,0x31,0x80,0xbf]
|
||||
|
||||
s_nop 0xc1d1
|
||||
// CHECK: [0xd1,0xc1,0x80,0xbf]
|
||||
|
||||
s_endpgm
|
||||
// CHECK: [0x00,0x00,0x81,0xbf]
|
||||
|
||||
s_branch 12609
|
||||
// CHECK: [0x41,0x31,0x82,0xbf]
|
||||
|
||||
s_branch 49617
|
||||
// CHECK: [0xd1,0xc1,0x82,0xbf]
|
||||
|
||||
s_cbranch_scc0 12609
|
||||
// CHECK: [0x41,0x31,0x84,0xbf]
|
||||
|
||||
s_cbranch_scc0 49617
|
||||
// CHECK: [0xd1,0xc1,0x84,0xbf]
|
||||
|
||||
s_cbranch_scc1 12609
|
||||
// CHECK: [0x41,0x31,0x85,0xbf]
|
||||
|
||||
s_cbranch_scc1 49617
|
||||
// CHECK: [0xd1,0xc1,0x85,0xbf]
|
||||
|
||||
s_cbranch_vccz 12609
|
||||
// CHECK: [0x41,0x31,0x86,0xbf]
|
||||
|
||||
s_cbranch_vccz 49617
|
||||
// CHECK: [0xd1,0xc1,0x86,0xbf]
|
||||
|
||||
s_cbranch_vccnz 12609
|
||||
// CHECK: [0x41,0x31,0x87,0xbf]
|
||||
|
||||
s_cbranch_vccnz 49617
|
||||
// CHECK: [0xd1,0xc1,0x87,0xbf]
|
||||
|
||||
s_cbranch_execz 12609
|
||||
// CHECK: [0x41,0x31,0x88,0xbf]
|
||||
|
||||
s_cbranch_execz 49617
|
||||
// CHECK: [0xd1,0xc1,0x88,0xbf]
|
||||
|
||||
s_cbranch_execnz 12609
|
||||
// CHECK: [0x41,0x31,0x89,0xbf]
|
||||
|
||||
s_cbranch_execnz 49617
|
||||
// CHECK: [0xd1,0xc1,0x89,0xbf]
|
||||
|
||||
s_barrier
|
||||
// CHECK: [0x00,0x00,0x8a,0xbf]
|
||||
|
||||
s_setkill 0x3141
|
||||
// CHECK: [0x41,0x31,0x8b,0xbf]
|
||||
|
||||
s_setkill 0xc1d1
|
||||
// CHECK: [0xd1,0xc1,0x8b,0xbf]
|
||||
|
||||
s_waitcnt 0x3141
|
||||
// CHECK: [0x41,0x31,0x8c,0xbf]
|
||||
|
||||
s_waitcnt 0xc1d1
|
||||
// CHECK: [0xd1,0xc1,0x8c,0xbf]
|
||||
|
||||
s_sethalt 0x3141
|
||||
// CHECK: [0x41,0x31,0x8d,0xbf]
|
||||
|
||||
s_sethalt 0xc1d1
|
||||
// CHECK: [0xd1,0xc1,0x8d,0xbf]
|
||||
|
||||
s_sleep 0x3141
|
||||
// CHECK: [0x41,0x31,0x8e,0xbf]
|
||||
|
||||
s_sleep 0xc1d1
|
||||
// CHECK: [0xd1,0xc1,0x8e,0xbf]
|
||||
|
||||
s_setprio 0x3141
|
||||
// CHECK: [0x41,0x31,0x8f,0xbf]
|
||||
|
||||
s_setprio 0xc1d1
|
||||
// CHECK: [0xd1,0xc1,0x8f,0xbf]
|
||||
|
||||
s_sendmsg 0x3141
|
||||
// CHECK: [0x41,0x31,0x90,0xbf]
|
||||
|
||||
s_sendmsg 0xc1d1
|
||||
// CHECK: [0xd1,0xc1,0x90,0xbf]
|
||||
|
||||
s_sendmsghalt 0x3141
|
||||
// CHECK: [0x41,0x31,0x91,0xbf]
|
||||
|
||||
s_sendmsghalt 0xc1d1
|
||||
// CHECK: [0xd1,0xc1,0x91,0xbf]
|
||||
|
||||
s_trap 0x3141
|
||||
// CHECK: [0x41,0x31,0x92,0xbf]
|
||||
|
||||
s_trap 0xc1d1
|
||||
// CHECK: [0xd1,0xc1,0x92,0xbf]
|
||||
|
||||
s_icache_inv
|
||||
// CHECK: [0x00,0x00,0x93,0xbf]
|
||||
|
||||
s_incperflevel 0x3141
|
||||
// CHECK: [0x41,0x31,0x94,0xbf]
|
||||
|
||||
s_incperflevel 0xc1d1
|
||||
// CHECK: [0xd1,0xc1,0x94,0xbf]
|
||||
|
||||
s_decperflevel 0x3141
|
||||
// CHECK: [0x41,0x31,0x95,0xbf]
|
||||
|
||||
s_decperflevel 0xc1d1
|
||||
// CHECK: [0xd1,0xc1,0x95,0xbf]
|
||||
|
||||
s_ttracedata
|
||||
// CHECK: [0x00,0x00,0x96,0xbf]
|
||||
|
||||
s_cbranch_cdbgsys 12609
|
||||
// CHECK: [0x41,0x31,0x97,0xbf]
|
||||
|
||||
s_cbranch_cdbgsys 49617
|
||||
// CHECK: [0xd1,0xc1,0x97,0xbf]
|
||||
|
||||
s_cbranch_cdbguser 12609
|
||||
// CHECK: [0x41,0x31,0x98,0xbf]
|
||||
|
||||
s_cbranch_cdbguser 49617
|
||||
// CHECK: [0xd1,0xc1,0x98,0xbf]
|
||||
|
||||
s_cbranch_cdbgsys_or_user 12609
|
||||
// CHECK: [0x41,0x31,0x99,0xbf]
|
||||
|
||||
s_cbranch_cdbgsys_or_user 49617
|
||||
// CHECK: [0xd1,0xc1,0x99,0xbf]
|
||||
|
||||
s_cbranch_cdbgsys_and_user 12609
|
||||
// CHECK: [0x41,0x31,0x9a,0xbf]
|
||||
|
||||
s_cbranch_cdbgsys_and_user 49617
|
||||
// CHECK: [0xd1,0xc1,0x9a,0xbf]
|
||||
|
|
@ -0,0 +1,85 @@
|
|||
// RUN: llvm-mc -arch=amdgcn -mcpu=bonaire -show-encoding %s | FileCheck %s
|
||||
|
||||
v_interp_p1_f32 v5, v1, attr0.x
|
||||
// CHECK: [0x01,0x00,0x14,0xc8]
|
||||
|
||||
v_interp_p1_f32 v255, v1, attr0.x
|
||||
// CHECK: [0x01,0x00,0xfc,0xcb]
|
||||
|
||||
v_interp_p1_f32 v5, v255, attr0.x
|
||||
// CHECK: [0xff,0x00,0x14,0xc8]
|
||||
|
||||
v_interp_p1_f32 v5, v1, attr1.x
|
||||
// CHECK: [0x01,0x04,0x14,0xc8]
|
||||
|
||||
v_interp_p1_f32 v5, v1, attr31.x
|
||||
// CHECK: [0x01,0x7c,0x14,0xc8]
|
||||
|
||||
v_interp_p1_f32 v5, v1, attr32.x
|
||||
// CHECK: [0x01,0x80,0x14,0xc8]
|
||||
|
||||
v_interp_p1_f32 v5, v1, attr0.y
|
||||
// CHECK: [0x01,0x01,0x14,0xc8]
|
||||
|
||||
v_interp_p1_f32 v5, v1, attr0.z
|
||||
// CHECK: [0x01,0x02,0x14,0xc8]
|
||||
|
||||
v_interp_p1_f32 v5, v1, attr0.w
|
||||
// CHECK: [0x01,0x03,0x14,0xc8]
|
||||
|
||||
v_interp_p2_f32 v5, v1, attr0.x
|
||||
// CHECK: [0x01,0x00,0x15,0xc8]
|
||||
|
||||
v_interp_p2_f32 v255, v1, attr0.x
|
||||
// CHECK: [0x01,0x00,0xfd,0xcb]
|
||||
|
||||
v_interp_p2_f32 v5, v255, attr0.x
|
||||
// CHECK: [0xff,0x00,0x15,0xc8]
|
||||
|
||||
v_interp_p2_f32 v5, v1, attr1.x
|
||||
// CHECK: [0x01,0x04,0x15,0xc8]
|
||||
|
||||
v_interp_p2_f32 v5, v1, attr31.x
|
||||
// CHECK: [0x01,0x7c,0x15,0xc8]
|
||||
|
||||
v_interp_p2_f32 v5, v1, attr32.x
|
||||
// CHECK: [0x01,0x80,0x15,0xc8]
|
||||
|
||||
v_interp_p2_f32 v5, v1, attr0.y
|
||||
// CHECK: [0x01,0x01,0x15,0xc8]
|
||||
|
||||
v_interp_p2_f32 v5, v1, attr0.z
|
||||
// CHECK: [0x01,0x02,0x15,0xc8]
|
||||
|
||||
v_interp_p2_f32 v5, v1, attr0.w
|
||||
// CHECK: [0x01,0x03,0x15,0xc8]
|
||||
|
||||
v_interp_mov_f32 v5, p10, attr0.x
|
||||
// CHECK: [0x00,0x00,0x16,0xc8]
|
||||
|
||||
v_interp_mov_f32 v255, p10, attr0.x
|
||||
// CHECK: [0x00,0x00,0xfe,0xcb]
|
||||
|
||||
v_interp_mov_f32 v5, p20, attr0.x
|
||||
// CHECK: [0x01,0x00,0x16,0xc8]
|
||||
|
||||
v_interp_mov_f32 v5, p0, attr0.x
|
||||
// CHECK: [0x02,0x00,0x16,0xc8]
|
||||
|
||||
v_interp_mov_f32 v5, p10, attr1.x
|
||||
// CHECK: [0x00,0x04,0x16,0xc8]
|
||||
|
||||
v_interp_mov_f32 v5, p10, attr31.x
|
||||
// CHECK: [0x00,0x7c,0x16,0xc8]
|
||||
|
||||
v_interp_mov_f32 v5, p10, attr32.x
|
||||
// CHECK: [0x00,0x80,0x16,0xc8]
|
||||
|
||||
v_interp_mov_f32 v5, p10, attr0.y
|
||||
// CHECK: [0x00,0x01,0x16,0xc8]
|
||||
|
||||
v_interp_mov_f32 v5, p10, attr0.z
|
||||
// CHECK: [0x00,0x02,0x16,0xc8]
|
||||
|
||||
v_interp_mov_f32 v5, p10, attr0.w
|
||||
// CHECK: [0x00,0x03,0x16,0xc8]
|
||||
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
|
|
@ -0,0 +1,82 @@
|
|||
// RUN: llvm-mc -arch=amdgcn -mcpu=tonga -show-encoding %s | FileCheck %s
|
||||
|
||||
exp mrt0 v0, v0, v0, v0
|
||||
// CHECK: [0x0f,0x00,0x00,0xc4,0x00,0x00,0x00,0x00]
|
||||
|
||||
exp mrtz v0, v0, v0, v0
|
||||
// CHECK: [0x8f,0x00,0x00,0xc4,0x00,0x00,0x00,0x00]
|
||||
|
||||
exp null v0, v0, v0, v0
|
||||
// CHECK: [0x9f,0x00,0x00,0xc4,0x00,0x00,0x00,0x00]
|
||||
|
||||
exp pos0 v0, v0, v0, v0
|
||||
// CHECK: [0xcf,0x00,0x00,0xc4,0x00,0x00,0x00,0x00]
|
||||
|
||||
exp param0 v0, v0, v0, v0
|
||||
// CHECK: [0x0f,0x02,0x00,0xc4,0x00,0x00,0x00,0x00]
|
||||
|
||||
exp mrt0 v255, v0, v0, v0
|
||||
// CHECK: [0x0f,0x00,0x00,0xc4,0xff,0x00,0x00,0x00]
|
||||
|
||||
exp mrt0 v0, v255, v0, v0
|
||||
// CHECK: [0x0f,0x00,0x00,0xc4,0x00,0xff,0x00,0x00]
|
||||
|
||||
exp mrt0 v0, v0, v255, v0
|
||||
// CHECK: [0x0f,0x00,0x00,0xc4,0x00,0x00,0xff,0x00]
|
||||
|
||||
exp mrt0 v0, v0, v0, v255
|
||||
// CHECK: [0x0f,0x00,0x00,0xc4,0x00,0x00,0x00,0xff]
|
||||
|
||||
exp mrt0 v0, off, off, off
|
||||
// CHECK: [0x01,0x00,0x00,0xc4,0x00,0x00,0x00,0x00]
|
||||
|
||||
exp mrt0 off, v0, off, off
|
||||
// CHECK: [0x02,0x00,0x00,0xc4,0x00,0x00,0x00,0x00]
|
||||
|
||||
exp mrt0 v0, v0, off, off
|
||||
// CHECK: [0x03,0x00,0x00,0xc4,0x00,0x00,0x00,0x00]
|
||||
|
||||
exp mrt0 off, off, v0, off
|
||||
// CHECK: [0x04,0x00,0x00,0xc4,0x00,0x00,0x00,0x00]
|
||||
|
||||
exp mrt0 v0, off, v0, off
|
||||
// CHECK: [0x05,0x00,0x00,0xc4,0x00,0x00,0x00,0x00]
|
||||
|
||||
exp mrt0 off, v0, v0, off
|
||||
// CHECK: [0x06,0x00,0x00,0xc4,0x00,0x00,0x00,0x00]
|
||||
|
||||
exp mrt0 v0, v0, v0, off
|
||||
// CHECK: [0x07,0x00,0x00,0xc4,0x00,0x00,0x00,0x00]
|
||||
|
||||
exp mrt0 off, off, off, v0
|
||||
// CHECK: [0x08,0x00,0x00,0xc4,0x00,0x00,0x00,0x00]
|
||||
|
||||
exp mrt0 v0, off, off, v0
|
||||
// CHECK: [0x09,0x00,0x00,0xc4,0x00,0x00,0x00,0x00]
|
||||
|
||||
exp mrt0 off, v0, off, v0
|
||||
// CHECK: [0x0a,0x00,0x00,0xc4,0x00,0x00,0x00,0x00]
|
||||
|
||||
exp mrt0 v0, v0, off, v0
|
||||
// CHECK: [0x0b,0x00,0x00,0xc4,0x00,0x00,0x00,0x00]
|
||||
|
||||
exp mrt0 off, off, v0, v0
|
||||
// CHECK: [0x0c,0x00,0x00,0xc4,0x00,0x00,0x00,0x00]
|
||||
|
||||
exp mrt0 v0, off, v0, v0
|
||||
// CHECK: [0x0d,0x00,0x00,0xc4,0x00,0x00,0x00,0x00]
|
||||
|
||||
exp mrt0 off, v0, v0, v0
|
||||
// CHECK: [0x0e,0x00,0x00,0xc4,0x00,0x00,0x00,0x00]
|
||||
|
||||
exp mrt0 off, off, off, off
|
||||
// CHECK: [0x00,0x00,0x00,0xc4,0x00,0x00,0x00,0x00]
|
||||
|
||||
exp mrt0 v0, v0, v0, v0 done
|
||||
// CHECK: [0x0f,0x08,0x00,0xc4,0x00,0x00,0x00,0x00]
|
||||
|
||||
exp mrt0 v0, v0, v0, v0 compr
|
||||
// CHECK: [0x0f,0x04,0x00,0xc4,0x00,0x00,0x00,0x00]
|
||||
|
||||
exp mrt0 v0, v0, v0, v0 vm
|
||||
// CHECK: [0x0f,0x10,0x00,0xc4,0x00,0x00,0x00,0x00]
|
||||
|
|
@ -0,0 +1,601 @@
|
|||
// RUN: llvm-mc -arch=amdgcn -mcpu=tonga -show-encoding %s | FileCheck %s
|
||||
|
||||
flat_load_ubyte v5, v[1:2]
|
||||
// CHECK: [0x00,0x00,0x40,0xdc,0x01,0x00,0x00,0x05]
|
||||
|
||||
flat_load_ubyte v255, v[1:2]
|
||||
// CHECK: [0x00,0x00,0x40,0xdc,0x01,0x00,0x00,0xff]
|
||||
|
||||
flat_load_ubyte v5, v[254:255]
|
||||
// CHECK: [0x00,0x00,0x40,0xdc,0xfe,0x00,0x00,0x05]
|
||||
|
||||
flat_load_ubyte v5, v[1:2] glc
|
||||
// CHECK: [0x00,0x00,0x41,0xdc,0x01,0x00,0x00,0x05]
|
||||
|
||||
flat_load_ubyte v5, v[1:2] slc
|
||||
// CHECK: [0x00,0x00,0x42,0xdc,0x01,0x00,0x00,0x05]
|
||||
|
||||
flat_load_sbyte v5, v[1:2]
|
||||
// CHECK: [0x00,0x00,0x44,0xdc,0x01,0x00,0x00,0x05]
|
||||
|
||||
flat_load_sbyte v255, v[1:2]
|
||||
// CHECK: [0x00,0x00,0x44,0xdc,0x01,0x00,0x00,0xff]
|
||||
|
||||
flat_load_sbyte v5, v[254:255]
|
||||
// CHECK: [0x00,0x00,0x44,0xdc,0xfe,0x00,0x00,0x05]
|
||||
|
||||
flat_load_sbyte v5, v[1:2] glc
|
||||
// CHECK: [0x00,0x00,0x45,0xdc,0x01,0x00,0x00,0x05]
|
||||
|
||||
flat_load_sbyte v5, v[1:2] slc
|
||||
// CHECK: [0x00,0x00,0x46,0xdc,0x01,0x00,0x00,0x05]
|
||||
|
||||
flat_load_ushort v5, v[1:2]
|
||||
// CHECK: [0x00,0x00,0x48,0xdc,0x01,0x00,0x00,0x05]
|
||||
|
||||
flat_load_ushort v255, v[1:2]
|
||||
// CHECK: [0x00,0x00,0x48,0xdc,0x01,0x00,0x00,0xff]
|
||||
|
||||
flat_load_ushort v5, v[254:255]
|
||||
// CHECK: [0x00,0x00,0x48,0xdc,0xfe,0x00,0x00,0x05]
|
||||
|
||||
flat_load_ushort v5, v[1:2] glc
|
||||
// CHECK: [0x00,0x00,0x49,0xdc,0x01,0x00,0x00,0x05]
|
||||
|
||||
flat_load_ushort v5, v[1:2] slc
|
||||
// CHECK: [0x00,0x00,0x4a,0xdc,0x01,0x00,0x00,0x05]
|
||||
|
||||
flat_load_sshort v5, v[1:2]
|
||||
// CHECK: [0x00,0x00,0x4c,0xdc,0x01,0x00,0x00,0x05]
|
||||
|
||||
flat_load_sshort v255, v[1:2]
|
||||
// CHECK: [0x00,0x00,0x4c,0xdc,0x01,0x00,0x00,0xff]
|
||||
|
||||
flat_load_sshort v5, v[254:255]
|
||||
// CHECK: [0x00,0x00,0x4c,0xdc,0xfe,0x00,0x00,0x05]
|
||||
|
||||
flat_load_sshort v5, v[1:2] glc
|
||||
// CHECK: [0x00,0x00,0x4d,0xdc,0x01,0x00,0x00,0x05]
|
||||
|
||||
flat_load_sshort v5, v[1:2] slc
|
||||
// CHECK: [0x00,0x00,0x4e,0xdc,0x01,0x00,0x00,0x05]
|
||||
|
||||
flat_load_dword v5, v[1:2]
|
||||
// CHECK: [0x00,0x00,0x50,0xdc,0x01,0x00,0x00,0x05]
|
||||
|
||||
flat_load_dword v255, v[1:2]
|
||||
// CHECK: [0x00,0x00,0x50,0xdc,0x01,0x00,0x00,0xff]
|
||||
|
||||
flat_load_dword v5, v[254:255]
|
||||
// CHECK: [0x00,0x00,0x50,0xdc,0xfe,0x00,0x00,0x05]
|
||||
|
||||
flat_load_dword v5, v[1:2] glc
|
||||
// CHECK: [0x00,0x00,0x51,0xdc,0x01,0x00,0x00,0x05]
|
||||
|
||||
flat_load_dword v5, v[1:2] slc
|
||||
// CHECK: [0x00,0x00,0x52,0xdc,0x01,0x00,0x00,0x05]
|
||||
|
||||
flat_load_dwordx2 v[5:6], v[1:2]
|
||||
// CHECK: [0x00,0x00,0x54,0xdc,0x01,0x00,0x00,0x05]
|
||||
|
||||
flat_load_dwordx2 v[254:255], v[1:2]
|
||||
// CHECK: [0x00,0x00,0x54,0xdc,0x01,0x00,0x00,0xfe]
|
||||
|
||||
flat_load_dwordx2 v[5:6], v[254:255]
|
||||
// CHECK: [0x00,0x00,0x54,0xdc,0xfe,0x00,0x00,0x05]
|
||||
|
||||
flat_load_dwordx2 v[5:6], v[1:2] glc
|
||||
// CHECK: [0x00,0x00,0x55,0xdc,0x01,0x00,0x00,0x05]
|
||||
|
||||
flat_load_dwordx2 v[5:6], v[1:2] slc
|
||||
// CHECK: [0x00,0x00,0x56,0xdc,0x01,0x00,0x00,0x05]
|
||||
|
||||
flat_load_dwordx3 v[5:7], v[1:2]
|
||||
// CHECK: [0x00,0x00,0x58,0xdc,0x01,0x00,0x00,0x05]
|
||||
|
||||
flat_load_dwordx3 v[253:255], v[1:2]
|
||||
// CHECK: [0x00,0x00,0x58,0xdc,0x01,0x00,0x00,0xfd]
|
||||
|
||||
flat_load_dwordx3 v[5:7], v[254:255]
|
||||
// CHECK: [0x00,0x00,0x58,0xdc,0xfe,0x00,0x00,0x05]
|
||||
|
||||
flat_load_dwordx3 v[5:7], v[1:2] glc
|
||||
// CHECK: [0x00,0x00,0x59,0xdc,0x01,0x00,0x00,0x05]
|
||||
|
||||
flat_load_dwordx3 v[5:7], v[1:2] slc
|
||||
// CHECK: [0x00,0x00,0x5a,0xdc,0x01,0x00,0x00,0x05]
|
||||
|
||||
flat_load_dwordx4 v[5:8], v[1:2]
|
||||
// CHECK: [0x00,0x00,0x5c,0xdc,0x01,0x00,0x00,0x05]
|
||||
|
||||
flat_load_dwordx4 v[252:255], v[1:2]
|
||||
// CHECK: [0x00,0x00,0x5c,0xdc,0x01,0x00,0x00,0xfc]
|
||||
|
||||
flat_load_dwordx4 v[5:8], v[254:255]
|
||||
// CHECK: [0x00,0x00,0x5c,0xdc,0xfe,0x00,0x00,0x05]
|
||||
|
||||
flat_load_dwordx4 v[5:8], v[1:2] glc
|
||||
// CHECK: [0x00,0x00,0x5d,0xdc,0x01,0x00,0x00,0x05]
|
||||
|
||||
flat_load_dwordx4 v[5:8], v[1:2] slc
|
||||
// CHECK: [0x00,0x00,0x5e,0xdc,0x01,0x00,0x00,0x05]
|
||||
|
||||
flat_store_byte v[1:2], v2
|
||||
// CHECK: [0x00,0x00,0x60,0xdc,0x01,0x02,0x00,0x00]
|
||||
|
||||
flat_store_byte v[254:255], v2
|
||||
// CHECK: [0x00,0x00,0x60,0xdc,0xfe,0x02,0x00,0x00]
|
||||
|
||||
flat_store_byte v[1:2], v255
|
||||
// CHECK: [0x00,0x00,0x60,0xdc,0x01,0xff,0x00,0x00]
|
||||
|
||||
flat_store_byte v[1:2], v2 glc
|
||||
// CHECK: [0x00,0x00,0x61,0xdc,0x01,0x02,0x00,0x00]
|
||||
|
||||
flat_store_byte v[1:2], v2 slc
|
||||
// CHECK: [0x00,0x00,0x62,0xdc,0x01,0x02,0x00,0x00]
|
||||
|
||||
flat_store_short v[1:2], v2
|
||||
// CHECK: [0x00,0x00,0x68,0xdc,0x01,0x02,0x00,0x00]
|
||||
|
||||
flat_store_short v[254:255], v2
|
||||
// CHECK: [0x00,0x00,0x68,0xdc,0xfe,0x02,0x00,0x00]
|
||||
|
||||
flat_store_short v[1:2], v255
|
||||
// CHECK: [0x00,0x00,0x68,0xdc,0x01,0xff,0x00,0x00]
|
||||
|
||||
flat_store_short v[1:2], v2 glc
|
||||
// CHECK: [0x00,0x00,0x69,0xdc,0x01,0x02,0x00,0x00]
|
||||
|
||||
flat_store_short v[1:2], v2 slc
|
||||
// CHECK: [0x00,0x00,0x6a,0xdc,0x01,0x02,0x00,0x00]
|
||||
|
||||
flat_store_dword v[1:2], v2
|
||||
// CHECK: [0x00,0x00,0x70,0xdc,0x01,0x02,0x00,0x00]
|
||||
|
||||
flat_store_dword v[254:255], v2
|
||||
// CHECK: [0x00,0x00,0x70,0xdc,0xfe,0x02,0x00,0x00]
|
||||
|
||||
flat_store_dword v[1:2], v255
|
||||
// CHECK: [0x00,0x00,0x70,0xdc,0x01,0xff,0x00,0x00]
|
||||
|
||||
flat_store_dword v[1:2], v2 glc
|
||||
// CHECK: [0x00,0x00,0x71,0xdc,0x01,0x02,0x00,0x00]
|
||||
|
||||
flat_store_dword v[1:2], v2 slc
|
||||
// CHECK: [0x00,0x00,0x72,0xdc,0x01,0x02,0x00,0x00]
|
||||
|
||||
flat_store_dwordx2 v[1:2], v[2:3]
|
||||
// CHECK: [0x00,0x00,0x74,0xdc,0x01,0x02,0x00,0x00]
|
||||
|
||||
flat_store_dwordx2 v[254:255], v[2:3]
|
||||
// CHECK: [0x00,0x00,0x74,0xdc,0xfe,0x02,0x00,0x00]
|
||||
|
||||
flat_store_dwordx2 v[1:2], v[254:255]
|
||||
// CHECK: [0x00,0x00,0x74,0xdc,0x01,0xfe,0x00,0x00]
|
||||
|
||||
flat_store_dwordx2 v[1:2], v[2:3] glc
|
||||
// CHECK: [0x00,0x00,0x75,0xdc,0x01,0x02,0x00,0x00]
|
||||
|
||||
flat_store_dwordx2 v[1:2], v[2:3] slc
|
||||
// CHECK: [0x00,0x00,0x76,0xdc,0x01,0x02,0x00,0x00]
|
||||
|
||||
flat_store_dwordx3 v[1:2], v[2:4]
|
||||
// CHECK: [0x00,0x00,0x78,0xdc,0x01,0x02,0x00,0x00]
|
||||
|
||||
flat_store_dwordx3 v[254:255], v[2:4]
|
||||
// CHECK: [0x00,0x00,0x78,0xdc,0xfe,0x02,0x00,0x00]
|
||||
|
||||
flat_store_dwordx3 v[1:2], v[253:255]
|
||||
// CHECK: [0x00,0x00,0x78,0xdc,0x01,0xfd,0x00,0x00]
|
||||
|
||||
flat_store_dwordx3 v[1:2], v[2:4] glc
|
||||
// CHECK: [0x00,0x00,0x79,0xdc,0x01,0x02,0x00,0x00]
|
||||
|
||||
flat_store_dwordx3 v[1:2], v[2:4] slc
|
||||
// CHECK: [0x00,0x00,0x7a,0xdc,0x01,0x02,0x00,0x00]
|
||||
|
||||
flat_store_dwordx4 v[1:2], v[2:5]
|
||||
// CHECK: [0x00,0x00,0x7c,0xdc,0x01,0x02,0x00,0x00]
|
||||
|
||||
flat_store_dwordx4 v[254:255], v[2:5]
|
||||
// CHECK: [0x00,0x00,0x7c,0xdc,0xfe,0x02,0x00,0x00]
|
||||
|
||||
flat_store_dwordx4 v[1:2], v[252:255]
|
||||
// CHECK: [0x00,0x00,0x7c,0xdc,0x01,0xfc,0x00,0x00]
|
||||
|
||||
flat_store_dwordx4 v[1:2], v[2:5] glc
|
||||
// CHECK: [0x00,0x00,0x7d,0xdc,0x01,0x02,0x00,0x00]
|
||||
|
||||
flat_store_dwordx4 v[1:2], v[2:5] slc
|
||||
// CHECK: [0x00,0x00,0x7e,0xdc,0x01,0x02,0x00,0x00]
|
||||
|
||||
flat_atomic_swap v[1:2], v2
|
||||
// CHECK: [0x00,0x00,0x00,0xdd,0x01,0x02,0x00,0x00]
|
||||
|
||||
flat_atomic_swap v[254:255], v2
|
||||
// CHECK: [0x00,0x00,0x00,0xdd,0xfe,0x02,0x00,0x00]
|
||||
|
||||
flat_atomic_swap v[1:2], v255
|
||||
// CHECK: [0x00,0x00,0x00,0xdd,0x01,0xff,0x00,0x00]
|
||||
|
||||
flat_atomic_swap v0, v[1:2], v2 glc
|
||||
// CHECK: [0x00,0x00,0x01,0xdd,0x01,0x02,0x00,0x00]
|
||||
|
||||
flat_atomic_swap v[1:2], v2 slc
|
||||
// CHECK: [0x00,0x00,0x02,0xdd,0x01,0x02,0x00,0x00]
|
||||
|
||||
flat_atomic_cmpswap v[1:2], v[2:3]
|
||||
// CHECK: [0x00,0x00,0x04,0xdd,0x01,0x02,0x00,0x00]
|
||||
|
||||
flat_atomic_cmpswap v[254:255], v[2:3]
|
||||
// CHECK: [0x00,0x00,0x04,0xdd,0xfe,0x02,0x00,0x00]
|
||||
|
||||
flat_atomic_cmpswap v[1:2], v[254:255]
|
||||
// CHECK: [0x00,0x00,0x04,0xdd,0x01,0xfe,0x00,0x00]
|
||||
|
||||
flat_atomic_cmpswap v0, v[1:2], v[2:3] glc
|
||||
// CHECK: [0x00,0x00,0x05,0xdd,0x01,0x02,0x00,0x00]
|
||||
|
||||
flat_atomic_cmpswap v[1:2], v[2:3] slc
|
||||
// CHECK: [0x00,0x00,0x06,0xdd,0x01,0x02,0x00,0x00]
|
||||
|
||||
flat_atomic_add v[1:2], v2
|
||||
// CHECK: [0x00,0x00,0x08,0xdd,0x01,0x02,0x00,0x00]
|
||||
|
||||
flat_atomic_add v[254:255], v2
|
||||
// CHECK: [0x00,0x00,0x08,0xdd,0xfe,0x02,0x00,0x00]
|
||||
|
||||
flat_atomic_add v[1:2], v255
|
||||
// CHECK: [0x00,0x00,0x08,0xdd,0x01,0xff,0x00,0x00]
|
||||
|
||||
flat_atomic_add v0, v[1:2], v2 glc
|
||||
// CHECK: [0x00,0x00,0x09,0xdd,0x01,0x02,0x00,0x00]
|
||||
|
||||
flat_atomic_add v[1:2], v2 slc
|
||||
// CHECK: [0x00,0x00,0x0a,0xdd,0x01,0x02,0x00,0x00]
|
||||
|
||||
flat_atomic_sub v[1:2], v2
|
||||
// CHECK: [0x00,0x00,0x0c,0xdd,0x01,0x02,0x00,0x00]
|
||||
|
||||
flat_atomic_sub v[254:255], v2
|
||||
// CHECK: [0x00,0x00,0x0c,0xdd,0xfe,0x02,0x00,0x00]
|
||||
|
||||
flat_atomic_sub v[1:2], v255
|
||||
// CHECK: [0x00,0x00,0x0c,0xdd,0x01,0xff,0x00,0x00]
|
||||
|
||||
flat_atomic_sub v0, v[1:2], v2 glc
|
||||
// CHECK: [0x00,0x00,0x0d,0xdd,0x01,0x02,0x00,0x00]
|
||||
|
||||
flat_atomic_sub v[1:2], v2 slc
|
||||
// CHECK: [0x00,0x00,0x0e,0xdd,0x01,0x02,0x00,0x00]
|
||||
|
||||
flat_atomic_smin v[1:2], v2
|
||||
// CHECK: [0x00,0x00,0x10,0xdd,0x01,0x02,0x00,0x00]
|
||||
|
||||
flat_atomic_smin v[254:255], v2
|
||||
// CHECK: [0x00,0x00,0x10,0xdd,0xfe,0x02,0x00,0x00]
|
||||
|
||||
flat_atomic_smin v[1:2], v255
|
||||
// CHECK: [0x00,0x00,0x10,0xdd,0x01,0xff,0x00,0x00]
|
||||
|
||||
flat_atomic_smin v0, v[1:2], v2 glc
|
||||
// CHECK: [0x00,0x00,0x11,0xdd,0x01,0x02,0x00,0x00]
|
||||
|
||||
flat_atomic_smin v[1:2], v2 slc
|
||||
// CHECK: [0x00,0x00,0x12,0xdd,0x01,0x02,0x00,0x00]
|
||||
|
||||
flat_atomic_umin v[1:2], v2
|
||||
// CHECK: [0x00,0x00,0x14,0xdd,0x01,0x02,0x00,0x00]
|
||||
|
||||
flat_atomic_umin v[254:255], v2
|
||||
// CHECK: [0x00,0x00,0x14,0xdd,0xfe,0x02,0x00,0x00]
|
||||
|
||||
flat_atomic_umin v[1:2], v255
|
||||
// CHECK: [0x00,0x00,0x14,0xdd,0x01,0xff,0x00,0x00]
|
||||
|
||||
flat_atomic_umin v0, v[1:2], v2 glc
|
||||
// CHECK: [0x00,0x00,0x15,0xdd,0x01,0x02,0x00,0x00]
|
||||
|
||||
flat_atomic_umin v[1:2], v2 slc
|
||||
// CHECK: [0x00,0x00,0x16,0xdd,0x01,0x02,0x00,0x00]
|
||||
|
||||
flat_atomic_smax v[1:2], v2
|
||||
// CHECK: [0x00,0x00,0x18,0xdd,0x01,0x02,0x00,0x00]
|
||||
|
||||
flat_atomic_smax v[254:255], v2
|
||||
// CHECK: [0x00,0x00,0x18,0xdd,0xfe,0x02,0x00,0x00]
|
||||
|
||||
flat_atomic_smax v[1:2], v255
|
||||
// CHECK: [0x00,0x00,0x18,0xdd,0x01,0xff,0x00,0x00]
|
||||
|
||||
flat_atomic_smax v0, v[1:2], v2 glc
|
||||
// CHECK: [0x00,0x00,0x19,0xdd,0x01,0x02,0x00,0x00]
|
||||
|
||||
flat_atomic_smax v[1:2], v2 slc
|
||||
// CHECK: [0x00,0x00,0x1a,0xdd,0x01,0x02,0x00,0x00]
|
||||
|
||||
flat_atomic_umax v[1:2], v2
|
||||
// CHECK: [0x00,0x00,0x1c,0xdd,0x01,0x02,0x00,0x00]
|
||||
|
||||
flat_atomic_umax v[254:255], v2
|
||||
// CHECK: [0x00,0x00,0x1c,0xdd,0xfe,0x02,0x00,0x00]
|
||||
|
||||
flat_atomic_umax v[1:2], v255
|
||||
// CHECK: [0x00,0x00,0x1c,0xdd,0x01,0xff,0x00,0x00]
|
||||
|
||||
flat_atomic_umax v0, v[1:2], v2 glc
|
||||
// CHECK: [0x00,0x00,0x1d,0xdd,0x01,0x02,0x00,0x00]
|
||||
|
||||
flat_atomic_umax v[1:2], v2 slc
|
||||
// CHECK: [0x00,0x00,0x1e,0xdd,0x01,0x02,0x00,0x00]
|
||||
|
||||
flat_atomic_and v[1:2], v2
|
||||
// CHECK: [0x00,0x00,0x20,0xdd,0x01,0x02,0x00,0x00]
|
||||
|
||||
flat_atomic_and v[254:255], v2
|
||||
// CHECK: [0x00,0x00,0x20,0xdd,0xfe,0x02,0x00,0x00]
|
||||
|
||||
flat_atomic_and v[1:2], v255
|
||||
// CHECK: [0x00,0x00,0x20,0xdd,0x01,0xff,0x00,0x00]
|
||||
|
||||
flat_atomic_and v0, v[1:2], v2 glc
|
||||
// CHECK: [0x00,0x00,0x21,0xdd,0x01,0x02,0x00,0x00]
|
||||
|
||||
flat_atomic_and v[1:2], v2 slc
|
||||
// CHECK: [0x00,0x00,0x22,0xdd,0x01,0x02,0x00,0x00]
|
||||
|
||||
flat_atomic_or v[1:2], v2
|
||||
// CHECK: [0x00,0x00,0x24,0xdd,0x01,0x02,0x00,0x00]
|
||||
|
||||
flat_atomic_or v[254:255], v2
|
||||
// CHECK: [0x00,0x00,0x24,0xdd,0xfe,0x02,0x00,0x00]
|
||||
|
||||
flat_atomic_or v[1:2], v255
|
||||
// CHECK: [0x00,0x00,0x24,0xdd,0x01,0xff,0x00,0x00]
|
||||
|
||||
flat_atomic_or v0, v[1:2], v2 glc
|
||||
// CHECK: [0x00,0x00,0x25,0xdd,0x01,0x02,0x00,0x00]
|
||||
|
||||
flat_atomic_or v[1:2], v2 slc
|
||||
// CHECK: [0x00,0x00,0x26,0xdd,0x01,0x02,0x00,0x00]
|
||||
|
||||
flat_atomic_xor v[1:2], v2
|
||||
// CHECK: [0x00,0x00,0x28,0xdd,0x01,0x02,0x00,0x00]
|
||||
|
||||
flat_atomic_xor v[254:255], v2
|
||||
// CHECK: [0x00,0x00,0x28,0xdd,0xfe,0x02,0x00,0x00]
|
||||
|
||||
flat_atomic_xor v[1:2], v255
|
||||
// CHECK: [0x00,0x00,0x28,0xdd,0x01,0xff,0x00,0x00]
|
||||
|
||||
flat_atomic_xor v0, v[1:2], v2 glc
|
||||
// CHECK: [0x00,0x00,0x29,0xdd,0x01,0x02,0x00,0x00]
|
||||
|
||||
flat_atomic_xor v[1:2], v2 slc
|
||||
// CHECK: [0x00,0x00,0x2a,0xdd,0x01,0x02,0x00,0x00]
|
||||
|
||||
flat_atomic_inc v[1:2], v2
|
||||
// CHECK: [0x00,0x00,0x2c,0xdd,0x01,0x02,0x00,0x00]
|
||||
|
||||
flat_atomic_inc v[254:255], v2
|
||||
// CHECK: [0x00,0x00,0x2c,0xdd,0xfe,0x02,0x00,0x00]
|
||||
|
||||
flat_atomic_inc v[1:2], v255
|
||||
// CHECK: [0x00,0x00,0x2c,0xdd,0x01,0xff,0x00,0x00]
|
||||
|
||||
flat_atomic_inc v0, v[1:2], v2 glc
|
||||
// CHECK: [0x00,0x00,0x2d,0xdd,0x01,0x02,0x00,0x00]
|
||||
|
||||
flat_atomic_inc v[1:2], v2 slc
|
||||
// CHECK: [0x00,0x00,0x2e,0xdd,0x01,0x02,0x00,0x00]
|
||||
|
||||
flat_atomic_dec v[1:2], v2
|
||||
// CHECK: [0x00,0x00,0x30,0xdd,0x01,0x02,0x00,0x00]
|
||||
|
||||
flat_atomic_dec v[254:255], v2
|
||||
// CHECK: [0x00,0x00,0x30,0xdd,0xfe,0x02,0x00,0x00]
|
||||
|
||||
flat_atomic_dec v[1:2], v255
|
||||
// CHECK: [0x00,0x00,0x30,0xdd,0x01,0xff,0x00,0x00]
|
||||
|
||||
flat_atomic_dec v0, v[1:2], v2 glc
|
||||
// CHECK: [0x00,0x00,0x31,0xdd,0x01,0x02,0x00,0x00]
|
||||
|
||||
flat_atomic_dec v[1:2], v2 slc
|
||||
// CHECK: [0x00,0x00,0x32,0xdd,0x01,0x02,0x00,0x00]
|
||||
|
||||
flat_atomic_swap_x2 v[1:2], v[2:3]
|
||||
// CHECK: [0x00,0x00,0x80,0xdd,0x01,0x02,0x00,0x00]
|
||||
|
||||
flat_atomic_swap_x2 v[254:255], v[2:3]
|
||||
// CHECK: [0x00,0x00,0x80,0xdd,0xfe,0x02,0x00,0x00]
|
||||
|
||||
flat_atomic_swap_x2 v[1:2], v[254:255]
|
||||
// CHECK: [0x00,0x00,0x80,0xdd,0x01,0xfe,0x00,0x00]
|
||||
|
||||
flat_atomic_swap_x2 v[0:1], v[1:2], v[2:3] glc
|
||||
// CHECK: [0x00,0x00,0x81,0xdd,0x01,0x02,0x00,0x00]
|
||||
|
||||
flat_atomic_swap_x2 v[1:2], v[2:3] slc
|
||||
// CHECK: [0x00,0x00,0x82,0xdd,0x01,0x02,0x00,0x00]
|
||||
|
||||
flat_atomic_cmpswap_x2 v[1:2], v[2:5]
|
||||
// CHECK: [0x00,0x00,0x84,0xdd,0x01,0x02,0x00,0x00]
|
||||
|
||||
flat_atomic_cmpswap_x2 v[254:255], v[2:5]
|
||||
// CHECK: [0x00,0x00,0x84,0xdd,0xfe,0x02,0x00,0x00]
|
||||
|
||||
flat_atomic_cmpswap_x2 v[1:2], v[252:255]
|
||||
// CHECK: [0x00,0x00,0x84,0xdd,0x01,0xfc,0x00,0x00]
|
||||
|
||||
flat_atomic_cmpswap_x2 v[0:1], v[1:2], v[2:5] glc
|
||||
// CHECK: [0x00,0x00,0x85,0xdd,0x01,0x02,0x00,0x00]
|
||||
|
||||
flat_atomic_cmpswap_x2 v[1:2], v[2:5] slc
|
||||
// CHECK: [0x00,0x00,0x86,0xdd,0x01,0x02,0x00,0x00]
|
||||
|
||||
flat_atomic_add_x2 v[1:2], v[2:3]
|
||||
// CHECK: [0x00,0x00,0x88,0xdd,0x01,0x02,0x00,0x00]
|
||||
|
||||
flat_atomic_add_x2 v[254:255], v[2:3]
|
||||
// CHECK: [0x00,0x00,0x88,0xdd,0xfe,0x02,0x00,0x00]
|
||||
|
||||
flat_atomic_add_x2 v[1:2], v[254:255]
|
||||
// CHECK: [0x00,0x00,0x88,0xdd,0x01,0xfe,0x00,0x00]
|
||||
|
||||
flat_atomic_add_x2 v[0:1], v[1:2], v[2:3] glc
|
||||
// CHECK: [0x00,0x00,0x89,0xdd,0x01,0x02,0x00,0x00]
|
||||
|
||||
flat_atomic_add_x2 v[1:2], v[2:3] slc
|
||||
// CHECK: [0x00,0x00,0x8a,0xdd,0x01,0x02,0x00,0x00]
|
||||
|
||||
flat_atomic_sub_x2 v[1:2], v[2:3]
|
||||
// CHECK: [0x00,0x00,0x8c,0xdd,0x01,0x02,0x00,0x00]
|
||||
|
||||
flat_atomic_sub_x2 v[254:255], v[2:3]
|
||||
// CHECK: [0x00,0x00,0x8c,0xdd,0xfe,0x02,0x00,0x00]
|
||||
|
||||
flat_atomic_sub_x2 v[1:2], v[254:255]
|
||||
// CHECK: [0x00,0x00,0x8c,0xdd,0x01,0xfe,0x00,0x00]
|
||||
|
||||
flat_atomic_sub_x2 v[0:1], v[1:2], v[2:3] glc
|
||||
// CHECK: [0x00,0x00,0x8d,0xdd,0x01,0x02,0x00,0x00]
|
||||
|
||||
flat_atomic_sub_x2 v[1:2], v[2:3] slc
|
||||
// CHECK: [0x00,0x00,0x8e,0xdd,0x01,0x02,0x00,0x00]
|
||||
|
||||
flat_atomic_smin_x2 v[1:2], v[2:3]
|
||||
// CHECK: [0x00,0x00,0x90,0xdd,0x01,0x02,0x00,0x00]
|
||||
|
||||
flat_atomic_smin_x2 v[254:255], v[2:3]
|
||||
// CHECK: [0x00,0x00,0x90,0xdd,0xfe,0x02,0x00,0x00]
|
||||
|
||||
flat_atomic_smin_x2 v[1:2], v[254:255]
|
||||
// CHECK: [0x00,0x00,0x90,0xdd,0x01,0xfe,0x00,0x00]
|
||||
|
||||
flat_atomic_smin_x2 v[0:1], v[1:2], v[2:3] glc
|
||||
// CHECK: [0x00,0x00,0x91,0xdd,0x01,0x02,0x00,0x00]
|
||||
|
||||
flat_atomic_smin_x2 v[1:2], v[2:3] slc
|
||||
// CHECK: [0x00,0x00,0x92,0xdd,0x01,0x02,0x00,0x00]
|
||||
|
||||
flat_atomic_umin_x2 v[1:2], v[2:3]
|
||||
// CHECK: [0x00,0x00,0x94,0xdd,0x01,0x02,0x00,0x00]
|
||||
|
||||
flat_atomic_umin_x2 v[254:255], v[2:3]
|
||||
// CHECK: [0x00,0x00,0x94,0xdd,0xfe,0x02,0x00,0x00]
|
||||
|
||||
flat_atomic_umin_x2 v[1:2], v[254:255]
|
||||
// CHECK: [0x00,0x00,0x94,0xdd,0x01,0xfe,0x00,0x00]
|
||||
|
||||
flat_atomic_umin_x2 v[0:1], v[1:2], v[2:3] glc
|
||||
// CHECK: [0x00,0x00,0x95,0xdd,0x01,0x02,0x00,0x00]
|
||||
|
||||
flat_atomic_umin_x2 v[1:2], v[2:3] slc
|
||||
// CHECK: [0x00,0x00,0x96,0xdd,0x01,0x02,0x00,0x00]
|
||||
|
||||
flat_atomic_smax_x2 v[1:2], v[2:3]
|
||||
// CHECK: [0x00,0x00,0x98,0xdd,0x01,0x02,0x00,0x00]
|
||||
|
||||
flat_atomic_smax_x2 v[254:255], v[2:3]
|
||||
// CHECK: [0x00,0x00,0x98,0xdd,0xfe,0x02,0x00,0x00]
|
||||
|
||||
flat_atomic_smax_x2 v[1:2], v[254:255]
|
||||
// CHECK: [0x00,0x00,0x98,0xdd,0x01,0xfe,0x00,0x00]
|
||||
|
||||
flat_atomic_smax_x2 v[0:1], v[1:2], v[2:3] glc
|
||||
// CHECK: [0x00,0x00,0x99,0xdd,0x01,0x02,0x00,0x00]
|
||||
|
||||
flat_atomic_smax_x2 v[1:2], v[2:3] slc
|
||||
// CHECK: [0x00,0x00,0x9a,0xdd,0x01,0x02,0x00,0x00]
|
||||
|
||||
flat_atomic_umax_x2 v[1:2], v[2:3]
|
||||
// CHECK: [0x00,0x00,0x9c,0xdd,0x01,0x02,0x00,0x00]
|
||||
|
||||
flat_atomic_umax_x2 v[254:255], v[2:3]
|
||||
// CHECK: [0x00,0x00,0x9c,0xdd,0xfe,0x02,0x00,0x00]
|
||||
|
||||
flat_atomic_umax_x2 v[1:2], v[254:255]
|
||||
// CHECK: [0x00,0x00,0x9c,0xdd,0x01,0xfe,0x00,0x00]
|
||||
|
||||
flat_atomic_umax_x2 v[0:1], v[1:2], v[2:3] glc
|
||||
// CHECK: [0x00,0x00,0x9d,0xdd,0x01,0x02,0x00,0x00]
|
||||
|
||||
flat_atomic_umax_x2 v[1:2], v[2:3] slc
|
||||
// CHECK: [0x00,0x00,0x9e,0xdd,0x01,0x02,0x00,0x00]
|
||||
|
||||
flat_atomic_and_x2 v[1:2], v[2:3]
|
||||
// CHECK: [0x00,0x00,0xa0,0xdd,0x01,0x02,0x00,0x00]
|
||||
|
||||
flat_atomic_and_x2 v[254:255], v[2:3]
|
||||
// CHECK: [0x00,0x00,0xa0,0xdd,0xfe,0x02,0x00,0x00]
|
||||
|
||||
flat_atomic_and_x2 v[1:2], v[254:255]
|
||||
// CHECK: [0x00,0x00,0xa0,0xdd,0x01,0xfe,0x00,0x00]
|
||||
|
||||
flat_atomic_and_x2 v[0:1], v[1:2], v[2:3] glc
|
||||
// CHECK: [0x00,0x00,0xa1,0xdd,0x01,0x02,0x00,0x00]
|
||||
|
||||
flat_atomic_and_x2 v[1:2], v[2:3] slc
|
||||
// CHECK: [0x00,0x00,0xa2,0xdd,0x01,0x02,0x00,0x00]
|
||||
|
||||
flat_atomic_or_x2 v[1:2], v[2:3]
|
||||
// CHECK: [0x00,0x00,0xa4,0xdd,0x01,0x02,0x00,0x00]
|
||||
|
||||
flat_atomic_or_x2 v[254:255], v[2:3]
|
||||
// CHECK: [0x00,0x00,0xa4,0xdd,0xfe,0x02,0x00,0x00]
|
||||
|
||||
flat_atomic_or_x2 v[1:2], v[254:255]
|
||||
// CHECK: [0x00,0x00,0xa4,0xdd,0x01,0xfe,0x00,0x00]
|
||||
|
||||
flat_atomic_or_x2 v[0:1], v[1:2], v[2:3] glc
|
||||
// CHECK: [0x00,0x00,0xa5,0xdd,0x01,0x02,0x00,0x00]
|
||||
|
||||
flat_atomic_or_x2 v[1:2], v[2:3] slc
|
||||
// CHECK: [0x00,0x00,0xa6,0xdd,0x01,0x02,0x00,0x00]
|
||||
|
||||
flat_atomic_xor_x2 v[1:2], v[2:3]
|
||||
// CHECK: [0x00,0x00,0xa8,0xdd,0x01,0x02,0x00,0x00]
|
||||
|
||||
flat_atomic_xor_x2 v[254:255], v[2:3]
|
||||
// CHECK: [0x00,0x00,0xa8,0xdd,0xfe,0x02,0x00,0x00]
|
||||
|
||||
flat_atomic_xor_x2 v[1:2], v[254:255]
|
||||
// CHECK: [0x00,0x00,0xa8,0xdd,0x01,0xfe,0x00,0x00]
|
||||
|
||||
flat_atomic_xor_x2 v[0:1], v[1:2], v[2:3] glc
|
||||
// CHECK: [0x00,0x00,0xa9,0xdd,0x01,0x02,0x00,0x00]
|
||||
|
||||
flat_atomic_xor_x2 v[1:2], v[2:3] slc
|
||||
// CHECK: [0x00,0x00,0xaa,0xdd,0x01,0x02,0x00,0x00]
|
||||
|
||||
flat_atomic_inc_x2 v[1:2], v[2:3]
|
||||
// CHECK: [0x00,0x00,0xac,0xdd,0x01,0x02,0x00,0x00]
|
||||
|
||||
flat_atomic_inc_x2 v[254:255], v[2:3]
|
||||
// CHECK: [0x00,0x00,0xac,0xdd,0xfe,0x02,0x00,0x00]
|
||||
|
||||
flat_atomic_inc_x2 v[1:2], v[254:255]
|
||||
// CHECK: [0x00,0x00,0xac,0xdd,0x01,0xfe,0x00,0x00]
|
||||
|
||||
flat_atomic_inc_x2 v[0:1], v[1:2], v[2:3] glc
|
||||
// CHECK: [0x00,0x00,0xad,0xdd,0x01,0x02,0x00,0x00]
|
||||
|
||||
flat_atomic_inc_x2 v[1:2], v[2:3] slc
|
||||
// CHECK: [0x00,0x00,0xae,0xdd,0x01,0x02,0x00,0x00]
|
||||
|
||||
flat_atomic_dec_x2 v[1:2], v[2:3]
|
||||
// CHECK: [0x00,0x00,0xb0,0xdd,0x01,0x02,0x00,0x00]
|
||||
|
||||
flat_atomic_dec_x2 v[254:255], v[2:3]
|
||||
// CHECK: [0x00,0x00,0xb0,0xdd,0xfe,0x02,0x00,0x00]
|
||||
|
||||
flat_atomic_dec_x2 v[1:2], v[254:255]
|
||||
// CHECK: [0x00,0x00,0xb0,0xdd,0x01,0xfe,0x00,0x00]
|
||||
|
||||
flat_atomic_dec_x2 v[0:1], v[1:2], v[2:3] glc
|
||||
// CHECK: [0x00,0x00,0xb1,0xdd,0x01,0x02,0x00,0x00]
|
||||
|
||||
flat_atomic_dec_x2 v[1:2], v[2:3] slc
|
||||
// CHECK: [0x00,0x00,0xb2,0xdd,0x01,0x02,0x00,0x00]
|
||||
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
|
|
@ -0,0 +1,850 @@
|
|||
// RUN: llvm-mc -arch=amdgcn -mcpu=tonga -show-encoding %s | FileCheck %s
|
||||
|
||||
s_movk_i32 s5, 0x3141
|
||||
// CHECK: [0x41,0x31,0x05,0xb0]
|
||||
|
||||
s_movk_i32 s101, 0x3141
|
||||
// CHECK: [0x41,0x31,0x65,0xb0]
|
||||
|
||||
s_movk_i32 flat_scratch_lo, 0x3141
|
||||
// CHECK: [0x41,0x31,0x66,0xb0]
|
||||
|
||||
s_movk_i32 flat_scratch_hi, 0x3141
|
||||
// CHECK: [0x41,0x31,0x67,0xb0]
|
||||
|
||||
s_movk_i32 vcc_lo, 0x3141
|
||||
// CHECK: [0x41,0x31,0x6a,0xb0]
|
||||
|
||||
s_movk_i32 vcc_hi, 0x3141
|
||||
// CHECK: [0x41,0x31,0x6b,0xb0]
|
||||
|
||||
s_movk_i32 tba_lo, 0x3141
|
||||
// CHECK: [0x41,0x31,0x6c,0xb0]
|
||||
|
||||
s_movk_i32 tba_hi, 0x3141
|
||||
// CHECK: [0x41,0x31,0x6d,0xb0]
|
||||
|
||||
s_movk_i32 tma_lo, 0x3141
|
||||
// CHECK: [0x41,0x31,0x6e,0xb0]
|
||||
|
||||
s_movk_i32 tma_hi, 0x3141
|
||||
// CHECK: [0x41,0x31,0x6f,0xb0]
|
||||
|
||||
s_movk_i32 ttmp11, 0x3141
|
||||
// CHECK: [0x41,0x31,0x7b,0xb0]
|
||||
|
||||
s_movk_i32 m0, 0x3141
|
||||
// CHECK: [0x41,0x31,0x7c,0xb0]
|
||||
|
||||
s_movk_i32 exec_lo, 0x3141
|
||||
// CHECK: [0x41,0x31,0x7e,0xb0]
|
||||
|
||||
s_movk_i32 exec_hi, 0x3141
|
||||
// CHECK: [0x41,0x31,0x7f,0xb0]
|
||||
|
||||
s_movk_i32 s5, 0xc1d1
|
||||
// CHECK: [0xd1,0xc1,0x05,0xb0]
|
||||
|
||||
s_cmovk_i32 s5, 0x3141
|
||||
// CHECK: [0x41,0x31,0x85,0xb0]
|
||||
|
||||
s_cmovk_i32 s101, 0x3141
|
||||
// CHECK: [0x41,0x31,0xe5,0xb0]
|
||||
|
||||
s_cmovk_i32 flat_scratch_lo, 0x3141
|
||||
// CHECK: [0x41,0x31,0xe6,0xb0]
|
||||
|
||||
s_cmovk_i32 flat_scratch_hi, 0x3141
|
||||
// CHECK: [0x41,0x31,0xe7,0xb0]
|
||||
|
||||
s_cmovk_i32 vcc_lo, 0x3141
|
||||
// CHECK: [0x41,0x31,0xea,0xb0]
|
||||
|
||||
s_cmovk_i32 vcc_hi, 0x3141
|
||||
// CHECK: [0x41,0x31,0xeb,0xb0]
|
||||
|
||||
s_cmovk_i32 tba_lo, 0x3141
|
||||
// CHECK: [0x41,0x31,0xec,0xb0]
|
||||
|
||||
s_cmovk_i32 tba_hi, 0x3141
|
||||
// CHECK: [0x41,0x31,0xed,0xb0]
|
||||
|
||||
s_cmovk_i32 tma_lo, 0x3141
|
||||
// CHECK: [0x41,0x31,0xee,0xb0]
|
||||
|
||||
s_cmovk_i32 tma_hi, 0x3141
|
||||
// CHECK: [0x41,0x31,0xef,0xb0]
|
||||
|
||||
s_cmovk_i32 ttmp11, 0x3141
|
||||
// CHECK: [0x41,0x31,0xfb,0xb0]
|
||||
|
||||
s_cmovk_i32 m0, 0x3141
|
||||
// CHECK: [0x41,0x31,0xfc,0xb0]
|
||||
|
||||
s_cmovk_i32 exec_lo, 0x3141
|
||||
// CHECK: [0x41,0x31,0xfe,0xb0]
|
||||
|
||||
s_cmovk_i32 exec_hi, 0x3141
|
||||
// CHECK: [0x41,0x31,0xff,0xb0]
|
||||
|
||||
s_cmovk_i32 s5, 0xc1d1
|
||||
// CHECK: [0xd1,0xc1,0x85,0xb0]
|
||||
|
||||
s_cmpk_eq_i32 s1, 0x3141
|
||||
// CHECK: [0x41,0x31,0x01,0xb1]
|
||||
|
||||
s_cmpk_eq_i32 s101, 0x3141
|
||||
// CHECK: [0x41,0x31,0x65,0xb1]
|
||||
|
||||
s_cmpk_eq_i32 flat_scratch_lo, 0x3141
|
||||
// CHECK: [0x41,0x31,0x66,0xb1]
|
||||
|
||||
s_cmpk_eq_i32 flat_scratch_hi, 0x3141
|
||||
// CHECK: [0x41,0x31,0x67,0xb1]
|
||||
|
||||
s_cmpk_eq_i32 vcc_lo, 0x3141
|
||||
// CHECK: [0x41,0x31,0x6a,0xb1]
|
||||
|
||||
s_cmpk_eq_i32 vcc_hi, 0x3141
|
||||
// CHECK: [0x41,0x31,0x6b,0xb1]
|
||||
|
||||
s_cmpk_eq_i32 tba_lo, 0x3141
|
||||
// CHECK: [0x41,0x31,0x6c,0xb1]
|
||||
|
||||
s_cmpk_eq_i32 tba_hi, 0x3141
|
||||
// CHECK: [0x41,0x31,0x6d,0xb1]
|
||||
|
||||
s_cmpk_eq_i32 tma_lo, 0x3141
|
||||
// CHECK: [0x41,0x31,0x6e,0xb1]
|
||||
|
||||
s_cmpk_eq_i32 tma_hi, 0x3141
|
||||
// CHECK: [0x41,0x31,0x6f,0xb1]
|
||||
|
||||
s_cmpk_eq_i32 ttmp11, 0x3141
|
||||
// CHECK: [0x41,0x31,0x7b,0xb1]
|
||||
|
||||
s_cmpk_eq_i32 m0, 0x3141
|
||||
// CHECK: [0x41,0x31,0x7c,0xb1]
|
||||
|
||||
s_cmpk_eq_i32 exec_lo, 0x3141
|
||||
// CHECK: [0x41,0x31,0x7e,0xb1]
|
||||
|
||||
s_cmpk_eq_i32 exec_hi, 0x3141
|
||||
// CHECK: [0x41,0x31,0x7f,0xb1]
|
||||
|
||||
s_cmpk_eq_i32 s1, 0xc1d1
|
||||
// CHECK: [0xd1,0xc1,0x01,0xb1]
|
||||
|
||||
s_cmpk_lg_i32 s1, 0x3141
|
||||
// CHECK: [0x41,0x31,0x81,0xb1]
|
||||
|
||||
s_cmpk_lg_i32 s101, 0x3141
|
||||
// CHECK: [0x41,0x31,0xe5,0xb1]
|
||||
|
||||
s_cmpk_lg_i32 flat_scratch_lo, 0x3141
|
||||
// CHECK: [0x41,0x31,0xe6,0xb1]
|
||||
|
||||
s_cmpk_lg_i32 flat_scratch_hi, 0x3141
|
||||
// CHECK: [0x41,0x31,0xe7,0xb1]
|
||||
|
||||
s_cmpk_lg_i32 vcc_lo, 0x3141
|
||||
// CHECK: [0x41,0x31,0xea,0xb1]
|
||||
|
||||
s_cmpk_lg_i32 vcc_hi, 0x3141
|
||||
// CHECK: [0x41,0x31,0xeb,0xb1]
|
||||
|
||||
s_cmpk_lg_i32 tba_lo, 0x3141
|
||||
// CHECK: [0x41,0x31,0xec,0xb1]
|
||||
|
||||
s_cmpk_lg_i32 tba_hi, 0x3141
|
||||
// CHECK: [0x41,0x31,0xed,0xb1]
|
||||
|
||||
s_cmpk_lg_i32 tma_lo, 0x3141
|
||||
// CHECK: [0x41,0x31,0xee,0xb1]
|
||||
|
||||
s_cmpk_lg_i32 tma_hi, 0x3141
|
||||
// CHECK: [0x41,0x31,0xef,0xb1]
|
||||
|
||||
s_cmpk_lg_i32 ttmp11, 0x3141
|
||||
// CHECK: [0x41,0x31,0xfb,0xb1]
|
||||
|
||||
s_cmpk_lg_i32 m0, 0x3141
|
||||
// CHECK: [0x41,0x31,0xfc,0xb1]
|
||||
|
||||
s_cmpk_lg_i32 exec_lo, 0x3141
|
||||
// CHECK: [0x41,0x31,0xfe,0xb1]
|
||||
|
||||
s_cmpk_lg_i32 exec_hi, 0x3141
|
||||
// CHECK: [0x41,0x31,0xff,0xb1]
|
||||
|
||||
s_cmpk_lg_i32 s1, 0xc1d1
|
||||
// CHECK: [0xd1,0xc1,0x81,0xb1]
|
||||
|
||||
s_cmpk_gt_i32 s1, 0x3141
|
||||
// CHECK: [0x41,0x31,0x01,0xb2]
|
||||
|
||||
s_cmpk_gt_i32 s101, 0x3141
|
||||
// CHECK: [0x41,0x31,0x65,0xb2]
|
||||
|
||||
s_cmpk_gt_i32 flat_scratch_lo, 0x3141
|
||||
// CHECK: [0x41,0x31,0x66,0xb2]
|
||||
|
||||
s_cmpk_gt_i32 flat_scratch_hi, 0x3141
|
||||
// CHECK: [0x41,0x31,0x67,0xb2]
|
||||
|
||||
s_cmpk_gt_i32 vcc_lo, 0x3141
|
||||
// CHECK: [0x41,0x31,0x6a,0xb2]
|
||||
|
||||
s_cmpk_gt_i32 vcc_hi, 0x3141
|
||||
// CHECK: [0x41,0x31,0x6b,0xb2]
|
||||
|
||||
s_cmpk_gt_i32 tba_lo, 0x3141
|
||||
// CHECK: [0x41,0x31,0x6c,0xb2]
|
||||
|
||||
s_cmpk_gt_i32 tba_hi, 0x3141
|
||||
// CHECK: [0x41,0x31,0x6d,0xb2]
|
||||
|
||||
s_cmpk_gt_i32 tma_lo, 0x3141
|
||||
// CHECK: [0x41,0x31,0x6e,0xb2]
|
||||
|
||||
s_cmpk_gt_i32 tma_hi, 0x3141
|
||||
// CHECK: [0x41,0x31,0x6f,0xb2]
|
||||
|
||||
s_cmpk_gt_i32 ttmp11, 0x3141
|
||||
// CHECK: [0x41,0x31,0x7b,0xb2]
|
||||
|
||||
s_cmpk_gt_i32 m0, 0x3141
|
||||
// CHECK: [0x41,0x31,0x7c,0xb2]
|
||||
|
||||
s_cmpk_gt_i32 exec_lo, 0x3141
|
||||
// CHECK: [0x41,0x31,0x7e,0xb2]
|
||||
|
||||
s_cmpk_gt_i32 exec_hi, 0x3141
|
||||
// CHECK: [0x41,0x31,0x7f,0xb2]
|
||||
|
||||
s_cmpk_gt_i32 s1, 0xc1d1
|
||||
// CHECK: [0xd1,0xc1,0x01,0xb2]
|
||||
|
||||
s_cmpk_ge_i32 s1, 0x3141
|
||||
// CHECK: [0x41,0x31,0x81,0xb2]
|
||||
|
||||
s_cmpk_ge_i32 s101, 0x3141
|
||||
// CHECK: [0x41,0x31,0xe5,0xb2]
|
||||
|
||||
s_cmpk_ge_i32 flat_scratch_lo, 0x3141
|
||||
// CHECK: [0x41,0x31,0xe6,0xb2]
|
||||
|
||||
s_cmpk_ge_i32 flat_scratch_hi, 0x3141
|
||||
// CHECK: [0x41,0x31,0xe7,0xb2]
|
||||
|
||||
s_cmpk_ge_i32 vcc_lo, 0x3141
|
||||
// CHECK: [0x41,0x31,0xea,0xb2]
|
||||
|
||||
s_cmpk_ge_i32 vcc_hi, 0x3141
|
||||
// CHECK: [0x41,0x31,0xeb,0xb2]
|
||||
|
||||
s_cmpk_ge_i32 tba_lo, 0x3141
|
||||
// CHECK: [0x41,0x31,0xec,0xb2]
|
||||
|
||||
s_cmpk_ge_i32 tba_hi, 0x3141
|
||||
// CHECK: [0x41,0x31,0xed,0xb2]
|
||||
|
||||
s_cmpk_ge_i32 tma_lo, 0x3141
|
||||
// CHECK: [0x41,0x31,0xee,0xb2]
|
||||
|
||||
s_cmpk_ge_i32 tma_hi, 0x3141
|
||||
// CHECK: [0x41,0x31,0xef,0xb2]
|
||||
|
||||
s_cmpk_ge_i32 ttmp11, 0x3141
|
||||
// CHECK: [0x41,0x31,0xfb,0xb2]
|
||||
|
||||
s_cmpk_ge_i32 m0, 0x3141
|
||||
// CHECK: [0x41,0x31,0xfc,0xb2]
|
||||
|
||||
s_cmpk_ge_i32 exec_lo, 0x3141
|
||||
// CHECK: [0x41,0x31,0xfe,0xb2]
|
||||
|
||||
s_cmpk_ge_i32 exec_hi, 0x3141
|
||||
// CHECK: [0x41,0x31,0xff,0xb2]
|
||||
|
||||
s_cmpk_ge_i32 s1, 0xc1d1
|
||||
// CHECK: [0xd1,0xc1,0x81,0xb2]
|
||||
|
||||
s_cmpk_lt_i32 s1, 0x3141
|
||||
// CHECK: [0x41,0x31,0x01,0xb3]
|
||||
|
||||
s_cmpk_lt_i32 s101, 0x3141
|
||||
// CHECK: [0x41,0x31,0x65,0xb3]
|
||||
|
||||
s_cmpk_lt_i32 flat_scratch_lo, 0x3141
|
||||
// CHECK: [0x41,0x31,0x66,0xb3]
|
||||
|
||||
s_cmpk_lt_i32 flat_scratch_hi, 0x3141
|
||||
// CHECK: [0x41,0x31,0x67,0xb3]
|
||||
|
||||
s_cmpk_lt_i32 vcc_lo, 0x3141
|
||||
// CHECK: [0x41,0x31,0x6a,0xb3]
|
||||
|
||||
s_cmpk_lt_i32 vcc_hi, 0x3141
|
||||
// CHECK: [0x41,0x31,0x6b,0xb3]
|
||||
|
||||
s_cmpk_lt_i32 tba_lo, 0x3141
|
||||
// CHECK: [0x41,0x31,0x6c,0xb3]
|
||||
|
||||
s_cmpk_lt_i32 tba_hi, 0x3141
|
||||
// CHECK: [0x41,0x31,0x6d,0xb3]
|
||||
|
||||
s_cmpk_lt_i32 tma_lo, 0x3141
|
||||
// CHECK: [0x41,0x31,0x6e,0xb3]
|
||||
|
||||
s_cmpk_lt_i32 tma_hi, 0x3141
|
||||
// CHECK: [0x41,0x31,0x6f,0xb3]
|
||||
|
||||
s_cmpk_lt_i32 ttmp11, 0x3141
|
||||
// CHECK: [0x41,0x31,0x7b,0xb3]
|
||||
|
||||
s_cmpk_lt_i32 m0, 0x3141
|
||||
// CHECK: [0x41,0x31,0x7c,0xb3]
|
||||
|
||||
s_cmpk_lt_i32 exec_lo, 0x3141
|
||||
// CHECK: [0x41,0x31,0x7e,0xb3]
|
||||
|
||||
s_cmpk_lt_i32 exec_hi, 0x3141
|
||||
// CHECK: [0x41,0x31,0x7f,0xb3]
|
||||
|
||||
s_cmpk_lt_i32 s1, 0xc1d1
|
||||
// CHECK: [0xd1,0xc1,0x01,0xb3]
|
||||
|
||||
s_cmpk_le_i32 s1, 0x3141
|
||||
// CHECK: [0x41,0x31,0x81,0xb3]
|
||||
|
||||
s_cmpk_le_i32 s101, 0x3141
|
||||
// CHECK: [0x41,0x31,0xe5,0xb3]
|
||||
|
||||
s_cmpk_le_i32 flat_scratch_lo, 0x3141
|
||||
// CHECK: [0x41,0x31,0xe6,0xb3]
|
||||
|
||||
s_cmpk_le_i32 flat_scratch_hi, 0x3141
|
||||
// CHECK: [0x41,0x31,0xe7,0xb3]
|
||||
|
||||
s_cmpk_le_i32 vcc_lo, 0x3141
|
||||
// CHECK: [0x41,0x31,0xea,0xb3]
|
||||
|
||||
s_cmpk_le_i32 vcc_hi, 0x3141
|
||||
// CHECK: [0x41,0x31,0xeb,0xb3]
|
||||
|
||||
s_cmpk_le_i32 tba_lo, 0x3141
|
||||
// CHECK: [0x41,0x31,0xec,0xb3]
|
||||
|
||||
s_cmpk_le_i32 tba_hi, 0x3141
|
||||
// CHECK: [0x41,0x31,0xed,0xb3]
|
||||
|
||||
s_cmpk_le_i32 tma_lo, 0x3141
|
||||
// CHECK: [0x41,0x31,0xee,0xb3]
|
||||
|
||||
s_cmpk_le_i32 tma_hi, 0x3141
|
||||
// CHECK: [0x41,0x31,0xef,0xb3]
|
||||
|
||||
s_cmpk_le_i32 ttmp11, 0x3141
|
||||
// CHECK: [0x41,0x31,0xfb,0xb3]
|
||||
|
||||
s_cmpk_le_i32 m0, 0x3141
|
||||
// CHECK: [0x41,0x31,0xfc,0xb3]
|
||||
|
||||
s_cmpk_le_i32 exec_lo, 0x3141
|
||||
// CHECK: [0x41,0x31,0xfe,0xb3]
|
||||
|
||||
s_cmpk_le_i32 exec_hi, 0x3141
|
||||
// CHECK: [0x41,0x31,0xff,0xb3]
|
||||
|
||||
s_cmpk_le_i32 s1, 0xc1d1
|
||||
// CHECK: [0xd1,0xc1,0x81,0xb3]
|
||||
|
||||
s_cmpk_eq_u32 s1, 0x3141
|
||||
// CHECK: [0x41,0x31,0x01,0xb4]
|
||||
|
||||
s_cmpk_eq_u32 s101, 0x3141
|
||||
// CHECK: [0x41,0x31,0x65,0xb4]
|
||||
|
||||
s_cmpk_eq_u32 flat_scratch_lo, 0x3141
|
||||
// CHECK: [0x41,0x31,0x66,0xb4]
|
||||
|
||||
s_cmpk_eq_u32 flat_scratch_hi, 0x3141
|
||||
// CHECK: [0x41,0x31,0x67,0xb4]
|
||||
|
||||
s_cmpk_eq_u32 vcc_lo, 0x3141
|
||||
// CHECK: [0x41,0x31,0x6a,0xb4]
|
||||
|
||||
s_cmpk_eq_u32 vcc_hi, 0x3141
|
||||
// CHECK: [0x41,0x31,0x6b,0xb4]
|
||||
|
||||
s_cmpk_eq_u32 tba_lo, 0x3141
|
||||
// CHECK: [0x41,0x31,0x6c,0xb4]
|
||||
|
||||
s_cmpk_eq_u32 tba_hi, 0x3141
|
||||
// CHECK: [0x41,0x31,0x6d,0xb4]
|
||||
|
||||
s_cmpk_eq_u32 tma_lo, 0x3141
|
||||
// CHECK: [0x41,0x31,0x6e,0xb4]
|
||||
|
||||
s_cmpk_eq_u32 tma_hi, 0x3141
|
||||
// CHECK: [0x41,0x31,0x6f,0xb4]
|
||||
|
||||
s_cmpk_eq_u32 ttmp11, 0x3141
|
||||
// CHECK: [0x41,0x31,0x7b,0xb4]
|
||||
|
||||
s_cmpk_eq_u32 m0, 0x3141
|
||||
// CHECK: [0x41,0x31,0x7c,0xb4]
|
||||
|
||||
s_cmpk_eq_u32 exec_lo, 0x3141
|
||||
// CHECK: [0x41,0x31,0x7e,0xb4]
|
||||
|
||||
s_cmpk_eq_u32 exec_hi, 0x3141
|
||||
// CHECK: [0x41,0x31,0x7f,0xb4]
|
||||
|
||||
s_cmpk_eq_u32 s1, 0xc1d1
|
||||
// CHECK: [0xd1,0xc1,0x01,0xb4]
|
||||
|
||||
s_cmpk_lg_u32 s1, 0x3141
|
||||
// CHECK: [0x41,0x31,0x81,0xb4]
|
||||
|
||||
s_cmpk_lg_u32 s101, 0x3141
|
||||
// CHECK: [0x41,0x31,0xe5,0xb4]
|
||||
|
||||
s_cmpk_lg_u32 flat_scratch_lo, 0x3141
|
||||
// CHECK: [0x41,0x31,0xe6,0xb4]
|
||||
|
||||
s_cmpk_lg_u32 flat_scratch_hi, 0x3141
|
||||
// CHECK: [0x41,0x31,0xe7,0xb4]
|
||||
|
||||
s_cmpk_lg_u32 vcc_lo, 0x3141
|
||||
// CHECK: [0x41,0x31,0xea,0xb4]
|
||||
|
||||
s_cmpk_lg_u32 vcc_hi, 0x3141
|
||||
// CHECK: [0x41,0x31,0xeb,0xb4]
|
||||
|
||||
s_cmpk_lg_u32 tba_lo, 0x3141
|
||||
// CHECK: [0x41,0x31,0xec,0xb4]
|
||||
|
||||
s_cmpk_lg_u32 tba_hi, 0x3141
|
||||
// CHECK: [0x41,0x31,0xed,0xb4]
|
||||
|
||||
s_cmpk_lg_u32 tma_lo, 0x3141
|
||||
// CHECK: [0x41,0x31,0xee,0xb4]
|
||||
|
||||
s_cmpk_lg_u32 tma_hi, 0x3141
|
||||
// CHECK: [0x41,0x31,0xef,0xb4]
|
||||
|
||||
s_cmpk_lg_u32 ttmp11, 0x3141
|
||||
// CHECK: [0x41,0x31,0xfb,0xb4]
|
||||
|
||||
s_cmpk_lg_u32 m0, 0x3141
|
||||
// CHECK: [0x41,0x31,0xfc,0xb4]
|
||||
|
||||
s_cmpk_lg_u32 exec_lo, 0x3141
|
||||
// CHECK: [0x41,0x31,0xfe,0xb4]
|
||||
|
||||
s_cmpk_lg_u32 exec_hi, 0x3141
|
||||
// CHECK: [0x41,0x31,0xff,0xb4]
|
||||
|
||||
s_cmpk_lg_u32 s1, 0xc1d1
|
||||
// CHECK: [0xd1,0xc1,0x81,0xb4]
|
||||
|
||||
s_cmpk_gt_u32 s1, 0x3141
|
||||
// CHECK: [0x41,0x31,0x01,0xb5]
|
||||
|
||||
s_cmpk_gt_u32 s101, 0x3141
|
||||
// CHECK: [0x41,0x31,0x65,0xb5]
|
||||
|
||||
s_cmpk_gt_u32 flat_scratch_lo, 0x3141
|
||||
// CHECK: [0x41,0x31,0x66,0xb5]
|
||||
|
||||
s_cmpk_gt_u32 flat_scratch_hi, 0x3141
|
||||
// CHECK: [0x41,0x31,0x67,0xb5]
|
||||
|
||||
s_cmpk_gt_u32 vcc_lo, 0x3141
|
||||
// CHECK: [0x41,0x31,0x6a,0xb5]
|
||||
|
||||
s_cmpk_gt_u32 vcc_hi, 0x3141
|
||||
// CHECK: [0x41,0x31,0x6b,0xb5]
|
||||
|
||||
s_cmpk_gt_u32 tba_lo, 0x3141
|
||||
// CHECK: [0x41,0x31,0x6c,0xb5]
|
||||
|
||||
s_cmpk_gt_u32 tba_hi, 0x3141
|
||||
// CHECK: [0x41,0x31,0x6d,0xb5]
|
||||
|
||||
s_cmpk_gt_u32 tma_lo, 0x3141
|
||||
// CHECK: [0x41,0x31,0x6e,0xb5]
|
||||
|
||||
s_cmpk_gt_u32 tma_hi, 0x3141
|
||||
// CHECK: [0x41,0x31,0x6f,0xb5]
|
||||
|
||||
s_cmpk_gt_u32 ttmp11, 0x3141
|
||||
// CHECK: [0x41,0x31,0x7b,0xb5]
|
||||
|
||||
s_cmpk_gt_u32 m0, 0x3141
|
||||
// CHECK: [0x41,0x31,0x7c,0xb5]
|
||||
|
||||
s_cmpk_gt_u32 exec_lo, 0x3141
|
||||
// CHECK: [0x41,0x31,0x7e,0xb5]
|
||||
|
||||
s_cmpk_gt_u32 exec_hi, 0x3141
|
||||
// CHECK: [0x41,0x31,0x7f,0xb5]
|
||||
|
||||
s_cmpk_gt_u32 s1, 0xc1d1
|
||||
// CHECK: [0xd1,0xc1,0x01,0xb5]
|
||||
|
||||
s_cmpk_ge_u32 s1, 0x3141
|
||||
// CHECK: [0x41,0x31,0x81,0xb5]
|
||||
|
||||
s_cmpk_ge_u32 s101, 0x3141
|
||||
// CHECK: [0x41,0x31,0xe5,0xb5]
|
||||
|
||||
s_cmpk_ge_u32 flat_scratch_lo, 0x3141
|
||||
// CHECK: [0x41,0x31,0xe6,0xb5]
|
||||
|
||||
s_cmpk_ge_u32 flat_scratch_hi, 0x3141
|
||||
// CHECK: [0x41,0x31,0xe7,0xb5]
|
||||
|
||||
s_cmpk_ge_u32 vcc_lo, 0x3141
|
||||
// CHECK: [0x41,0x31,0xea,0xb5]
|
||||
|
||||
s_cmpk_ge_u32 vcc_hi, 0x3141
|
||||
// CHECK: [0x41,0x31,0xeb,0xb5]
|
||||
|
||||
s_cmpk_ge_u32 tba_lo, 0x3141
|
||||
// CHECK: [0x41,0x31,0xec,0xb5]
|
||||
|
||||
s_cmpk_ge_u32 tba_hi, 0x3141
|
||||
// CHECK: [0x41,0x31,0xed,0xb5]
|
||||
|
||||
s_cmpk_ge_u32 tma_lo, 0x3141
|
||||
// CHECK: [0x41,0x31,0xee,0xb5]
|
||||
|
||||
s_cmpk_ge_u32 tma_hi, 0x3141
|
||||
// CHECK: [0x41,0x31,0xef,0xb5]
|
||||
|
||||
s_cmpk_ge_u32 ttmp11, 0x3141
|
||||
// CHECK: [0x41,0x31,0xfb,0xb5]
|
||||
|
||||
s_cmpk_ge_u32 m0, 0x3141
|
||||
// CHECK: [0x41,0x31,0xfc,0xb5]
|
||||
|
||||
s_cmpk_ge_u32 exec_lo, 0x3141
|
||||
// CHECK: [0x41,0x31,0xfe,0xb5]
|
||||
|
||||
s_cmpk_ge_u32 exec_hi, 0x3141
|
||||
// CHECK: [0x41,0x31,0xff,0xb5]
|
||||
|
||||
s_cmpk_ge_u32 s1, 0xc1d1
|
||||
// CHECK: [0xd1,0xc1,0x81,0xb5]
|
||||
|
||||
s_cmpk_lt_u32 s1, 0x3141
|
||||
// CHECK: [0x41,0x31,0x01,0xb6]
|
||||
|
||||
s_cmpk_lt_u32 s101, 0x3141
|
||||
// CHECK: [0x41,0x31,0x65,0xb6]
|
||||
|
||||
s_cmpk_lt_u32 flat_scratch_lo, 0x3141
|
||||
// CHECK: [0x41,0x31,0x66,0xb6]
|
||||
|
||||
s_cmpk_lt_u32 flat_scratch_hi, 0x3141
|
||||
// CHECK: [0x41,0x31,0x67,0xb6]
|
||||
|
||||
s_cmpk_lt_u32 vcc_lo, 0x3141
|
||||
// CHECK: [0x41,0x31,0x6a,0xb6]
|
||||
|
||||
s_cmpk_lt_u32 vcc_hi, 0x3141
|
||||
// CHECK: [0x41,0x31,0x6b,0xb6]
|
||||
|
||||
s_cmpk_lt_u32 tba_lo, 0x3141
|
||||
// CHECK: [0x41,0x31,0x6c,0xb6]
|
||||
|
||||
s_cmpk_lt_u32 tba_hi, 0x3141
|
||||
// CHECK: [0x41,0x31,0x6d,0xb6]
|
||||
|
||||
s_cmpk_lt_u32 tma_lo, 0x3141
|
||||
// CHECK: [0x41,0x31,0x6e,0xb6]
|
||||
|
||||
s_cmpk_lt_u32 tma_hi, 0x3141
|
||||
// CHECK: [0x41,0x31,0x6f,0xb6]
|
||||
|
||||
s_cmpk_lt_u32 ttmp11, 0x3141
|
||||
// CHECK: [0x41,0x31,0x7b,0xb6]
|
||||
|
||||
s_cmpk_lt_u32 m0, 0x3141
|
||||
// CHECK: [0x41,0x31,0x7c,0xb6]
|
||||
|
||||
s_cmpk_lt_u32 exec_lo, 0x3141
|
||||
// CHECK: [0x41,0x31,0x7e,0xb6]
|
||||
|
||||
s_cmpk_lt_u32 exec_hi, 0x3141
|
||||
// CHECK: [0x41,0x31,0x7f,0xb6]
|
||||
|
||||
s_cmpk_lt_u32 s1, 0xc1d1
|
||||
// CHECK: [0xd1,0xc1,0x01,0xb6]
|
||||
|
||||
s_cmpk_le_u32 s1, 0x3141
|
||||
// CHECK: [0x41,0x31,0x81,0xb6]
|
||||
|
||||
s_cmpk_le_u32 s101, 0x3141
|
||||
// CHECK: [0x41,0x31,0xe5,0xb6]
|
||||
|
||||
s_cmpk_le_u32 flat_scratch_lo, 0x3141
|
||||
// CHECK: [0x41,0x31,0xe6,0xb6]
|
||||
|
||||
s_cmpk_le_u32 flat_scratch_hi, 0x3141
|
||||
// CHECK: [0x41,0x31,0xe7,0xb6]
|
||||
|
||||
s_cmpk_le_u32 vcc_lo, 0x3141
|
||||
// CHECK: [0x41,0x31,0xea,0xb6]
|
||||
|
||||
s_cmpk_le_u32 vcc_hi, 0x3141
|
||||
// CHECK: [0x41,0x31,0xeb,0xb6]
|
||||
|
||||
s_cmpk_le_u32 tba_lo, 0x3141
|
||||
// CHECK: [0x41,0x31,0xec,0xb6]
|
||||
|
||||
s_cmpk_le_u32 tba_hi, 0x3141
|
||||
// CHECK: [0x41,0x31,0xed,0xb6]
|
||||
|
||||
s_cmpk_le_u32 tma_lo, 0x3141
|
||||
// CHECK: [0x41,0x31,0xee,0xb6]
|
||||
|
||||
s_cmpk_le_u32 tma_hi, 0x3141
|
||||
// CHECK: [0x41,0x31,0xef,0xb6]
|
||||
|
||||
s_cmpk_le_u32 ttmp11, 0x3141
|
||||
// CHECK: [0x41,0x31,0xfb,0xb6]
|
||||
|
||||
s_cmpk_le_u32 m0, 0x3141
|
||||
// CHECK: [0x41,0x31,0xfc,0xb6]
|
||||
|
||||
s_cmpk_le_u32 exec_lo, 0x3141
|
||||
// CHECK: [0x41,0x31,0xfe,0xb6]
|
||||
|
||||
s_cmpk_le_u32 exec_hi, 0x3141
|
||||
// CHECK: [0x41,0x31,0xff,0xb6]
|
||||
|
||||
s_cmpk_le_u32 s1, 0xc1d1
|
||||
// CHECK: [0xd1,0xc1,0x81,0xb6]
|
||||
|
||||
s_addk_i32 s5, 0x3141
|
||||
// CHECK: [0x41,0x31,0x05,0xb7]
|
||||
|
||||
s_addk_i32 s101, 0x3141
|
||||
// CHECK: [0x41,0x31,0x65,0xb7]
|
||||
|
||||
s_addk_i32 flat_scratch_lo, 0x3141
|
||||
// CHECK: [0x41,0x31,0x66,0xb7]
|
||||
|
||||
s_addk_i32 flat_scratch_hi, 0x3141
|
||||
// CHECK: [0x41,0x31,0x67,0xb7]
|
||||
|
||||
s_addk_i32 vcc_lo, 0x3141
|
||||
// CHECK: [0x41,0x31,0x6a,0xb7]
|
||||
|
||||
s_addk_i32 vcc_hi, 0x3141
|
||||
// CHECK: [0x41,0x31,0x6b,0xb7]
|
||||
|
||||
s_addk_i32 tba_lo, 0x3141
|
||||
// CHECK: [0x41,0x31,0x6c,0xb7]
|
||||
|
||||
s_addk_i32 tba_hi, 0x3141
|
||||
// CHECK: [0x41,0x31,0x6d,0xb7]
|
||||
|
||||
s_addk_i32 tma_lo, 0x3141
|
||||
// CHECK: [0x41,0x31,0x6e,0xb7]
|
||||
|
||||
s_addk_i32 tma_hi, 0x3141
|
||||
// CHECK: [0x41,0x31,0x6f,0xb7]
|
||||
|
||||
s_addk_i32 ttmp11, 0x3141
|
||||
// CHECK: [0x41,0x31,0x7b,0xb7]
|
||||
|
||||
s_addk_i32 m0, 0x3141
|
||||
// CHECK: [0x41,0x31,0x7c,0xb7]
|
||||
|
||||
s_addk_i32 exec_lo, 0x3141
|
||||
// CHECK: [0x41,0x31,0x7e,0xb7]
|
||||
|
||||
s_addk_i32 exec_hi, 0x3141
|
||||
// CHECK: [0x41,0x31,0x7f,0xb7]
|
||||
|
||||
s_addk_i32 s5, 0xc1d1
|
||||
// CHECK: [0xd1,0xc1,0x05,0xb7]
|
||||
|
||||
s_mulk_i32 s5, 0x3141
|
||||
// CHECK: [0x41,0x31,0x85,0xb7]
|
||||
|
||||
s_mulk_i32 s101, 0x3141
|
||||
// CHECK: [0x41,0x31,0xe5,0xb7]
|
||||
|
||||
s_mulk_i32 flat_scratch_lo, 0x3141
|
||||
// CHECK: [0x41,0x31,0xe6,0xb7]
|
||||
|
||||
s_mulk_i32 flat_scratch_hi, 0x3141
|
||||
// CHECK: [0x41,0x31,0xe7,0xb7]
|
||||
|
||||
s_mulk_i32 vcc_lo, 0x3141
|
||||
// CHECK: [0x41,0x31,0xea,0xb7]
|
||||
|
||||
s_mulk_i32 vcc_hi, 0x3141
|
||||
// CHECK: [0x41,0x31,0xeb,0xb7]
|
||||
|
||||
s_mulk_i32 tba_lo, 0x3141
|
||||
// CHECK: [0x41,0x31,0xec,0xb7]
|
||||
|
||||
s_mulk_i32 tba_hi, 0x3141
|
||||
// CHECK: [0x41,0x31,0xed,0xb7]
|
||||
|
||||
s_mulk_i32 tma_lo, 0x3141
|
||||
// CHECK: [0x41,0x31,0xee,0xb7]
|
||||
|
||||
s_mulk_i32 tma_hi, 0x3141
|
||||
// CHECK: [0x41,0x31,0xef,0xb7]
|
||||
|
||||
s_mulk_i32 ttmp11, 0x3141
|
||||
// CHECK: [0x41,0x31,0xfb,0xb7]
|
||||
|
||||
s_mulk_i32 m0, 0x3141
|
||||
// CHECK: [0x41,0x31,0xfc,0xb7]
|
||||
|
||||
s_mulk_i32 exec_lo, 0x3141
|
||||
// CHECK: [0x41,0x31,0xfe,0xb7]
|
||||
|
||||
s_mulk_i32 exec_hi, 0x3141
|
||||
// CHECK: [0x41,0x31,0xff,0xb7]
|
||||
|
||||
s_mulk_i32 s5, 0xc1d1
|
||||
// CHECK: [0xd1,0xc1,0x85,0xb7]
|
||||
|
||||
s_cbranch_i_fork s[2:3], 12609
|
||||
// CHECK: [0x41,0x31,0x02,0xb8]
|
||||
|
||||
s_cbranch_i_fork s[4:5], 12609
|
||||
// CHECK: [0x41,0x31,0x04,0xb8]
|
||||
|
||||
s_cbranch_i_fork s[100:101], 12609
|
||||
// CHECK: [0x41,0x31,0x64,0xb8]
|
||||
|
||||
s_cbranch_i_fork flat_scratch, 12609
|
||||
// CHECK: [0x41,0x31,0x66,0xb8]
|
||||
|
||||
s_cbranch_i_fork vcc, 12609
|
||||
// CHECK: [0x41,0x31,0x6a,0xb8]
|
||||
|
||||
s_cbranch_i_fork tba, 12609
|
||||
// CHECK: [0x41,0x31,0x6c,0xb8]
|
||||
|
||||
s_cbranch_i_fork tma, 12609
|
||||
// CHECK: [0x41,0x31,0x6e,0xb8]
|
||||
|
||||
s_cbranch_i_fork ttmp[10:11], 12609
|
||||
// CHECK: [0x41,0x31,0x7a,0xb8]
|
||||
|
||||
s_cbranch_i_fork exec, 12609
|
||||
// CHECK: [0x41,0x31,0x7e,0xb8]
|
||||
|
||||
s_cbranch_i_fork s[2:3], 49617
|
||||
// CHECK: [0xd1,0xc1,0x02,0xb8]
|
||||
|
||||
s_getreg_b32 s5, 0x3141
|
||||
// CHECK: [0x41,0x31,0x85,0xb8]
|
||||
|
||||
s_getreg_b32 s101, 0x3141
|
||||
// CHECK: [0x41,0x31,0xe5,0xb8]
|
||||
|
||||
s_getreg_b32 flat_scratch_lo, 0x3141
|
||||
// CHECK: [0x41,0x31,0xe6,0xb8]
|
||||
|
||||
s_getreg_b32 flat_scratch_hi, 0x3141
|
||||
// CHECK: [0x41,0x31,0xe7,0xb8]
|
||||
|
||||
s_getreg_b32 vcc_lo, 0x3141
|
||||
// CHECK: [0x41,0x31,0xea,0xb8]
|
||||
|
||||
s_getreg_b32 vcc_hi, 0x3141
|
||||
// CHECK: [0x41,0x31,0xeb,0xb8]
|
||||
|
||||
s_getreg_b32 tba_lo, 0x3141
|
||||
// CHECK: [0x41,0x31,0xec,0xb8]
|
||||
|
||||
s_getreg_b32 tba_hi, 0x3141
|
||||
// CHECK: [0x41,0x31,0xed,0xb8]
|
||||
|
||||
s_getreg_b32 tma_lo, 0x3141
|
||||
// CHECK: [0x41,0x31,0xee,0xb8]
|
||||
|
||||
s_getreg_b32 tma_hi, 0x3141
|
||||
// CHECK: [0x41,0x31,0xef,0xb8]
|
||||
|
||||
s_getreg_b32 ttmp11, 0x3141
|
||||
// CHECK: [0x41,0x31,0xfb,0xb8]
|
||||
|
||||
s_getreg_b32 m0, 0x3141
|
||||
// CHECK: [0x41,0x31,0xfc,0xb8]
|
||||
|
||||
s_getreg_b32 exec_lo, 0x3141
|
||||
// CHECK: [0x41,0x31,0xfe,0xb8]
|
||||
|
||||
s_getreg_b32 exec_hi, 0x3141
|
||||
// CHECK: [0x41,0x31,0xff,0xb8]
|
||||
|
||||
s_getreg_b32 s5, 0xc1d1
|
||||
// CHECK: [0xd1,0xc1,0x85,0xb8]
|
||||
|
||||
s_setreg_b32 0x3141, s1
|
||||
// CHECK: [0x41,0x31,0x01,0xb9]
|
||||
|
||||
s_setreg_b32 0xc1d1, s1
|
||||
// CHECK: [0xd1,0xc1,0x01,0xb9]
|
||||
|
||||
s_setreg_b32 0x3141, s101
|
||||
// CHECK: [0x41,0x31,0x65,0xb9]
|
||||
|
||||
s_setreg_b32 0x3141, flat_scratch_lo
|
||||
// CHECK: [0x41,0x31,0x66,0xb9]
|
||||
|
||||
s_setreg_b32 0x3141, flat_scratch_hi
|
||||
// CHECK: [0x41,0x31,0x67,0xb9]
|
||||
|
||||
s_setreg_b32 0x3141, vcc_lo
|
||||
// CHECK: [0x41,0x31,0x6a,0xb9]
|
||||
|
||||
s_setreg_b32 0x3141, vcc_hi
|
||||
// CHECK: [0x41,0x31,0x6b,0xb9]
|
||||
|
||||
s_setreg_b32 0x3141, tba_lo
|
||||
// CHECK: [0x41,0x31,0x6c,0xb9]
|
||||
|
||||
s_setreg_b32 0x3141, tba_hi
|
||||
// CHECK: [0x41,0x31,0x6d,0xb9]
|
||||
|
||||
s_setreg_b32 0x3141, tma_lo
|
||||
// CHECK: [0x41,0x31,0x6e,0xb9]
|
||||
|
||||
s_setreg_b32 0x3141, tma_hi
|
||||
// CHECK: [0x41,0x31,0x6f,0xb9]
|
||||
|
||||
s_setreg_b32 0x3141, ttmp11
|
||||
// CHECK: [0x41,0x31,0x7b,0xb9]
|
||||
|
||||
s_setreg_b32 0x3141, m0
|
||||
// CHECK: [0x41,0x31,0x7c,0xb9]
|
||||
|
||||
s_setreg_b32 0x3141, exec_lo
|
||||
// CHECK: [0x41,0x31,0x7e,0xb9]
|
||||
|
||||
s_setreg_b32 0x3141, exec_hi
|
||||
// CHECK: [0x41,0x31,0x7f,0xb9]
|
||||
|
||||
s_setreg_imm32_b32 0x3141, 0x11213141
|
||||
// CHECK: [0x41,0x31,0x00,0xba,0x41,0x31,0x21,0x11]
|
||||
|
||||
s_setreg_imm32_b32 0xc1d1, 0x11213141
|
||||
// CHECK: [0xd1,0xc1,0x00,0xba,0x41,0x31,0x21,0x11]
|
||||
|
||||
s_setreg_imm32_b32 0x3141, 0xa1b1c1d1
|
||||
// CHECK: [0x41,0x31,0x00,0xba,0xd1,0xc1,0xb1,0xa1]
|
||||
|
|
@ -0,0 +1,163 @@
|
|||
// RUN: llvm-mc -arch=amdgcn -mcpu=tonga -show-encoding %s | FileCheck %s
|
||||
|
||||
s_nop 0x3141
|
||||
// CHECK: [0x41,0x31,0x80,0xbf]
|
||||
|
||||
s_nop 0xc1d1
|
||||
// CHECK: [0xd1,0xc1,0x80,0xbf]
|
||||
|
||||
s_endpgm
|
||||
// CHECK: [0x00,0x00,0x81,0xbf]
|
||||
|
||||
s_branch 12609
|
||||
// CHECK: [0x41,0x31,0x82,0xbf]
|
||||
|
||||
s_branch 49617
|
||||
// CHECK: [0xd1,0xc1,0x82,0xbf]
|
||||
|
||||
s_wakeup
|
||||
// CHECK: [0x00,0x00,0x83,0xbf]
|
||||
|
||||
s_cbranch_scc0 12609
|
||||
// CHECK: [0x41,0x31,0x84,0xbf]
|
||||
|
||||
s_cbranch_scc0 49617
|
||||
// CHECK: [0xd1,0xc1,0x84,0xbf]
|
||||
|
||||
s_cbranch_scc1 12609
|
||||
// CHECK: [0x41,0x31,0x85,0xbf]
|
||||
|
||||
s_cbranch_scc1 49617
|
||||
// CHECK: [0xd1,0xc1,0x85,0xbf]
|
||||
|
||||
s_cbranch_vccz 12609
|
||||
// CHECK: [0x41,0x31,0x86,0xbf]
|
||||
|
||||
s_cbranch_vccz 49617
|
||||
// CHECK: [0xd1,0xc1,0x86,0xbf]
|
||||
|
||||
s_cbranch_vccnz 12609
|
||||
// CHECK: [0x41,0x31,0x87,0xbf]
|
||||
|
||||
s_cbranch_vccnz 49617
|
||||
// CHECK: [0xd1,0xc1,0x87,0xbf]
|
||||
|
||||
s_cbranch_execz 12609
|
||||
// CHECK: [0x41,0x31,0x88,0xbf]
|
||||
|
||||
s_cbranch_execz 49617
|
||||
// CHECK: [0xd1,0xc1,0x88,0xbf]
|
||||
|
||||
s_cbranch_execnz 12609
|
||||
// CHECK: [0x41,0x31,0x89,0xbf]
|
||||
|
||||
s_cbranch_execnz 49617
|
||||
// CHECK: [0xd1,0xc1,0x89,0xbf]
|
||||
|
||||
s_barrier
|
||||
// CHECK: [0x00,0x00,0x8a,0xbf]
|
||||
|
||||
s_setkill 0x3141
|
||||
// CHECK: [0x41,0x31,0x8b,0xbf]
|
||||
|
||||
s_setkill 0xc1d1
|
||||
// CHECK: [0xd1,0xc1,0x8b,0xbf]
|
||||
|
||||
s_waitcnt 0x3141
|
||||
// CHECK: [0x41,0x31,0x8c,0xbf]
|
||||
|
||||
s_waitcnt 0xc1d1
|
||||
// CHECK: [0xd1,0xc1,0x8c,0xbf]
|
||||
|
||||
s_sethalt 0x3141
|
||||
// CHECK: [0x41,0x31,0x8d,0xbf]
|
||||
|
||||
s_sethalt 0xc1d1
|
||||
// CHECK: [0xd1,0xc1,0x8d,0xbf]
|
||||
|
||||
s_sleep 0x3141
|
||||
// CHECK: [0x41,0x31,0x8e,0xbf]
|
||||
|
||||
s_sleep 0xc1d1
|
||||
// CHECK: [0xd1,0xc1,0x8e,0xbf]
|
||||
|
||||
s_setprio 0x3141
|
||||
// CHECK: [0x41,0x31,0x8f,0xbf]
|
||||
|
||||
s_setprio 0xc1d1
|
||||
// CHECK: [0xd1,0xc1,0x8f,0xbf]
|
||||
|
||||
s_sendmsg 0x3141
|
||||
// CHECK: [0x41,0x31,0x90,0xbf]
|
||||
|
||||
s_sendmsg 0xc1d1
|
||||
// CHECK: [0xd1,0xc1,0x90,0xbf]
|
||||
|
||||
s_sendmsghalt 0x3141
|
||||
// CHECK: [0x41,0x31,0x91,0xbf]
|
||||
|
||||
s_sendmsghalt 0xc1d1
|
||||
// CHECK: [0xd1,0xc1,0x91,0xbf]
|
||||
|
||||
s_trap 0x3141
|
||||
// CHECK: [0x41,0x31,0x92,0xbf]
|
||||
|
||||
s_trap 0xc1d1
|
||||
// CHECK: [0xd1,0xc1,0x92,0xbf]
|
||||
|
||||
s_icache_inv
|
||||
// CHECK: [0x00,0x00,0x93,0xbf]
|
||||
|
||||
s_incperflevel 0x3141
|
||||
// CHECK: [0x41,0x31,0x94,0xbf]
|
||||
|
||||
s_incperflevel 0xc1d1
|
||||
// CHECK: [0xd1,0xc1,0x94,0xbf]
|
||||
|
||||
s_decperflevel 0x3141
|
||||
// CHECK: [0x41,0x31,0x95,0xbf]
|
||||
|
||||
s_decperflevel 0xc1d1
|
||||
// CHECK: [0xd1,0xc1,0x95,0xbf]
|
||||
|
||||
s_ttracedata
|
||||
// CHECK: [0x00,0x00,0x96,0xbf]
|
||||
|
||||
s_cbranch_cdbgsys 12609
|
||||
// CHECK: [0x41,0x31,0x97,0xbf]
|
||||
|
||||
s_cbranch_cdbgsys 49617
|
||||
// CHECK: [0xd1,0xc1,0x97,0xbf]
|
||||
|
||||
s_cbranch_cdbguser 12609
|
||||
// CHECK: [0x41,0x31,0x98,0xbf]
|
||||
|
||||
s_cbranch_cdbguser 49617
|
||||
// CHECK: [0xd1,0xc1,0x98,0xbf]
|
||||
|
||||
s_cbranch_cdbgsys_or_user 12609
|
||||
// CHECK: [0x41,0x31,0x99,0xbf]
|
||||
|
||||
s_cbranch_cdbgsys_or_user 49617
|
||||
// CHECK: [0xd1,0xc1,0x99,0xbf]
|
||||
|
||||
s_cbranch_cdbgsys_and_user 12609
|
||||
// CHECK: [0x41,0x31,0x9a,0xbf]
|
||||
|
||||
s_cbranch_cdbgsys_and_user 49617
|
||||
// CHECK: [0xd1,0xc1,0x9a,0xbf]
|
||||
|
||||
s_endpgm_saved
|
||||
// CHECK: [0x00,0x00,0x9b,0xbf]
|
||||
|
||||
s_set_gpr_idx_off
|
||||
// CHECK: [0x00,0x00,0x9c,0xbf]
|
||||
|
||||
s_set_gpr_idx_mode 0x0
|
||||
// CHECK: [0x00,0x00,0x9d,0xbf]
|
||||
|
||||
s_set_gpr_idx_mode 0x1
|
||||
// CHECK: [0x01,0x00,0x9d,0xbf]
|
||||
|
||||
s_set_gpr_idx_mode 0xF
|
||||
// CHECK: [0x0f,0x00,0x9d,0xbf]
|
||||
|
|
@ -0,0 +1,85 @@
|
|||
// RUN: llvm-mc -arch=amdgcn -mcpu=tonga -show-encoding %s | FileCheck %s
|
||||
|
||||
v_interp_p1_f32 v5, v1, attr0.x
|
||||
// CHECK: [0x01,0x00,0x14,0xd4]
|
||||
|
||||
v_interp_p1_f32 v255, v1, attr0.x
|
||||
// CHECK: [0x01,0x00,0xfc,0xd7]
|
||||
|
||||
v_interp_p1_f32 v5, v255, attr0.x
|
||||
// CHECK: [0xff,0x00,0x14,0xd4]
|
||||
|
||||
v_interp_p1_f32 v5, v1, attr1.x
|
||||
// CHECK: [0x01,0x04,0x14,0xd4]
|
||||
|
||||
v_interp_p1_f32 v5, v1, attr31.x
|
||||
// CHECK: [0x01,0x7c,0x14,0xd4]
|
||||
|
||||
v_interp_p1_f32 v5, v1, attr32.x
|
||||
// CHECK: [0x01,0x80,0x14,0xd4]
|
||||
|
||||
v_interp_p1_f32 v5, v1, attr0.y
|
||||
// CHECK: [0x01,0x01,0x14,0xd4]
|
||||
|
||||
v_interp_p1_f32 v5, v1, attr0.z
|
||||
// CHECK: [0x01,0x02,0x14,0xd4]
|
||||
|
||||
v_interp_p1_f32 v5, v1, attr0.w
|
||||
// CHECK: [0x01,0x03,0x14,0xd4]
|
||||
|
||||
v_interp_p2_f32 v5, v1, attr0.x
|
||||
// CHECK: [0x01,0x00,0x15,0xd4]
|
||||
|
||||
v_interp_p2_f32 v255, v1, attr0.x
|
||||
// CHECK: [0x01,0x00,0xfd,0xd7]
|
||||
|
||||
v_interp_p2_f32 v5, v255, attr0.x
|
||||
// CHECK: [0xff,0x00,0x15,0xd4]
|
||||
|
||||
v_interp_p2_f32 v5, v1, attr1.x
|
||||
// CHECK: [0x01,0x04,0x15,0xd4]
|
||||
|
||||
v_interp_p2_f32 v5, v1, attr31.x
|
||||
// CHECK: [0x01,0x7c,0x15,0xd4]
|
||||
|
||||
v_interp_p2_f32 v5, v1, attr32.x
|
||||
// CHECK: [0x01,0x80,0x15,0xd4]
|
||||
|
||||
v_interp_p2_f32 v5, v1, attr0.y
|
||||
// CHECK: [0x01,0x01,0x15,0xd4]
|
||||
|
||||
v_interp_p2_f32 v5, v1, attr0.z
|
||||
// CHECK: [0x01,0x02,0x15,0xd4]
|
||||
|
||||
v_interp_p2_f32 v5, v1, attr0.w
|
||||
// CHECK: [0x01,0x03,0x15,0xd4]
|
||||
|
||||
v_interp_mov_f32 v5, p10, attr0.x
|
||||
// CHECK: [0x00,0x00,0x16,0xd4]
|
||||
|
||||
v_interp_mov_f32 v255, p10, attr0.x
|
||||
// CHECK: [0x00,0x00,0xfe,0xd7]
|
||||
|
||||
v_interp_mov_f32 v5, p20, attr0.x
|
||||
// CHECK: [0x01,0x00,0x16,0xd4]
|
||||
|
||||
v_interp_mov_f32 v5, p0, attr0.x
|
||||
// CHECK: [0x02,0x00,0x16,0xd4]
|
||||
|
||||
v_interp_mov_f32 v5, p10, attr1.x
|
||||
// CHECK: [0x00,0x04,0x16,0xd4]
|
||||
|
||||
v_interp_mov_f32 v5, p10, attr31.x
|
||||
// CHECK: [0x00,0x7c,0x16,0xd4]
|
||||
|
||||
v_interp_mov_f32 v5, p10, attr32.x
|
||||
// CHECK: [0x00,0x80,0x16,0xd4]
|
||||
|
||||
v_interp_mov_f32 v5, p10, attr0.y
|
||||
// CHECK: [0x00,0x01,0x16,0xd4]
|
||||
|
||||
v_interp_mov_f32 v5, p10, attr0.z
|
||||
// CHECK: [0x00,0x02,0x16,0xd4]
|
||||
|
||||
v_interp_mov_f32 v5, p10, attr0.w
|
||||
// CHECK: [0x00,0x03,0x16,0xd4]
|
||||
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
|
|
@ -0,0 +1,82 @@
|
|||
// RUN: llvm-mc -arch=amdgcn -mcpu=gfx900 -show-encoding %s | FileCheck %s
|
||||
|
||||
exp mrt0 v0, v0, v0, v0
|
||||
// CHECK: [0x0f,0x00,0x00,0xc4,0x00,0x00,0x00,0x00]
|
||||
|
||||
exp mrtz v0, v0, v0, v0
|
||||
// CHECK: [0x8f,0x00,0x00,0xc4,0x00,0x00,0x00,0x00]
|
||||
|
||||
exp null v0, v0, v0, v0
|
||||
// CHECK: [0x9f,0x00,0x00,0xc4,0x00,0x00,0x00,0x00]
|
||||
|
||||
exp pos0 v0, v0, v0, v0
|
||||
// CHECK: [0xcf,0x00,0x00,0xc4,0x00,0x00,0x00,0x00]
|
||||
|
||||
exp param0 v0, v0, v0, v0
|
||||
// CHECK: [0x0f,0x02,0x00,0xc4,0x00,0x00,0x00,0x00]
|
||||
|
||||
exp mrt0 v255, v0, v0, v0
|
||||
// CHECK: [0x0f,0x00,0x00,0xc4,0xff,0x00,0x00,0x00]
|
||||
|
||||
exp mrt0 v0, v255, v0, v0
|
||||
// CHECK: [0x0f,0x00,0x00,0xc4,0x00,0xff,0x00,0x00]
|
||||
|
||||
exp mrt0 v0, v0, v255, v0
|
||||
// CHECK: [0x0f,0x00,0x00,0xc4,0x00,0x00,0xff,0x00]
|
||||
|
||||
exp mrt0 v0, v0, v0, v255
|
||||
// CHECK: [0x0f,0x00,0x00,0xc4,0x00,0x00,0x00,0xff]
|
||||
|
||||
exp mrt0 v0, off, off, off
|
||||
// CHECK: [0x01,0x00,0x00,0xc4,0x00,0x00,0x00,0x00]
|
||||
|
||||
exp mrt0 off, v0, off, off
|
||||
// CHECK: [0x02,0x00,0x00,0xc4,0x00,0x00,0x00,0x00]
|
||||
|
||||
exp mrt0 v0, v0, off, off
|
||||
// CHECK: [0x03,0x00,0x00,0xc4,0x00,0x00,0x00,0x00]
|
||||
|
||||
exp mrt0 off, off, v0, off
|
||||
// CHECK: [0x04,0x00,0x00,0xc4,0x00,0x00,0x00,0x00]
|
||||
|
||||
exp mrt0 v0, off, v0, off
|
||||
// CHECK: [0x05,0x00,0x00,0xc4,0x00,0x00,0x00,0x00]
|
||||
|
||||
exp mrt0 off, v0, v0, off
|
||||
// CHECK: [0x06,0x00,0x00,0xc4,0x00,0x00,0x00,0x00]
|
||||
|
||||
exp mrt0 v0, v0, v0, off
|
||||
// CHECK: [0x07,0x00,0x00,0xc4,0x00,0x00,0x00,0x00]
|
||||
|
||||
exp mrt0 off, off, off, v0
|
||||
// CHECK: [0x08,0x00,0x00,0xc4,0x00,0x00,0x00,0x00]
|
||||
|
||||
exp mrt0 v0, off, off, v0
|
||||
// CHECK: [0x09,0x00,0x00,0xc4,0x00,0x00,0x00,0x00]
|
||||
|
||||
exp mrt0 off, v0, off, v0
|
||||
// CHECK: [0x0a,0x00,0x00,0xc4,0x00,0x00,0x00,0x00]
|
||||
|
||||
exp mrt0 v0, v0, off, v0
|
||||
// CHECK: [0x0b,0x00,0x00,0xc4,0x00,0x00,0x00,0x00]
|
||||
|
||||
exp mrt0 off, off, v0, v0
|
||||
// CHECK: [0x0c,0x00,0x00,0xc4,0x00,0x00,0x00,0x00]
|
||||
|
||||
exp mrt0 v0, off, v0, v0
|
||||
// CHECK: [0x0d,0x00,0x00,0xc4,0x00,0x00,0x00,0x00]
|
||||
|
||||
exp mrt0 off, v0, v0, v0
|
||||
// CHECK: [0x0e,0x00,0x00,0xc4,0x00,0x00,0x00,0x00]
|
||||
|
||||
exp mrt0 off, off, off, off
|
||||
// CHECK: [0x00,0x00,0x00,0xc4,0x00,0x00,0x00,0x00]
|
||||
|
||||
exp mrt0 v0, v0, v0, v0 done
|
||||
// CHECK: [0x0f,0x08,0x00,0xc4,0x00,0x00,0x00,0x00]
|
||||
|
||||
exp mrt0 v0, v0, v0, v0 compr
|
||||
// CHECK: [0x0f,0x04,0x00,0xc4,0x00,0x00,0x00,0x00]
|
||||
|
||||
exp mrt0 v0, v0, v0, v0 vm
|
||||
// CHECK: [0x0f,0x10,0x00,0xc4,0x00,0x00,0x00,0x00]
|
||||
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
|
|
@ -0,0 +1,652 @@
|
|||
// RUN: llvm-mc -arch=amdgcn -mcpu=gfx900 -show-encoding %s | FileCheck %s
|
||||
|
||||
s_movk_i32 s5, 0x3141
|
||||
// CHECK: [0x41,0x31,0x05,0xb0]
|
||||
|
||||
s_movk_i32 s101, 0x3141
|
||||
// CHECK: [0x41,0x31,0x65,0xb0]
|
||||
|
||||
s_movk_i32 flat_scratch_lo, 0x3141
|
||||
// CHECK: [0x41,0x31,0x66,0xb0]
|
||||
|
||||
s_movk_i32 flat_scratch_hi, 0x3141
|
||||
// CHECK: [0x41,0x31,0x67,0xb0]
|
||||
|
||||
s_movk_i32 vcc_lo, 0x3141
|
||||
// CHECK: [0x41,0x31,0x6a,0xb0]
|
||||
|
||||
s_movk_i32 vcc_hi, 0x3141
|
||||
// CHECK: [0x41,0x31,0x6b,0xb0]
|
||||
|
||||
s_movk_i32 ttmp15, 0x3141
|
||||
// CHECK: [0x41,0x31,0x7b,0xb0]
|
||||
|
||||
s_movk_i32 m0, 0x3141
|
||||
// CHECK: [0x41,0x31,0x7c,0xb0]
|
||||
|
||||
s_movk_i32 exec_lo, 0x3141
|
||||
// CHECK: [0x41,0x31,0x7e,0xb0]
|
||||
|
||||
s_movk_i32 exec_hi, 0x3141
|
||||
// CHECK: [0x41,0x31,0x7f,0xb0]
|
||||
|
||||
s_movk_i32 s5, 0xc1d1
|
||||
// CHECK: [0xd1,0xc1,0x05,0xb0]
|
||||
|
||||
s_cmovk_i32 s5, 0x3141
|
||||
// CHECK: [0x41,0x31,0x85,0xb0]
|
||||
|
||||
s_cmovk_i32 s101, 0x3141
|
||||
// CHECK: [0x41,0x31,0xe5,0xb0]
|
||||
|
||||
s_cmovk_i32 flat_scratch_lo, 0x3141
|
||||
// CHECK: [0x41,0x31,0xe6,0xb0]
|
||||
|
||||
s_cmovk_i32 flat_scratch_hi, 0x3141
|
||||
// CHECK: [0x41,0x31,0xe7,0xb0]
|
||||
|
||||
s_cmovk_i32 vcc_lo, 0x3141
|
||||
// CHECK: [0x41,0x31,0xea,0xb0]
|
||||
|
||||
s_cmovk_i32 vcc_hi, 0x3141
|
||||
// CHECK: [0x41,0x31,0xeb,0xb0]
|
||||
|
||||
s_cmovk_i32 ttmp15, 0x3141
|
||||
// CHECK: [0x41,0x31,0xfb,0xb0]
|
||||
|
||||
s_cmovk_i32 m0, 0x3141
|
||||
// CHECK: [0x41,0x31,0xfc,0xb0]
|
||||
|
||||
s_cmovk_i32 exec_lo, 0x3141
|
||||
// CHECK: [0x41,0x31,0xfe,0xb0]
|
||||
|
||||
s_cmovk_i32 exec_hi, 0x3141
|
||||
// CHECK: [0x41,0x31,0xff,0xb0]
|
||||
|
||||
s_cmovk_i32 s5, 0xc1d1
|
||||
// CHECK: [0xd1,0xc1,0x85,0xb0]
|
||||
|
||||
s_cmpk_eq_i32 s1, 0x3141
|
||||
// CHECK: [0x41,0x31,0x01,0xb1]
|
||||
|
||||
s_cmpk_eq_i32 s101, 0x3141
|
||||
// CHECK: [0x41,0x31,0x65,0xb1]
|
||||
|
||||
s_cmpk_eq_i32 flat_scratch_lo, 0x3141
|
||||
// CHECK: [0x41,0x31,0x66,0xb1]
|
||||
|
||||
s_cmpk_eq_i32 flat_scratch_hi, 0x3141
|
||||
// CHECK: [0x41,0x31,0x67,0xb1]
|
||||
|
||||
s_cmpk_eq_i32 vcc_lo, 0x3141
|
||||
// CHECK: [0x41,0x31,0x6a,0xb1]
|
||||
|
||||
s_cmpk_eq_i32 vcc_hi, 0x3141
|
||||
// CHECK: [0x41,0x31,0x6b,0xb1]
|
||||
|
||||
s_cmpk_eq_i32 ttmp15, 0x3141
|
||||
// CHECK: [0x41,0x31,0x7b,0xb1]
|
||||
|
||||
s_cmpk_eq_i32 m0, 0x3141
|
||||
// CHECK: [0x41,0x31,0x7c,0xb1]
|
||||
|
||||
s_cmpk_eq_i32 exec_lo, 0x3141
|
||||
// CHECK: [0x41,0x31,0x7e,0xb1]
|
||||
|
||||
s_cmpk_eq_i32 exec_hi, 0x3141
|
||||
// CHECK: [0x41,0x31,0x7f,0xb1]
|
||||
|
||||
s_cmpk_eq_i32 s1, 0xc1d1
|
||||
// CHECK: [0xd1,0xc1,0x01,0xb1]
|
||||
|
||||
s_cmpk_lg_i32 s1, 0x3141
|
||||
// CHECK: [0x41,0x31,0x81,0xb1]
|
||||
|
||||
s_cmpk_lg_i32 s101, 0x3141
|
||||
// CHECK: [0x41,0x31,0xe5,0xb1]
|
||||
|
||||
s_cmpk_lg_i32 flat_scratch_lo, 0x3141
|
||||
// CHECK: [0x41,0x31,0xe6,0xb1]
|
||||
|
||||
s_cmpk_lg_i32 flat_scratch_hi, 0x3141
|
||||
// CHECK: [0x41,0x31,0xe7,0xb1]
|
||||
|
||||
s_cmpk_lg_i32 vcc_lo, 0x3141
|
||||
// CHECK: [0x41,0x31,0xea,0xb1]
|
||||
|
||||
s_cmpk_lg_i32 vcc_hi, 0x3141
|
||||
// CHECK: [0x41,0x31,0xeb,0xb1]
|
||||
|
||||
s_cmpk_lg_i32 ttmp15, 0x3141
|
||||
// CHECK: [0x41,0x31,0xfb,0xb1]
|
||||
|
||||
s_cmpk_lg_i32 m0, 0x3141
|
||||
// CHECK: [0x41,0x31,0xfc,0xb1]
|
||||
|
||||
s_cmpk_lg_i32 exec_lo, 0x3141
|
||||
// CHECK: [0x41,0x31,0xfe,0xb1]
|
||||
|
||||
s_cmpk_lg_i32 exec_hi, 0x3141
|
||||
// CHECK: [0x41,0x31,0xff,0xb1]
|
||||
|
||||
s_cmpk_lg_i32 s1, 0xc1d1
|
||||
// CHECK: [0xd1,0xc1,0x81,0xb1]
|
||||
|
||||
s_cmpk_gt_i32 s1, 0x3141
|
||||
// CHECK: [0x41,0x31,0x01,0xb2]
|
||||
|
||||
s_cmpk_gt_i32 s101, 0x3141
|
||||
// CHECK: [0x41,0x31,0x65,0xb2]
|
||||
|
||||
s_cmpk_gt_i32 flat_scratch_lo, 0x3141
|
||||
// CHECK: [0x41,0x31,0x66,0xb2]
|
||||
|
||||
s_cmpk_gt_i32 flat_scratch_hi, 0x3141
|
||||
// CHECK: [0x41,0x31,0x67,0xb2]
|
||||
|
||||
s_cmpk_gt_i32 vcc_lo, 0x3141
|
||||
// CHECK: [0x41,0x31,0x6a,0xb2]
|
||||
|
||||
s_cmpk_gt_i32 vcc_hi, 0x3141
|
||||
// CHECK: [0x41,0x31,0x6b,0xb2]
|
||||
|
||||
s_cmpk_gt_i32 ttmp15, 0x3141
|
||||
// CHECK: [0x41,0x31,0x7b,0xb2]
|
||||
|
||||
s_cmpk_gt_i32 m0, 0x3141
|
||||
// CHECK: [0x41,0x31,0x7c,0xb2]
|
||||
|
||||
s_cmpk_gt_i32 exec_lo, 0x3141
|
||||
// CHECK: [0x41,0x31,0x7e,0xb2]
|
||||
|
||||
s_cmpk_gt_i32 exec_hi, 0x3141
|
||||
// CHECK: [0x41,0x31,0x7f,0xb2]
|
||||
|
||||
s_cmpk_gt_i32 s1, 0xc1d1
|
||||
// CHECK: [0xd1,0xc1,0x01,0xb2]
|
||||
|
||||
s_cmpk_ge_i32 s1, 0x3141
|
||||
// CHECK: [0x41,0x31,0x81,0xb2]
|
||||
|
||||
s_cmpk_ge_i32 s101, 0x3141
|
||||
// CHECK: [0x41,0x31,0xe5,0xb2]
|
||||
|
||||
s_cmpk_ge_i32 flat_scratch_lo, 0x3141
|
||||
// CHECK: [0x41,0x31,0xe6,0xb2]
|
||||
|
||||
s_cmpk_ge_i32 flat_scratch_hi, 0x3141
|
||||
// CHECK: [0x41,0x31,0xe7,0xb2]
|
||||
|
||||
s_cmpk_ge_i32 vcc_lo, 0x3141
|
||||
// CHECK: [0x41,0x31,0xea,0xb2]
|
||||
|
||||
s_cmpk_ge_i32 vcc_hi, 0x3141
|
||||
// CHECK: [0x41,0x31,0xeb,0xb2]
|
||||
|
||||
s_cmpk_ge_i32 ttmp15, 0x3141
|
||||
// CHECK: [0x41,0x31,0xfb,0xb2]
|
||||
|
||||
s_cmpk_ge_i32 m0, 0x3141
|
||||
// CHECK: [0x41,0x31,0xfc,0xb2]
|
||||
|
||||
s_cmpk_ge_i32 exec_lo, 0x3141
|
||||
// CHECK: [0x41,0x31,0xfe,0xb2]
|
||||
|
||||
s_cmpk_ge_i32 exec_hi, 0x3141
|
||||
// CHECK: [0x41,0x31,0xff,0xb2]
|
||||
|
||||
s_cmpk_ge_i32 s1, 0xc1d1
|
||||
// CHECK: [0xd1,0xc1,0x81,0xb2]
|
||||
|
||||
s_cmpk_lt_i32 s1, 0x3141
|
||||
// CHECK: [0x41,0x31,0x01,0xb3]
|
||||
|
||||
s_cmpk_lt_i32 s101, 0x3141
|
||||
// CHECK: [0x41,0x31,0x65,0xb3]
|
||||
|
||||
s_cmpk_lt_i32 flat_scratch_lo, 0x3141
|
||||
// CHECK: [0x41,0x31,0x66,0xb3]
|
||||
|
||||
s_cmpk_lt_i32 flat_scratch_hi, 0x3141
|
||||
// CHECK: [0x41,0x31,0x67,0xb3]
|
||||
|
||||
s_cmpk_lt_i32 vcc_lo, 0x3141
|
||||
// CHECK: [0x41,0x31,0x6a,0xb3]
|
||||
|
||||
s_cmpk_lt_i32 vcc_hi, 0x3141
|
||||
// CHECK: [0x41,0x31,0x6b,0xb3]
|
||||
|
||||
s_cmpk_lt_i32 ttmp15, 0x3141
|
||||
// CHECK: [0x41,0x31,0x7b,0xb3]
|
||||
|
||||
s_cmpk_lt_i32 m0, 0x3141
|
||||
// CHECK: [0x41,0x31,0x7c,0xb3]
|
||||
|
||||
s_cmpk_lt_i32 exec_lo, 0x3141
|
||||
// CHECK: [0x41,0x31,0x7e,0xb3]
|
||||
|
||||
s_cmpk_lt_i32 exec_hi, 0x3141
|
||||
// CHECK: [0x41,0x31,0x7f,0xb3]
|
||||
|
||||
s_cmpk_lt_i32 s1, 0xc1d1
|
||||
// CHECK: [0xd1,0xc1,0x01,0xb3]
|
||||
|
||||
s_cmpk_le_i32 s1, 0x3141
|
||||
// CHECK: [0x41,0x31,0x81,0xb3]
|
||||
|
||||
s_cmpk_le_i32 s101, 0x3141
|
||||
// CHECK: [0x41,0x31,0xe5,0xb3]
|
||||
|
||||
s_cmpk_le_i32 flat_scratch_lo, 0x3141
|
||||
// CHECK: [0x41,0x31,0xe6,0xb3]
|
||||
|
||||
s_cmpk_le_i32 flat_scratch_hi, 0x3141
|
||||
// CHECK: [0x41,0x31,0xe7,0xb3]
|
||||
|
||||
s_cmpk_le_i32 vcc_lo, 0x3141
|
||||
// CHECK: [0x41,0x31,0xea,0xb3]
|
||||
|
||||
s_cmpk_le_i32 vcc_hi, 0x3141
|
||||
// CHECK: [0x41,0x31,0xeb,0xb3]
|
||||
|
||||
s_cmpk_le_i32 ttmp15, 0x3141
|
||||
// CHECK: [0x41,0x31,0xfb,0xb3]
|
||||
|
||||
s_cmpk_le_i32 m0, 0x3141
|
||||
// CHECK: [0x41,0x31,0xfc,0xb3]
|
||||
|
||||
s_cmpk_le_i32 exec_lo, 0x3141
|
||||
// CHECK: [0x41,0x31,0xfe,0xb3]
|
||||
|
||||
s_cmpk_le_i32 exec_hi, 0x3141
|
||||
// CHECK: [0x41,0x31,0xff,0xb3]
|
||||
|
||||
s_cmpk_le_i32 s1, 0xc1d1
|
||||
// CHECK: [0xd1,0xc1,0x81,0xb3]
|
||||
|
||||
s_cmpk_eq_u32 s1, 0x3141
|
||||
// CHECK: [0x41,0x31,0x01,0xb4]
|
||||
|
||||
s_cmpk_eq_u32 s101, 0x3141
|
||||
// CHECK: [0x41,0x31,0x65,0xb4]
|
||||
|
||||
s_cmpk_eq_u32 flat_scratch_lo, 0x3141
|
||||
// CHECK: [0x41,0x31,0x66,0xb4]
|
||||
|
||||
s_cmpk_eq_u32 flat_scratch_hi, 0x3141
|
||||
// CHECK: [0x41,0x31,0x67,0xb4]
|
||||
|
||||
s_cmpk_eq_u32 vcc_lo, 0x3141
|
||||
// CHECK: [0x41,0x31,0x6a,0xb4]
|
||||
|
||||
s_cmpk_eq_u32 vcc_hi, 0x3141
|
||||
// CHECK: [0x41,0x31,0x6b,0xb4]
|
||||
|
||||
s_cmpk_eq_u32 ttmp15, 0x3141
|
||||
// CHECK: [0x41,0x31,0x7b,0xb4]
|
||||
|
||||
s_cmpk_eq_u32 m0, 0x3141
|
||||
// CHECK: [0x41,0x31,0x7c,0xb4]
|
||||
|
||||
s_cmpk_eq_u32 exec_lo, 0x3141
|
||||
// CHECK: [0x41,0x31,0x7e,0xb4]
|
||||
|
||||
s_cmpk_eq_u32 exec_hi, 0x3141
|
||||
// CHECK: [0x41,0x31,0x7f,0xb4]
|
||||
|
||||
s_cmpk_eq_u32 s1, 0xc1d1
|
||||
// CHECK: [0xd1,0xc1,0x01,0xb4]
|
||||
|
||||
s_cmpk_lg_u32 s1, 0x3141
|
||||
// CHECK: [0x41,0x31,0x81,0xb4]
|
||||
|
||||
s_cmpk_lg_u32 s101, 0x3141
|
||||
// CHECK: [0x41,0x31,0xe5,0xb4]
|
||||
|
||||
s_cmpk_lg_u32 flat_scratch_lo, 0x3141
|
||||
// CHECK: [0x41,0x31,0xe6,0xb4]
|
||||
|
||||
s_cmpk_lg_u32 flat_scratch_hi, 0x3141
|
||||
// CHECK: [0x41,0x31,0xe7,0xb4]
|
||||
|
||||
s_cmpk_lg_u32 vcc_lo, 0x3141
|
||||
// CHECK: [0x41,0x31,0xea,0xb4]
|
||||
|
||||
s_cmpk_lg_u32 vcc_hi, 0x3141
|
||||
// CHECK: [0x41,0x31,0xeb,0xb4]
|
||||
|
||||
s_cmpk_lg_u32 ttmp15, 0x3141
|
||||
// CHECK: [0x41,0x31,0xfb,0xb4]
|
||||
|
||||
s_cmpk_lg_u32 m0, 0x3141
|
||||
// CHECK: [0x41,0x31,0xfc,0xb4]
|
||||
|
||||
s_cmpk_lg_u32 exec_lo, 0x3141
|
||||
// CHECK: [0x41,0x31,0xfe,0xb4]
|
||||
|
||||
s_cmpk_lg_u32 exec_hi, 0x3141
|
||||
// CHECK: [0x41,0x31,0xff,0xb4]
|
||||
|
||||
s_cmpk_lg_u32 s1, 0xc1d1
|
||||
// CHECK: [0xd1,0xc1,0x81,0xb4]
|
||||
|
||||
s_cmpk_gt_u32 s1, 0x3141
|
||||
// CHECK: [0x41,0x31,0x01,0xb5]
|
||||
|
||||
s_cmpk_gt_u32 s101, 0x3141
|
||||
// CHECK: [0x41,0x31,0x65,0xb5]
|
||||
|
||||
s_cmpk_gt_u32 flat_scratch_lo, 0x3141
|
||||
// CHECK: [0x41,0x31,0x66,0xb5]
|
||||
|
||||
s_cmpk_gt_u32 flat_scratch_hi, 0x3141
|
||||
// CHECK: [0x41,0x31,0x67,0xb5]
|
||||
|
||||
s_cmpk_gt_u32 vcc_lo, 0x3141
|
||||
// CHECK: [0x41,0x31,0x6a,0xb5]
|
||||
|
||||
s_cmpk_gt_u32 vcc_hi, 0x3141
|
||||
// CHECK: [0x41,0x31,0x6b,0xb5]
|
||||
|
||||
s_cmpk_gt_u32 ttmp15, 0x3141
|
||||
// CHECK: [0x41,0x31,0x7b,0xb5]
|
||||
|
||||
s_cmpk_gt_u32 m0, 0x3141
|
||||
// CHECK: [0x41,0x31,0x7c,0xb5]
|
||||
|
||||
s_cmpk_gt_u32 exec_lo, 0x3141
|
||||
// CHECK: [0x41,0x31,0x7e,0xb5]
|
||||
|
||||
s_cmpk_gt_u32 exec_hi, 0x3141
|
||||
// CHECK: [0x41,0x31,0x7f,0xb5]
|
||||
|
||||
s_cmpk_gt_u32 s1, 0xc1d1
|
||||
// CHECK: [0xd1,0xc1,0x01,0xb5]
|
||||
|
||||
s_cmpk_ge_u32 s1, 0x3141
|
||||
// CHECK: [0x41,0x31,0x81,0xb5]
|
||||
|
||||
s_cmpk_ge_u32 s101, 0x3141
|
||||
// CHECK: [0x41,0x31,0xe5,0xb5]
|
||||
|
||||
s_cmpk_ge_u32 flat_scratch_lo, 0x3141
|
||||
// CHECK: [0x41,0x31,0xe6,0xb5]
|
||||
|
||||
s_cmpk_ge_u32 flat_scratch_hi, 0x3141
|
||||
// CHECK: [0x41,0x31,0xe7,0xb5]
|
||||
|
||||
s_cmpk_ge_u32 vcc_lo, 0x3141
|
||||
// CHECK: [0x41,0x31,0xea,0xb5]
|
||||
|
||||
s_cmpk_ge_u32 vcc_hi, 0x3141
|
||||
// CHECK: [0x41,0x31,0xeb,0xb5]
|
||||
|
||||
s_cmpk_ge_u32 ttmp15, 0x3141
|
||||
// CHECK: [0x41,0x31,0xfb,0xb5]
|
||||
|
||||
s_cmpk_ge_u32 m0, 0x3141
|
||||
// CHECK: [0x41,0x31,0xfc,0xb5]
|
||||
|
||||
s_cmpk_ge_u32 exec_lo, 0x3141
|
||||
// CHECK: [0x41,0x31,0xfe,0xb5]
|
||||
|
||||
s_cmpk_ge_u32 exec_hi, 0x3141
|
||||
// CHECK: [0x41,0x31,0xff,0xb5]
|
||||
|
||||
s_cmpk_ge_u32 s1, 0xc1d1
|
||||
// CHECK: [0xd1,0xc1,0x81,0xb5]
|
||||
|
||||
s_cmpk_lt_u32 s1, 0x3141
|
||||
// CHECK: [0x41,0x31,0x01,0xb6]
|
||||
|
||||
s_cmpk_lt_u32 s101, 0x3141
|
||||
// CHECK: [0x41,0x31,0x65,0xb6]
|
||||
|
||||
s_cmpk_lt_u32 flat_scratch_lo, 0x3141
|
||||
// CHECK: [0x41,0x31,0x66,0xb6]
|
||||
|
||||
s_cmpk_lt_u32 flat_scratch_hi, 0x3141
|
||||
// CHECK: [0x41,0x31,0x67,0xb6]
|
||||
|
||||
s_cmpk_lt_u32 vcc_lo, 0x3141
|
||||
// CHECK: [0x41,0x31,0x6a,0xb6]
|
||||
|
||||
s_cmpk_lt_u32 vcc_hi, 0x3141
|
||||
// CHECK: [0x41,0x31,0x6b,0xb6]
|
||||
|
||||
s_cmpk_lt_u32 ttmp15, 0x3141
|
||||
// CHECK: [0x41,0x31,0x7b,0xb6]
|
||||
|
||||
s_cmpk_lt_u32 m0, 0x3141
|
||||
// CHECK: [0x41,0x31,0x7c,0xb6]
|
||||
|
||||
s_cmpk_lt_u32 exec_lo, 0x3141
|
||||
// CHECK: [0x41,0x31,0x7e,0xb6]
|
||||
|
||||
s_cmpk_lt_u32 exec_hi, 0x3141
|
||||
// CHECK: [0x41,0x31,0x7f,0xb6]
|
||||
|
||||
s_cmpk_lt_u32 s1, 0xc1d1
|
||||
// CHECK: [0xd1,0xc1,0x01,0xb6]
|
||||
|
||||
s_cmpk_le_u32 s1, 0x3141
|
||||
// CHECK: [0x41,0x31,0x81,0xb6]
|
||||
|
||||
s_cmpk_le_u32 s101, 0x3141
|
||||
// CHECK: [0x41,0x31,0xe5,0xb6]
|
||||
|
||||
s_cmpk_le_u32 flat_scratch_lo, 0x3141
|
||||
// CHECK: [0x41,0x31,0xe6,0xb6]
|
||||
|
||||
s_cmpk_le_u32 flat_scratch_hi, 0x3141
|
||||
// CHECK: [0x41,0x31,0xe7,0xb6]
|
||||
|
||||
s_cmpk_le_u32 vcc_lo, 0x3141
|
||||
// CHECK: [0x41,0x31,0xea,0xb6]
|
||||
|
||||
s_cmpk_le_u32 vcc_hi, 0x3141
|
||||
// CHECK: [0x41,0x31,0xeb,0xb6]
|
||||
|
||||
s_cmpk_le_u32 ttmp15, 0x3141
|
||||
// CHECK: [0x41,0x31,0xfb,0xb6]
|
||||
|
||||
s_cmpk_le_u32 m0, 0x3141
|
||||
// CHECK: [0x41,0x31,0xfc,0xb6]
|
||||
|
||||
s_cmpk_le_u32 exec_lo, 0x3141
|
||||
// CHECK: [0x41,0x31,0xfe,0xb6]
|
||||
|
||||
s_cmpk_le_u32 exec_hi, 0x3141
|
||||
// CHECK: [0x41,0x31,0xff,0xb6]
|
||||
|
||||
s_cmpk_le_u32 s1, 0xc1d1
|
||||
// CHECK: [0xd1,0xc1,0x81,0xb6]
|
||||
|
||||
s_addk_i32 s5, 0x3141
|
||||
// CHECK: [0x41,0x31,0x05,0xb7]
|
||||
|
||||
s_addk_i32 s101, 0x3141
|
||||
// CHECK: [0x41,0x31,0x65,0xb7]
|
||||
|
||||
s_addk_i32 flat_scratch_lo, 0x3141
|
||||
// CHECK: [0x41,0x31,0x66,0xb7]
|
||||
|
||||
s_addk_i32 flat_scratch_hi, 0x3141
|
||||
// CHECK: [0x41,0x31,0x67,0xb7]
|
||||
|
||||
s_addk_i32 vcc_lo, 0x3141
|
||||
// CHECK: [0x41,0x31,0x6a,0xb7]
|
||||
|
||||
s_addk_i32 vcc_hi, 0x3141
|
||||
// CHECK: [0x41,0x31,0x6b,0xb7]
|
||||
|
||||
s_addk_i32 ttmp15, 0x3141
|
||||
// CHECK: [0x41,0x31,0x7b,0xb7]
|
||||
|
||||
s_addk_i32 m0, 0x3141
|
||||
// CHECK: [0x41,0x31,0x7c,0xb7]
|
||||
|
||||
s_addk_i32 exec_lo, 0x3141
|
||||
// CHECK: [0x41,0x31,0x7e,0xb7]
|
||||
|
||||
s_addk_i32 exec_hi, 0x3141
|
||||
// CHECK: [0x41,0x31,0x7f,0xb7]
|
||||
|
||||
s_addk_i32 s5, 0xc1d1
|
||||
// CHECK: [0xd1,0xc1,0x05,0xb7]
|
||||
|
||||
s_mulk_i32 s5, 0x3141
|
||||
// CHECK: [0x41,0x31,0x85,0xb7]
|
||||
|
||||
s_mulk_i32 s101, 0x3141
|
||||
// CHECK: [0x41,0x31,0xe5,0xb7]
|
||||
|
||||
s_mulk_i32 flat_scratch_lo, 0x3141
|
||||
// CHECK: [0x41,0x31,0xe6,0xb7]
|
||||
|
||||
s_mulk_i32 flat_scratch_hi, 0x3141
|
||||
// CHECK: [0x41,0x31,0xe7,0xb7]
|
||||
|
||||
s_mulk_i32 vcc_lo, 0x3141
|
||||
// CHECK: [0x41,0x31,0xea,0xb7]
|
||||
|
||||
s_mulk_i32 vcc_hi, 0x3141
|
||||
// CHECK: [0x41,0x31,0xeb,0xb7]
|
||||
|
||||
s_mulk_i32 ttmp15, 0x3141
|
||||
// CHECK: [0x41,0x31,0xfb,0xb7]
|
||||
|
||||
s_mulk_i32 m0, 0x3141
|
||||
// CHECK: [0x41,0x31,0xfc,0xb7]
|
||||
|
||||
s_mulk_i32 exec_lo, 0x3141
|
||||
// CHECK: [0x41,0x31,0xfe,0xb7]
|
||||
|
||||
s_mulk_i32 exec_hi, 0x3141
|
||||
// CHECK: [0x41,0x31,0xff,0xb7]
|
||||
|
||||
s_mulk_i32 s5, 0xc1d1
|
||||
// CHECK: [0xd1,0xc1,0x85,0xb7]
|
||||
|
||||
s_cbranch_i_fork s[2:3], 12609
|
||||
// CHECK: [0x41,0x31,0x02,0xb8]
|
||||
|
||||
s_cbranch_i_fork s[4:5], 12609
|
||||
// CHECK: [0x41,0x31,0x04,0xb8]
|
||||
|
||||
s_cbranch_i_fork s[100:101], 12609
|
||||
// CHECK: [0x41,0x31,0x64,0xb8]
|
||||
|
||||
s_cbranch_i_fork flat_scratch, 12609
|
||||
// CHECK: [0x41,0x31,0x66,0xb8]
|
||||
|
||||
s_cbranch_i_fork vcc, 12609
|
||||
// CHECK: [0x41,0x31,0x6a,0xb8]
|
||||
|
||||
s_cbranch_i_fork ttmp[14:15], 12609
|
||||
// CHECK: [0x41,0x31,0x7a,0xb8]
|
||||
|
||||
s_cbranch_i_fork exec, 12609
|
||||
// CHECK: [0x41,0x31,0x7e,0xb8]
|
||||
|
||||
s_cbranch_i_fork s[2:3], 49617
|
||||
// CHECK: [0xd1,0xc1,0x02,0xb8]
|
||||
|
||||
s_getreg_b32 s5, 0x3141
|
||||
// CHECK: [0x41,0x31,0x85,0xb8]
|
||||
|
||||
s_getreg_b32 s101, 0x3141
|
||||
// CHECK: [0x41,0x31,0xe5,0xb8]
|
||||
|
||||
s_getreg_b32 flat_scratch_lo, 0x3141
|
||||
// CHECK: [0x41,0x31,0xe6,0xb8]
|
||||
|
||||
s_getreg_b32 flat_scratch_hi, 0x3141
|
||||
// CHECK: [0x41,0x31,0xe7,0xb8]
|
||||
|
||||
s_getreg_b32 vcc_lo, 0x3141
|
||||
// CHECK: [0x41,0x31,0xea,0xb8]
|
||||
|
||||
s_getreg_b32 vcc_hi, 0x3141
|
||||
// CHECK: [0x41,0x31,0xeb,0xb8]
|
||||
|
||||
s_getreg_b32 ttmp15, 0x3141
|
||||
// CHECK: [0x41,0x31,0xfb,0xb8]
|
||||
|
||||
s_getreg_b32 m0, 0x3141
|
||||
// CHECK: [0x41,0x31,0xfc,0xb8]
|
||||
|
||||
s_getreg_b32 exec_lo, 0x3141
|
||||
// CHECK: [0x41,0x31,0xfe,0xb8]
|
||||
|
||||
s_getreg_b32 exec_hi, 0x3141
|
||||
// CHECK: [0x41,0x31,0xff,0xb8]
|
||||
|
||||
s_getreg_b32 s5, 0xc1d1
|
||||
// CHECK: [0xd1,0xc1,0x85,0xb8]
|
||||
|
||||
s_setreg_b32 0x3141, s1
|
||||
// CHECK: [0x41,0x31,0x01,0xb9]
|
||||
|
||||
s_setreg_b32 0xc1d1, s1
|
||||
// CHECK: [0xd1,0xc1,0x01,0xb9]
|
||||
|
||||
s_setreg_b32 0x3141, s101
|
||||
// CHECK: [0x41,0x31,0x65,0xb9]
|
||||
|
||||
s_setreg_b32 0x3141, flat_scratch_lo
|
||||
// CHECK: [0x41,0x31,0x66,0xb9]
|
||||
|
||||
s_setreg_b32 0x3141, flat_scratch_hi
|
||||
// CHECK: [0x41,0x31,0x67,0xb9]
|
||||
|
||||
s_setreg_b32 0x3141, vcc_lo
|
||||
// CHECK: [0x41,0x31,0x6a,0xb9]
|
||||
|
||||
s_setreg_b32 0x3141, vcc_hi
|
||||
// CHECK: [0x41,0x31,0x6b,0xb9]
|
||||
|
||||
s_setreg_b32 0x3141, ttmp15
|
||||
// CHECK: [0x41,0x31,0x7b,0xb9]
|
||||
|
||||
s_setreg_b32 0x3141, m0
|
||||
// CHECK: [0x41,0x31,0x7c,0xb9]
|
||||
|
||||
s_setreg_b32 0x3141, exec_lo
|
||||
// CHECK: [0x41,0x31,0x7e,0xb9]
|
||||
|
||||
s_setreg_b32 0x3141, exec_hi
|
||||
// CHECK: [0x41,0x31,0x7f,0xb9]
|
||||
|
||||
s_setreg_imm32_b32 0x3141, 0x11213141
|
||||
// CHECK: [0x41,0x31,0x00,0xba,0x41,0x31,0x21,0x11]
|
||||
|
||||
s_setreg_imm32_b32 0xc1d1, 0x11213141
|
||||
// CHECK: [0xd1,0xc1,0x00,0xba,0x41,0x31,0x21,0x11]
|
||||
|
||||
s_setreg_imm32_b32 0x3141, 0xa1b1c1d1
|
||||
// CHECK: [0x41,0x31,0x00,0xba,0xd1,0xc1,0xb1,0xa1]
|
||||
|
||||
s_call_b64 s[10:11], 12609
|
||||
// CHECK: [0x41,0x31,0x8a,0xba]
|
||||
|
||||
s_call_b64 s[12:13], 12609
|
||||
// CHECK: [0x41,0x31,0x8c,0xba]
|
||||
|
||||
s_call_b64 s[100:101], 12609
|
||||
// CHECK: [0x41,0x31,0xe4,0xba]
|
||||
|
||||
s_call_b64 flat_scratch, 12609
|
||||
// CHECK: [0x41,0x31,0xe6,0xba]
|
||||
|
||||
s_call_b64 vcc, 12609
|
||||
// CHECK: [0x41,0x31,0xea,0xba]
|
||||
|
||||
s_call_b64 ttmp[14:15], 12609
|
||||
// CHECK: [0x41,0x31,0xfa,0xba]
|
||||
|
||||
s_call_b64 exec, 12609
|
||||
// CHECK: [0x41,0x31,0xfe,0xba]
|
||||
|
||||
s_call_b64 s[10:11], 49617
|
||||
// CHECK: [0xd1,0xc1,0x8a,0xba]
|
||||
|
|
@ -0,0 +1,166 @@
|
|||
// RUN: llvm-mc -arch=amdgcn -mcpu=gfx900 -show-encoding %s | FileCheck %s
|
||||
|
||||
s_nop 0x3141
|
||||
// CHECK: [0x41,0x31,0x80,0xbf]
|
||||
|
||||
s_nop 0xc1d1
|
||||
// CHECK: [0xd1,0xc1,0x80,0xbf]
|
||||
|
||||
s_endpgm
|
||||
// CHECK: [0x00,0x00,0x81,0xbf]
|
||||
|
||||
s_branch 12609
|
||||
// CHECK: [0x41,0x31,0x82,0xbf]
|
||||
|
||||
s_branch 49617
|
||||
// CHECK: [0xd1,0xc1,0x82,0xbf]
|
||||
|
||||
s_wakeup
|
||||
// CHECK: [0x00,0x00,0x83,0xbf]
|
||||
|
||||
s_cbranch_scc0 12609
|
||||
// CHECK: [0x41,0x31,0x84,0xbf]
|
||||
|
||||
s_cbranch_scc0 49617
|
||||
// CHECK: [0xd1,0xc1,0x84,0xbf]
|
||||
|
||||
s_cbranch_scc1 12609
|
||||
// CHECK: [0x41,0x31,0x85,0xbf]
|
||||
|
||||
s_cbranch_scc1 49617
|
||||
// CHECK: [0xd1,0xc1,0x85,0xbf]
|
||||
|
||||
s_cbranch_vccz 12609
|
||||
// CHECK: [0x41,0x31,0x86,0xbf]
|
||||
|
||||
s_cbranch_vccz 49617
|
||||
// CHECK: [0xd1,0xc1,0x86,0xbf]
|
||||
|
||||
s_cbranch_vccnz 12609
|
||||
// CHECK: [0x41,0x31,0x87,0xbf]
|
||||
|
||||
s_cbranch_vccnz 49617
|
||||
// CHECK: [0xd1,0xc1,0x87,0xbf]
|
||||
|
||||
s_cbranch_execz 12609
|
||||
// CHECK: [0x41,0x31,0x88,0xbf]
|
||||
|
||||
s_cbranch_execz 49617
|
||||
// CHECK: [0xd1,0xc1,0x88,0xbf]
|
||||
|
||||
s_cbranch_execnz 12609
|
||||
// CHECK: [0x41,0x31,0x89,0xbf]
|
||||
|
||||
s_cbranch_execnz 49617
|
||||
// CHECK: [0xd1,0xc1,0x89,0xbf]
|
||||
|
||||
s_barrier
|
||||
// CHECK: [0x00,0x00,0x8a,0xbf]
|
||||
|
||||
s_setkill 0x3141
|
||||
// CHECK: [0x41,0x31,0x8b,0xbf]
|
||||
|
||||
s_setkill 0xc1d1
|
||||
// CHECK: [0xd1,0xc1,0x8b,0xbf]
|
||||
|
||||
s_waitcnt 0x3141
|
||||
// CHECK: [0x41,0x31,0x8c,0xbf]
|
||||
|
||||
s_waitcnt 0xc1d1
|
||||
// CHECK: [0xd1,0xc1,0x8c,0xbf]
|
||||
|
||||
s_sethalt 0x3141
|
||||
// CHECK: [0x41,0x31,0x8d,0xbf]
|
||||
|
||||
s_sethalt 0xc1d1
|
||||
// CHECK: [0xd1,0xc1,0x8d,0xbf]
|
||||
|
||||
s_sleep 0x3141
|
||||
// CHECK: [0x41,0x31,0x8e,0xbf]
|
||||
|
||||
s_sleep 0xc1d1
|
||||
// CHECK: [0xd1,0xc1,0x8e,0xbf]
|
||||
|
||||
s_setprio 0x3141
|
||||
// CHECK: [0x41,0x31,0x8f,0xbf]
|
||||
|
||||
s_setprio 0xc1d1
|
||||
// CHECK: [0xd1,0xc1,0x8f,0xbf]
|
||||
|
||||
s_sendmsg 0x3141
|
||||
// CHECK: [0x41,0x31,0x90,0xbf]
|
||||
|
||||
s_sendmsg 0xc1d1
|
||||
// CHECK: [0xd1,0xc1,0x90,0xbf]
|
||||
|
||||
s_sendmsghalt 0x3141
|
||||
// CHECK: [0x41,0x31,0x91,0xbf]
|
||||
|
||||
s_sendmsghalt 0xc1d1
|
||||
// CHECK: [0xd1,0xc1,0x91,0xbf]
|
||||
|
||||
s_trap 0x3141
|
||||
// CHECK: [0x41,0x31,0x92,0xbf]
|
||||
|
||||
s_trap 0xc1d1
|
||||
// CHECK: [0xd1,0xc1,0x92,0xbf]
|
||||
|
||||
s_icache_inv
|
||||
// CHECK: [0x00,0x00,0x93,0xbf]
|
||||
|
||||
s_incperflevel 0x3141
|
||||
// CHECK: [0x41,0x31,0x94,0xbf]
|
||||
|
||||
s_incperflevel 0xc1d1
|
||||
// CHECK: [0xd1,0xc1,0x94,0xbf]
|
||||
|
||||
s_decperflevel 0x3141
|
||||
// CHECK: [0x41,0x31,0x95,0xbf]
|
||||
|
||||
s_decperflevel 0xc1d1
|
||||
// CHECK: [0xd1,0xc1,0x95,0xbf]
|
||||
|
||||
s_ttracedata
|
||||
// CHECK: [0x00,0x00,0x96,0xbf]
|
||||
|
||||
s_cbranch_cdbgsys 12609
|
||||
// CHECK: [0x41,0x31,0x97,0xbf]
|
||||
|
||||
s_cbranch_cdbgsys 49617
|
||||
// CHECK: [0xd1,0xc1,0x97,0xbf]
|
||||
|
||||
s_cbranch_cdbguser 12609
|
||||
// CHECK: [0x41,0x31,0x98,0xbf]
|
||||
|
||||
s_cbranch_cdbguser 49617
|
||||
// CHECK: [0xd1,0xc1,0x98,0xbf]
|
||||
|
||||
s_cbranch_cdbgsys_or_user 12609
|
||||
// CHECK: [0x41,0x31,0x99,0xbf]
|
||||
|
||||
s_cbranch_cdbgsys_or_user 49617
|
||||
// CHECK: [0xd1,0xc1,0x99,0xbf]
|
||||
|
||||
s_cbranch_cdbgsys_and_user 12609
|
||||
// CHECK: [0x41,0x31,0x9a,0xbf]
|
||||
|
||||
s_cbranch_cdbgsys_and_user 49617
|
||||
// CHECK: [0xd1,0xc1,0x9a,0xbf]
|
||||
|
||||
s_endpgm_saved
|
||||
// CHECK: [0x00,0x00,0x9b,0xbf]
|
||||
|
||||
s_set_gpr_idx_off
|
||||
// CHECK: [0x00,0x00,0x9c,0xbf]
|
||||
|
||||
s_set_gpr_idx_mode 0x0
|
||||
// CHECK: [0x00,0x00,0x9d,0xbf]
|
||||
|
||||
s_set_gpr_idx_mode 0x1
|
||||
// CHECK: [0x01,0x00,0x9d,0xbf]
|
||||
|
||||
s_set_gpr_idx_mode 0xF
|
||||
// CHECK: [0x0f,0x00,0x9d,0xbf]
|
||||
|
||||
s_endpgm_ordered_ps_done
|
||||
// CHECK: [0x00,0x00,0x9e,0xbf]
|
||||
|
|
@ -0,0 +1,85 @@
|
|||
// RUN: llvm-mc -arch=amdgcn -mcpu=gfx900 -show-encoding %s | FileCheck %s
|
||||
|
||||
v_interp_p1_f32 v5, v1, attr0.x
|
||||
// CHECK: [0x01,0x00,0x14,0xd4]
|
||||
|
||||
v_interp_p1_f32 v255, v1, attr0.x
|
||||
// CHECK: [0x01,0x00,0xfc,0xd7]
|
||||
|
||||
v_interp_p1_f32 v5, v255, attr0.x
|
||||
// CHECK: [0xff,0x00,0x14,0xd4]
|
||||
|
||||
v_interp_p1_f32 v5, v1, attr1.x
|
||||
// CHECK: [0x01,0x04,0x14,0xd4]
|
||||
|
||||
v_interp_p1_f32 v5, v1, attr31.x
|
||||
// CHECK: [0x01,0x7c,0x14,0xd4]
|
||||
|
||||
v_interp_p1_f32 v5, v1, attr32.x
|
||||
// CHECK: [0x01,0x80,0x14,0xd4]
|
||||
|
||||
v_interp_p1_f32 v5, v1, attr0.y
|
||||
// CHECK: [0x01,0x01,0x14,0xd4]
|
||||
|
||||
v_interp_p1_f32 v5, v1, attr0.z
|
||||
// CHECK: [0x01,0x02,0x14,0xd4]
|
||||
|
||||
v_interp_p1_f32 v5, v1, attr0.w
|
||||
// CHECK: [0x01,0x03,0x14,0xd4]
|
||||
|
||||
v_interp_p2_f32 v5, v1, attr0.x
|
||||
// CHECK: [0x01,0x00,0x15,0xd4]
|
||||
|
||||
v_interp_p2_f32 v255, v1, attr0.x
|
||||
// CHECK: [0x01,0x00,0xfd,0xd7]
|
||||
|
||||
v_interp_p2_f32 v5, v255, attr0.x
|
||||
// CHECK: [0xff,0x00,0x15,0xd4]
|
||||
|
||||
v_interp_p2_f32 v5, v1, attr1.x
|
||||
// CHECK: [0x01,0x04,0x15,0xd4]
|
||||
|
||||
v_interp_p2_f32 v5, v1, attr31.x
|
||||
// CHECK: [0x01,0x7c,0x15,0xd4]
|
||||
|
||||
v_interp_p2_f32 v5, v1, attr32.x
|
||||
// CHECK: [0x01,0x80,0x15,0xd4]
|
||||
|
||||
v_interp_p2_f32 v5, v1, attr0.y
|
||||
// CHECK: [0x01,0x01,0x15,0xd4]
|
||||
|
||||
v_interp_p2_f32 v5, v1, attr0.z
|
||||
// CHECK: [0x01,0x02,0x15,0xd4]
|
||||
|
||||
v_interp_p2_f32 v5, v1, attr0.w
|
||||
// CHECK: [0x01,0x03,0x15,0xd4]
|
||||
|
||||
v_interp_mov_f32 v5, p10, attr0.x
|
||||
// CHECK: [0x00,0x00,0x16,0xd4]
|
||||
|
||||
v_interp_mov_f32 v255, p10, attr0.x
|
||||
// CHECK: [0x00,0x00,0xfe,0xd7]
|
||||
|
||||
v_interp_mov_f32 v5, p20, attr0.x
|
||||
// CHECK: [0x01,0x00,0x16,0xd4]
|
||||
|
||||
v_interp_mov_f32 v5, p0, attr0.x
|
||||
// CHECK: [0x02,0x00,0x16,0xd4]
|
||||
|
||||
v_interp_mov_f32 v5, p10, attr1.x
|
||||
// CHECK: [0x00,0x04,0x16,0xd4]
|
||||
|
||||
v_interp_mov_f32 v5, p10, attr31.x
|
||||
// CHECK: [0x00,0x7c,0x16,0xd4]
|
||||
|
||||
v_interp_mov_f32 v5, p10, attr32.x
|
||||
// CHECK: [0x00,0x80,0x16,0xd4]
|
||||
|
||||
v_interp_mov_f32 v5, p10, attr0.y
|
||||
// CHECK: [0x00,0x01,0x16,0xd4]
|
||||
|
||||
v_interp_mov_f32 v5, p10, attr0.z
|
||||
// CHECK: [0x00,0x02,0x16,0xd4]
|
||||
|
||||
v_interp_mov_f32 v5, p10, attr0.w
|
||||
// CHECK: [0x00,0x03,0x16,0xd4]
|
||||
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
Loading…
Reference in New Issue