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[ARM] Use patterns instead of hardcoded regs in test. NFC. 

llvm-svn: 228259
This commit is contained in:
Ahmed Bougacha 2015-02-05 01:52:19 +00:00
parent daaf3d9b58
commit c7f241cba9
1 changed files with 5 additions and 5 deletions
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10
llvm/test/CodeGen/ARM/big-endian-neon-extend.ll
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@ -12,7 +12,7 @@ define void @vector_ext_2i8_to_2i64( <2 x i8>* %loadaddr, <2 x i64>* %storeaddr
; CHECK-NEXT: vrev64.32 [[QREG]], [[QREG]]
; CHECK-NEXT: vand [[QREG]], [[QREG]], [[MASK]]
; CHECK-NEXT: vrev64.32 [[QREG]], [[QREG]]
; CHECK-NEXT: vst1.64 {[[REG]], d17}, [r1]
; CHECK-NEXT: vst1.64 {[[REG]], {{d[0-9]+}}}, [r1]
; CHECK-NEXT: bx lr
%1 = load <2 x i8>* %loadaddr
%2 = zext <2 x i8> %1 to <2 x i64>
@ -31,7 +31,7 @@ define void @vector_ext_2i16_to_2i64( <2 x i16>* %loadaddr, <2 x i64>* %storeadd
; CHECK-NEXT: vrev64.32 [[QREG]], [[QREG]]
; CHECK-NEXT: vand [[QREG]], [[QREG]], [[MASK]]
; CHECK-NEXT: vrev64.32 [[QREG]], [[QREG]]
; CHECK-NEXT: vst1.64 {[[REG]], d17}, [r1]
; CHECK-NEXT: vst1.64 {[[REG]], {{d[0-9]+}}}, [r1]
; CHECK-NEXT: bx lr
%1 = load <2 x i16>* %loadaddr
%2 = zext <2 x i16> %1 to <2 x i64>
@ -76,8 +76,8 @@ define void @vector_ext_2i8_to_2i16( <2 x i8>* %loadaddr, <2 x i16>* %storeaddr
; CHECK-NEXT: vmovl.u8 [[QREG:q[0-9]+]], [[REG]]
; CHECK-NEXT: vmovl.u16 [[QREG]], [[REG]]
; CHECK-NEXT: vrev32.16 [[REG]], [[REG]]
; CHECK-NEXT: vuzp.16 [[REG]], d17
; CHECK-NEXT: vrev32.16 [[REG]], d17
; CHECK-NEXT: vuzp.16 [[REG]], {{d[0-9]+}}
; CHECK-NEXT: vrev32.16 [[REG]], {{d[0-9]+}}
; CHECK-NEXT: vst1.32 {[[REG]][0]}, [r1:32]
; CHECK-NEXT: bx lr
%1 = load <2 x i8>* %loadaddr
@ -93,7 +93,7 @@ define void @vector_ext_4i8_to_4i32( <4 x i8>* %loadaddr, <4 x i32>* %storeaddr
; CHECK-NEXT: vmovl.u8 [[QREG:q[0-9]+]], [[REG]]
; CHECK-NEXT: vmovl.u16 [[QREG]], [[REG]]
; CHECK-NEXT: vrev64.32 [[QREG]], [[QREG]]
; CHECK-NEXT: vst1.64 {[[REG]], d17}, [r1]
; CHECK-NEXT: vst1.64 {[[REG]], {{d[0-9]+}}}, [r1]
; CHECK-NEXT: bx lr
%1 = load <4 x i8>* %loadaddr
%2 = zext <4 x i8> %1 to <4 x i32>