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[AMDGPU] Fix scheduling info for terminator SALU instructions 

Summary:
Instruction variants like S_MOV_B32_term should have the same SchedRW
class as the base instruction, S_MOV_B32. This probably doesn't make any
difference in practice because as terminators, they'll always be
scheduled at the end of a basic block, but it's simply more correct than
giving them all the default SchedRW class of Write32Bit, which implies a
VALU operation.

Reviewers: rampitec, arsenm, nhaehnle

Subscribers: kzhuravl, jvesely, wdng, yaxunl, dstuttard, tpr, t-tye, hiraditya, kerbowa, llvm-commits

Tags: #llvm

Differential Revision: https://reviews.llvm.org/D75860
This commit is contained in:
Jay Foad 2020-03-06 15:35:35 +00:00
parent 6bfd10ff80
commit c7b2e7f527
1 changed files with 1 additions and 0 deletions
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1
llvm/lib/Target/AMDGPU/SIInstructions.td
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@ -230,6 +230,7 @@ class WrapTerminatorInst<SOP_Pseudo base_inst> : SPseudoInstSI<
let hasSideEffects = base_inst.hasSideEffects; let hasSideEffects = base_inst.hasSideEffects;
let UseNamedOperandTable = base_inst.UseNamedOperandTable; let UseNamedOperandTable = base_inst.UseNamedOperandTable;
let CodeSize = base_inst.CodeSize; let CodeSize = base_inst.CodeSize;
let SchedRW = base_inst.SchedRW;
} }
let WaveSizePredicate = isWave64 in { let WaveSizePredicate = isWave64 in {