forked from OSchip/llvm-project
[OPENMP 4.0] Codegen for 'declare simd' directive.
OpenMP 4.0 adds support for elemental functions using declarative directive '#pragma omp declare simd'. Patch adds mangling for simd functions in accordance with https://sourceware.org/glibc/wiki/libmvec?action=AttachFile&do=view&target=VectorABI.txt llvm-svn: 268721
This commit is contained in:
Alexey Bataev
parent
f578140ba6
commit
c7a82b41a7
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@ -6042,3 +6042,228 @@ void CGOpenMPRuntime::emitTargetEnterOrExitDataCall(
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ThenGenRCG(CGF);
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}
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}
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namespace {
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/// Kind of parameter in a function with 'declare simd' directive.
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enum ParamKindTy { LinearWithVarStride, Linear, Uniform, Vector };
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/// Attribute set of the parameter.
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struct ParamAttrTy {
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ParamKindTy Kind = Vector;
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llvm::APSInt StrideOrArg;
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llvm::APSInt Alignment;
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};
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} // namespace
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static unsigned evaluateCDTSize(const FunctionDecl *FD,
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ArrayRef<ParamAttrTy> ParamAttrs) {
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// Every vector variant of a SIMD-enabled function has a vector length (VLEN).
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// If OpenMP clause "simdlen" is used, the VLEN is the value of the argument
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// of that clause. The VLEN value must be power of 2.
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// In other case the notion of the function`s "characteristic data type" (CDT)
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// is used to compute the vector length.
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// CDT is defined in the following order:
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// a) For non-void function, the CDT is the return type.
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// b) If the function has any non-uniform, non-linear parameters, then the
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// CDT is the type of the first such parameter.
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// c) If the CDT determined by a) or b) above is struct, union, or class
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// type which is pass-by-value (except for the type that maps to the
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// built-in complex data type), the characteristic data type is int.
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// d) If none of the above three cases is applicable, the CDT is int.
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// The VLEN is then determined based on the CDT and the size of vector
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// register of that ISA for which current vector version is generated. The
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// VLEN is computed using the formula below:
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// VLEN = sizeof(vector_register) / sizeof(CDT),
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// where vector register size specified in section 3.2.1 Registers and the
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// Stack Frame of original AMD64 ABI document.
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QualType RetType = FD->getReturnType();
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if (RetType.isNull())
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return 0;
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ASTContext &C = FD->getASTContext();
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QualType CDT;
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if (!RetType.isNull() && !RetType->isVoidType())
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CDT = RetType;
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else {
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unsigned Offset = 0;
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if (auto *MD = dyn_cast<CXXMethodDecl>(FD)) {
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if (ParamAttrs[Offset].Kind == Vector)
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CDT = C.getPointerType(C.getRecordType(MD->getParent()));
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++Offset;
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}
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if (CDT.isNull()) {
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for (unsigned I = 0, E = FD->getNumParams(); I < E; ++I) {
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if (ParamAttrs[I + Offset].Kind == Vector) {
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CDT = FD->getParamDecl(I)->getType();
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break;
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}
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}
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}
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}
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if (CDT.isNull())
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CDT = C.IntTy;
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CDT = CDT->getCanonicalTypeUnqualified();
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if (CDT->isRecordType() || CDT->isUnionType())
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CDT = C.IntTy;
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return C.getTypeSize(CDT);
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}
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static void
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emitX86DeclareSimdFunction(const FunctionDecl *FD, llvm::Function *Fn,
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llvm::APSInt VLENVal,
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ArrayRef<ParamAttrTy> ParamAttrs,
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OMPDeclareSimdDeclAttr::BranchStateTy State) {
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struct ISADataTy {
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char ISA;
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unsigned VecRegSize;
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};
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ISADataTy ISAData[] = {
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{
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'b', 128
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}, // SSE
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{
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'c', 256
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}, // AVX
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{
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'd', 256
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}, // AVX2
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{
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'e', 512
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}, // AVX512
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};
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llvm::SmallVector<char, 2> Masked;
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switch (State) {
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case OMPDeclareSimdDeclAttr::BS_Undefined:
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Masked.push_back('N');
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Masked.push_back('M');
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break;
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case OMPDeclareSimdDeclAttr::BS_Notinbranch:
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Masked.push_back('N');
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break;
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case OMPDeclareSimdDeclAttr::BS_Inbranch:
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Masked.push_back('M');
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break;
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}
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for (auto Mask : Masked) {
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for (auto &Data : ISAData) {
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SmallString<256> Buffer;
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llvm::raw_svector_ostream Out(Buffer);
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Out << "_ZGV" << Data.ISA << Mask;
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if (!VLENVal) {
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Out << llvm::APSInt::getUnsigned(Data.VecRegSize /
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evaluateCDTSize(FD, ParamAttrs));
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} else
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Out << VLENVal;
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for (auto &ParamAttr : ParamAttrs) {
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switch (ParamAttr.Kind){
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case LinearWithVarStride:
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Out << 's' << ParamAttr.StrideOrArg;
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break;
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case Linear:
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Out << 'l';
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if (!!ParamAttr.StrideOrArg)
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Out << ParamAttr.StrideOrArg;
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break;
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case Uniform:
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Out << 'u';
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break;
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case Vector:
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Out << 'v';
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break;
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}
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if (!!ParamAttr.Alignment)
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Out << 'a' << ParamAttr.Alignment;
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}
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Out << '_' << Fn->getName();
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Fn->addFnAttr(Out.str());
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}
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}
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}
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void CGOpenMPRuntime::emitDeclareSimdFunction(const FunctionDecl *FD,
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llvm::Function *Fn) {
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ASTContext &C = CGM.getContext();
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FD = FD->getCanonicalDecl();
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// Map params to their positions in function decl.
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llvm::DenseMap<const Decl *, unsigned> ParamPositions;
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if (isa<CXXMethodDecl>(FD))
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ParamPositions.insert({FD, 0});
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unsigned ParamPos = ParamPositions.size();
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for (auto *P : FD->params()) {
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ParamPositions.insert({P->getCanonicalDecl(), ParamPos});
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++ParamPos;
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}
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for (auto *Attr : FD->specific_attrs<OMPDeclareSimdDeclAttr>()) {
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llvm::SmallVector<ParamAttrTy, 8> ParamAttrs(ParamPositions.size());
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// Mark uniform parameters.
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for (auto *E : Attr->uniforms()) {
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E = E->IgnoreParenImpCasts();
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unsigned Pos;
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if (isa<CXXThisExpr>(E))
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Pos = ParamPositions[FD];
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else {
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auto *PVD = cast<ParmVarDecl>(cast<DeclRefExpr>(E)->getDecl())
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->getCanonicalDecl();
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Pos = ParamPositions[PVD];
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}
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ParamAttrs[Pos].Kind = Uniform;
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}
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// Get alignment info.
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auto NI = Attr->alignments_begin();
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for (auto *E : Attr->aligneds()) {
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E = E->IgnoreParenImpCasts();
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unsigned Pos;
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QualType ParmTy;
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if (isa<CXXThisExpr>(E)) {
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Pos = ParamPositions[FD];
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ParmTy = E->getType();
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} else {
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auto *PVD = cast<ParmVarDecl>(cast<DeclRefExpr>(E)->getDecl())
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->getCanonicalDecl();
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Pos = ParamPositions[PVD];
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ParmTy = PVD->getType();
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}
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ParamAttrs[Pos].Alignment =
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(*NI) ? (*NI)->EvaluateKnownConstInt(C)
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: llvm::APSInt::getUnsigned(
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C.toCharUnitsFromBits(C.getOpenMPDefaultSimdAlign(ParmTy))
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.getQuantity());
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++NI;
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}
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// Mark linear parameters.
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auto SI = Attr->steps_begin();
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auto MI = Attr->modifiers_begin();
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for (auto *E : Attr->linears()) {
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E = E->IgnoreParenImpCasts();
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unsigned Pos;
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if (isa<CXXThisExpr>(E))
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Pos = ParamPositions[FD];
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else {
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auto *PVD = cast<ParmVarDecl>(cast<DeclRefExpr>(E)->getDecl())
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->getCanonicalDecl();
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Pos = ParamPositions[PVD];
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}
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auto &ParamAttr = ParamAttrs[Pos];
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ParamAttr.Kind = Linear;
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if (*SI) {
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if (!(*SI)->EvaluateAsInt(ParamAttr.StrideOrArg, C,
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Expr::SE_AllowSideEffects)) {
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if (auto *DRE = cast<DeclRefExpr>((*SI)->IgnoreParenImpCasts())) {
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if (auto *StridePVD = cast<ParmVarDecl>(DRE->getDecl())) {
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ParamAttr.Kind = LinearWithVarStride;
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ParamAttr.StrideOrArg = llvm::APSInt::getUnsigned(
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ParamPositions[StridePVD->getCanonicalDecl()]);
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}
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}
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}
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}
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++SI;
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++MI;
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}
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llvm::APSInt VLENVal;
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if (const Expr *VLEN = Attr->getSimdlen())
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VLENVal = VLEN->EvaluateKnownConstInt(C);
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OMPDeclareSimdDeclAttr::BranchStateTy State = Attr->getBranchState();
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if (CGM.getTriple().getArch() == llvm::Triple::x86 ||
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CGM.getTriple().getArch() == llvm::Triple::x86_64)
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emitX86DeclareSimdFunction(FD, Fn, VLENVal, ParamAttrs, State);
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}
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}
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@ -1013,6 +1013,13 @@ public:
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const OMPExecutableDirective &D,
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const Expr *IfCond,
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const Expr *Device);
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/// Marks function \a Fn with properly mangled versions of vector functions.
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/// \param FD Function marked as 'declare simd'.
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/// \param Fn LLVM function that must be marked with 'declare simd'
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/// attributes.
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virtual void emitDeclareSimdFunction(const FunctionDecl *FD,
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llvm::Function *Fn);
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};
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} // namespace CodeGen
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@ -710,6 +710,8 @@ void CodeGenFunction::StartFunction(GlobalDecl GD,
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}
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} else if (!FD->hasAttr<AlwaysInlineAttr>())
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Fn->addFnAttr(llvm::Attribute::NoInline);
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if (CGM.getLangOpts().OpenMP && FD->hasAttr<OMPDeclareSimdDeclAttr>())
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CGM.getOpenMPRuntime().emitDeclareSimdFunction(FD, Fn);
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}
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// Add no-jump-tables value.
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@ -0,0 +1,288 @@
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// RUN: %clang_cc1 -verify -triple x86_64-apple-darwin10 -fopenmp -x c++ -emit-llvm %s -o - -femit-all-decls | FileCheck %s
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// RUN: %clang_cc1 -fopenmp -x c++ -triple x86_64-apple-darwin10 -emit-pch -o %t %s
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// RUN: %clang_cc1 -fopenmp -x c++ -triple x86_64-apple-darwin10 -include-pch %t -verify %s -emit-llvm -o - -femit-all-decls | FileCheck %s
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// expected-no-diagnostics
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// REQUIRES: x86-registered-target
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#ifndef HEADER
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#define HEADER
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#pragma omp declare simd linear(d : 8)
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#pragma omp declare simd inbranch simdlen(32)
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#pragma omp declare simd notinbranch
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void add_1(float *d) {}
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#pragma omp declare simd aligned(hp, hp2)
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template <class C>
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void h(C *hp, C *hp2, C *hq, C *lin) {
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}
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// Explicit specialization with <C=int>.
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// Pragmas need to be same, otherwise standard says that's undefined behavior.
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#pragma omp declare simd aligned(hp, hp2)
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template <>
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void h(int *hp, int *hp2, int *hq, int *lin) {
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// Implicit specialization with <C=float>.
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// This is special case where the directive is stored by Sema and is
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// generated together with the (pending) function instatiation.
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h((float *)hp, (float *)hp2, (float *)hq, (float *)lin);
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}
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class VV {
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public:
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#pragma omp declare simd uniform(this, a) linear(val(b) : a)
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int add(int a, int b) __attribute__((cold)) { return a + b; }
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#pragma omp declare simd aligned(b : 4) aligned(a) linear(ref(b) : 4) linear(this, a)
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float taddpf(float *a, float *&b) { return *a + *b; }
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#pragma omp declare simd linear(uval(c) : 8)
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#pragma omp declare simd aligned(b : 8)
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int tadd(int (&b)[], int &c) { return x[b[0]] + b[0]; }
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private:
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int x[10];
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} vv;
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template <int X, typename T>
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class TVV {
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public:
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#pragma omp declare simd simdlen(X)
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int tadd(int a, int b) { return a + b; }
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#pragma omp declare simd aligned(a : X * 2) aligned(b) linear(ref(b) : X)
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float taddpf(float *a, T *&b) { return *a + *b; }
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#pragma omp declare simd
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#pragma omp declare simd uniform(this, b)
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int tadd(int b) { return x[b] + b; }
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private:
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int x[X];
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};
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#pragma omp declare simd simdlen(N) aligned(b : N * 2) linear(uval(c) : N)
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template <int N>
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void foo(int (&b)[N], float *&c) {}
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TVV<16, float> t16;
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void f(int (&g)[]) {
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float a = 1.0f, b = 2.0f;
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float *p = &b;
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float r = t16.taddpf(&a, p);
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int res = t16.tadd(b);
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int c[64];
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vv.add(res, res);
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vv.taddpf(p, p);
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vv.tadd(g, res);
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foo(c, p);
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}
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#pragma omp declare simd
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#pragma omp declare simd notinbranch aligned(a : 32)
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int bar(VV v, float *a) { return 0; }
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#pragma omp declare simd
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#pragma omp declare simd notinbranch aligned(a)
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float baz(VV v, int a[]) { return 0; }
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#pragma omp declare simd
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#pragma omp declare simd notinbranch aligned(a)
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double bay(VV v, double *&a) { return 0; }
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#pragma omp declare simd
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#pragma omp declare simd inbranch linear(a : b) uniform(v, b)
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void bax(VV v, double *a, int b) {}
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#pragma omp declare simd uniform(q) aligned(q : 16) linear(k : 1)
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float foo(float *q, float x, int k) { return 0; }
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#pragma omp declare simd notinbranch
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double foo(double x) { return 0; }
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// CHECK-DAG: define {{.+}}@_Z5add_1Pf(
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// CHECK-DAG: define {{.+}}@_Z1hIiEvPT_S1_S1_S1_(
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// CHECK-DAG: define {{.+}}@_Z1hIfEvPT_S1_S1_S1_(
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// CHECK-DAG: define {{.+}}@_ZN2VV3addEii(
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// CHECK-DAG: define {{.+}}@_ZN2VV6taddpfEPfRS0_(
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// CHECK-DAG: define {{.+}}@_ZN2VV4taddERA_iRi(
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// CHECK-DAG: define {{.+}}@_Z1fRA_i(
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// CHECK-DAG: define {{.+}}@_ZN3TVVILi16EfE6taddpfEPfRS1_(
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// CHECK-DAG: define {{.+}}@_ZN3TVVILi16EfE4taddEi(
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// CHECK-DAG: define {{.+}}@_Z3fooILi64EEvRAT__iRPf(
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// CHECK-DAG: define {{.+}}@_Z3bar2VVPf(
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// CHECK-DAG: define {{.+}}@_Z3baz2VVPi(
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// CHECK-DAG: define {{.+}}@_Z3bay2VVRPd(
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// CHECK-DAG: define {{.+}}@_Z3bax2VVPdi(
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// CHECK-DAG: define {{.+}}@_Z3fooPffi(
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// CHECK-DAG: define {{.+}}@_Z3food(
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// CHECK-DAG: "_ZGVbM4l8__Z5add_1Pf"
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// CHECK-DAG: "_ZGVbN4l8__Z5add_1Pf"
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// CHECK-DAG: "_ZGVcM8l8__Z5add_1Pf"
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// CHECK-DAG: "_ZGVcN8l8__Z5add_1Pf"
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// CHECK-DAG: "_ZGVdM8l8__Z5add_1Pf"
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// CHECK-DAG: "_ZGVdN8l8__Z5add_1Pf"
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// CHECK-DAG: "_ZGVeM16l8__Z5add_1Pf"
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// CHECK-DAG: "_ZGVeN16l8__Z5add_1Pf"
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// CHECK-DAG: "_ZGVbM32v__Z5add_1Pf"
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// CHECK-DAG: "_ZGVcM32v__Z5add_1Pf"
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// CHECK-DAG: "_ZGVdM32v__Z5add_1Pf"
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// CHECK-DAG: "_ZGVeM32v__Z5add_1Pf"
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// CHECK-DAG: "_ZGVbN2v__Z5add_1Pf"
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// CHECK-DAG: "_ZGVcN4v__Z5add_1Pf"
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// CHECK-DAG: "_ZGVdN4v__Z5add_1Pf"
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// CHECK-DAG: "_ZGVeN8v__Z5add_1Pf"
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// CHECK-DAG: "_ZGVbM2va16va16vv__Z1hIiEvPT_S1_S1_S1_"
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// CHECK-DAG: "_ZGVbN2va16va16vv__Z1hIiEvPT_S1_S1_S1_"
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// CHECK-DAG: "_ZGVcM4va16va16vv__Z1hIiEvPT_S1_S1_S1_"
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// CHECK-DAG: "_ZGVcN4va16va16vv__Z1hIiEvPT_S1_S1_S1_"
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// CHECK-DAG: "_ZGVdM4va16va16vv__Z1hIiEvPT_S1_S1_S1_"
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// CHECK-DAG: "_ZGVdN4va16va16vv__Z1hIiEvPT_S1_S1_S1_"
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// CHECK-DAG: "_ZGVeM8va16va16vv__Z1hIiEvPT_S1_S1_S1_"
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// CHECK-DAG: "_ZGVeN8va16va16vv__Z1hIiEvPT_S1_S1_S1_"
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// CHECK-DAG: "_ZGVbM2va16va16vv__Z1hIfEvPT_S1_S1_S1_"
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// CHECK-DAG: "_ZGVbN2va16va16vv__Z1hIfEvPT_S1_S1_S1_"
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// CHECK-DAG: "_ZGVcM4va16va16vv__Z1hIfEvPT_S1_S1_S1_"
|
||||
// CHECK-DAG: "_ZGVcN4va16va16vv__Z1hIfEvPT_S1_S1_S1_"
|
||||
// CHECK-DAG: "_ZGVdM4va16va16vv__Z1hIfEvPT_S1_S1_S1_"
|
||||
// CHECK-DAG: "_ZGVdN4va16va16vv__Z1hIfEvPT_S1_S1_S1_"
|
||||
// CHECK-DAG: "_ZGVeM8va16va16vv__Z1hIfEvPT_S1_S1_S1_"
|
||||
// CHECK-DAG: "_ZGVeN8va16va16vv__Z1hIfEvPT_S1_S1_S1_"
|
||||
|
||||
// CHECK-DAG: "_ZGVbM4uus1__ZN2VV3addEii"
|
||||
// CHECK-DAG: "_ZGVbN4uus1__ZN2VV3addEii"
|
||||
// CHECK-DAG: "_ZGVcM8uus1__ZN2VV3addEii"
|
||||
// CHECK-DAG: "_ZGVcN8uus1__ZN2VV3addEii"
|
||||
// CHECK-DAG: "_ZGVdM8uus1__ZN2VV3addEii"
|
||||
// CHECK-DAG: "_ZGVdN8uus1__ZN2VV3addEii"
|
||||
// CHECK-DAG: "_ZGVeM16uus1__ZN2VV3addEii"
|
||||
// CHECK-DAG: "_ZGVeN16uus1__ZN2VV3addEii"
|
||||
|
||||
// CHECK-DAG: "_ZGVbM4lla16l4a4__ZN2VV6taddpfEPfRS0_"
|
||||
// CHECK-DAG: "_ZGVbN4lla16l4a4__ZN2VV6taddpfEPfRS0_"
|
||||
// CHECK-DAG: "_ZGVcM8lla16l4a4__ZN2VV6taddpfEPfRS0_"
|
||||
// CHECK-DAG: "_ZGVcN8lla16l4a4__ZN2VV6taddpfEPfRS0_"
|
||||
// CHECK-DAG: "_ZGVdM8lla16l4a4__ZN2VV6taddpfEPfRS0_"
|
||||
// CHECK-DAG: "_ZGVdN8lla16l4a4__ZN2VV6taddpfEPfRS0_"
|
||||
// CHECK-DAG: "_ZGVeM16lla16l4a4__ZN2VV6taddpfEPfRS0_"
|
||||
// CHECK-DAG: "_ZGVeN16lla16l4a4__ZN2VV6taddpfEPfRS0_"
|
||||
|
||||
// CHECK-DAG: "_ZGVbM4vvl8__ZN2VV4taddERA_iRi"
|
||||
// CHECK-DAG: "_ZGVbN4vvl8__ZN2VV4taddERA_iRi"
|
||||
// CHECK-DAG: "_ZGVcM8vvl8__ZN2VV4taddERA_iRi"
|
||||
// CHECK-DAG: "_ZGVcN8vvl8__ZN2VV4taddERA_iRi"
|
||||
// CHECK-DAG: "_ZGVdM8vvl8__ZN2VV4taddERA_iRi"
|
||||
// CHECK-DAG: "_ZGVdN8vvl8__ZN2VV4taddERA_iRi"
|
||||
// CHECK-DAG: "_ZGVeM16vvl8__ZN2VV4taddERA_iRi"
|
||||
// CHECK-DAG: "_ZGVeN16vvl8__ZN2VV4taddERA_iRi"
|
||||
// CHECK-DAG: "_ZGVbM4vva8v__ZN2VV4taddERA_iRi"
|
||||
// CHECK-DAG: "_ZGVbN4vva8v__ZN2VV4taddERA_iRi"
|
||||
// CHECK-DAG: "_ZGVcM8vva8v__ZN2VV4taddERA_iRi"
|
||||
// CHECK-DAG: "_ZGVcN8vva8v__ZN2VV4taddERA_iRi"
|
||||
// CHECK-DAG: "_ZGVdM8vva8v__ZN2VV4taddERA_iRi"
|
||||
// CHECK-DAG: "_ZGVdN8vva8v__ZN2VV4taddERA_iRi"
|
||||
// CHECK-DAG: "_ZGVeM16vva8v__ZN2VV4taddERA_iRi"
|
||||
// CHECK-DAG: "_ZGVeN16vva8v__ZN2VV4taddERA_iRi"
|
||||
|
||||
// CHECK-DAG: "_ZGVbM4vva32l16a16__ZN3TVVILi16EfE6taddpfEPfRS1_"
|
||||
// CHECK-DAG: "_ZGVbN4vva32l16a16__ZN3TVVILi16EfE6taddpfEPfRS1_"
|
||||
// CHECK-DAG: "_ZGVcM8vva32l16a16__ZN3TVVILi16EfE6taddpfEPfRS1_"
|
||||
// CHECK-DAG: "_ZGVcN8vva32l16a16__ZN3TVVILi16EfE6taddpfEPfRS1_"
|
||||
// CHECK-DAG: "_ZGVdM8vva32l16a16__ZN3TVVILi16EfE6taddpfEPfRS1_"
|
||||
// CHECK-DAG: "_ZGVdN8vva32l16a16__ZN3TVVILi16EfE6taddpfEPfRS1_"
|
||||
// CHECK-DAG: "_ZGVeM16vva32l16a16__ZN3TVVILi16EfE6taddpfEPfRS1_"
|
||||
// CHECK-DAG: "_ZGVeN16vva32l16a16__ZN3TVVILi16EfE6taddpfEPfRS1_"
|
||||
|
||||
// CHECK-DAG: "_ZGVbM4uu__ZN3TVVILi16EfE4taddEi"
|
||||
// CHECK-DAG: "_ZGVbN4uu__ZN3TVVILi16EfE4taddEi"
|
||||
// CHECK-DAG: "_ZGVcM8uu__ZN3TVVILi16EfE4taddEi"
|
||||
// CHECK-DAG: "_ZGVcN8uu__ZN3TVVILi16EfE4taddEi"
|
||||
// CHECK-DAG: "_ZGVdM8uu__ZN3TVVILi16EfE4taddEi"
|
||||
// CHECK-DAG: "_ZGVdN8uu__ZN3TVVILi16EfE4taddEi"
|
||||
// CHECK-DAG: "_ZGVeM16uu__ZN3TVVILi16EfE4taddEi"
|
||||
// CHECK-DAG: "_ZGVeN16uu__ZN3TVVILi16EfE4taddEi"
|
||||
// CHECK-DAG: "_ZGVbM4vv__ZN3TVVILi16EfE4taddEi"
|
||||
// CHECK-DAG: "_ZGVbN4vv__ZN3TVVILi16EfE4taddEi"
|
||||
// CHECK-DAG: "_ZGVcM8vv__ZN3TVVILi16EfE4taddEi"
|
||||
// CHECK-DAG: "_ZGVcN8vv__ZN3TVVILi16EfE4taddEi"
|
||||
// CHECK-DAG: "_ZGVdM8vv__ZN3TVVILi16EfE4taddEi"
|
||||
// CHECK-DAG: "_ZGVdN8vv__ZN3TVVILi16EfE4taddEi"
|
||||
// CHECK-DAG: "_ZGVeM16vv__ZN3TVVILi16EfE4taddEi"
|
||||
// CHECK-DAG: "_ZGVeN16vv__ZN3TVVILi16EfE4taddEi"
|
||||
|
||||
// CHECK-DAG: "_ZGVbM64va128l64__Z3fooILi64EEvRAT__iRPf"
|
||||
// CHECK-DAG: "_ZGVbN64va128l64__Z3fooILi64EEvRAT__iRPf"
|
||||
// CHECK-DAG: "_ZGVcM64va128l64__Z3fooILi64EEvRAT__iRPf"
|
||||
// CHECK-DAG: "_ZGVcN64va128l64__Z3fooILi64EEvRAT__iRPf"
|
||||
// CHECK-DAG: "_ZGVdM64va128l64__Z3fooILi64EEvRAT__iRPf"
|
||||
// CHECK-DAG: "_ZGVdN64va128l64__Z3fooILi64EEvRAT__iRPf"
|
||||
// CHECK-DAG: "_ZGVeM64va128l64__Z3fooILi64EEvRAT__iRPf"
|
||||
// CHECK-DAG: "_ZGVeN64va128l64__Z3fooILi64EEvRAT__iRPf"
|
||||
|
||||
// CHECK-DAG: "_ZGVbM4vv__Z3bar2VVPf"
|
||||
// CHECK-DAG: "_ZGVbN4vv__Z3bar2VVPf"
|
||||
// CHECK-DAG: "_ZGVcM8vv__Z3bar2VVPf"
|
||||
// CHECK-DAG: "_ZGVcN8vv__Z3bar2VVPf"
|
||||
// CHECK-DAG: "_ZGVdM8vv__Z3bar2VVPf"
|
||||
// CHECK-DAG: "_ZGVdN8vv__Z3bar2VVPf"
|
||||
// CHECK-DAG: "_ZGVeM16vv__Z3bar2VVPf"
|
||||
// CHECK-DAG: "_ZGVeN16vv__Z3bar2VVPf"
|
||||
// CHECK-DAG: "_ZGVbN4vva32__Z3bar2VVPf"
|
||||
// CHECK-DAG: "_ZGVcN8vva32__Z3bar2VVPf"
|
||||
// CHECK-DAG: "_ZGVdN8vva32__Z3bar2VVPf"
|
||||
// CHECK-DAG: "_ZGVeN16vva32__Z3bar2VVPf"
|
||||
|
||||
// CHECK-DAG: "_ZGVbM4vv__Z3baz2VVPi"
|
||||
// CHECK-DAG: "_ZGVbN4vv__Z3baz2VVPi"
|
||||
// CHECK-DAG: "_ZGVcM8vv__Z3baz2VVPi"
|
||||
// CHECK-DAG: "_ZGVcN8vv__Z3baz2VVPi"
|
||||
// CHECK-DAG: "_ZGVdM8vv__Z3baz2VVPi"
|
||||
// CHECK-DAG: "_ZGVdN8vv__Z3baz2VVPi"
|
||||
// CHECK-DAG: "_ZGVeM16vv__Z3baz2VVPi"
|
||||
// CHECK-DAG: "_ZGVeN16vv__Z3baz2VVPi"
|
||||
// CHECK-DAG: "_ZGVbN4vva16__Z3baz2VVPi"
|
||||
// CHECK-DAG: "_ZGVcN8vva16__Z3baz2VVPi"
|
||||
// CHECK-DAG: "_ZGVdN8vva16__Z3baz2VVPi"
|
||||
// CHECK-DAG: "_ZGVeN16vva16__Z3baz2VVPi"
|
||||
|
||||
// CHECK-DAG: "_ZGVbM2vv__Z3bay2VVRPd"
|
||||
// CHECK-DAG: "_ZGVbN2vv__Z3bay2VVRPd"
|
||||
// CHECK-DAG: "_ZGVcM4vv__Z3bay2VVRPd"
|
||||
// CHECK-DAG: "_ZGVcN4vv__Z3bay2VVRPd"
|
||||
// CHECK-DAG: "_ZGVdM4vv__Z3bay2VVRPd"
|
||||
// CHECK-DAG: "_ZGVdN4vv__Z3bay2VVRPd"
|
||||
// CHECK-DAG: "_ZGVeM8vv__Z3bay2VVRPd"
|
||||
// CHECK-DAG: "_ZGVeN8vv__Z3bay2VVRPd"
|
||||
// CHECK-DAG: "_ZGVbN2vva16__Z3bay2VVRPd"
|
||||
// CHECK-DAG: "_ZGVcN4vva16__Z3bay2VVRPd"
|
||||
// CHECK-DAG: "_ZGVdN4vva16__Z3bay2VVRPd"
|
||||
// CHECK-DAG: "_ZGVeN8vva16__Z3bay2VVRPd"
|
||||
|
||||
// CHECK-DAG: "_ZGVbM4us2u__Z3bax2VVPdi"
|
||||
// CHECK-DAG: "_ZGVcM8us2u__Z3bax2VVPdi"
|
||||
// CHECK-DAG: "_ZGVdM8us2u__Z3bax2VVPdi"
|
||||
// CHECK-DAG: "_ZGVeM16us2u__Z3bax2VVPdi"
|
||||
// CHECK-DAG: "_ZGVbM4vvv__Z3bax2VVPdi"
|
||||
// CHECK-DAG: "_ZGVbN4vvv__Z3bax2VVPdi"
|
||||
// CHECK-DAG: "_ZGVcM8vvv__Z3bax2VVPdi"
|
||||
// CHECK-DAG: "_ZGVcN8vvv__Z3bax2VVPdi"
|
||||
// CHECK-DAG: "_ZGVdM8vvv__Z3bax2VVPdi"
|
||||
// CHECK-DAG: "_ZGVdN8vvv__Z3bax2VVPdi"
|
||||
// CHECK-DAG: "_ZGVeM16vvv__Z3bax2VVPdi"
|
||||
// CHECK-DAG: "_ZGVeN16vvv__Z3bax2VVPdi"
|
||||
|
||||
// CHECK-DAG: "_ZGVbM4ua16vl1__Z3fooPffi"
|
||||
// CHECK-DAG: "_ZGVbN4ua16vl1__Z3fooPffi"
|
||||
// CHECK-DAG: "_ZGVcM8ua16vl1__Z3fooPffi"
|
||||
// CHECK-DAG: "_ZGVcN8ua16vl1__Z3fooPffi"
|
||||
// CHECK-DAG: "_ZGVdM8ua16vl1__Z3fooPffi"
|
||||
// CHECK-DAG: "_ZGVdN8ua16vl1__Z3fooPffi"
|
||||
// CHECK-DAG: "_ZGVeM16ua16vl1__Z3fooPffi"
|
||||
// CHECK-DAG: "_ZGVeN16ua16vl1__Z3fooPffi"
|
||||
|
||||
// CHECK-DAG: "_ZGVbN2v__Z3food"
|
||||
// CHECK-DAG: "_ZGVcN4v__Z3food"
|
||||
// CHECK-DAG: "_ZGVdN4v__Z3food"
|
||||
// CHECK-DAG: "_ZGVeN8v__Z3food"
|
||||
|
||||
// CHECK-NOT: "_ZGV{{.+}}__Z1fRA_i
|
||||
|
||||
#endif
|
||||
Loading…
Reference in New Issue