From c781c254124445259fbea3049cd32544afca1cb5 Mon Sep 17 00:00:00 2001
From: Thomas Symalla <thomas.symalla@amd.com>
Date: Mon, 18 Jan 2021 16:05:00 +0100
Subject: [PATCH] Implemented a MED3_S32 GIR opcode.

---
 llvm/lib/Target/AMDGPU/AMDGPUGISel.td                 | 1 +
 llvm/lib/Target/AMDGPU/AMDGPUPreLegalizerCombiner.cpp | 9 +++++++--
 llvm/lib/Target/AMDGPU/AMDGPURegisterBankInfo.cpp     | 1 +
 llvm/lib/Target/AMDGPU/SIInstructions.td              | 6 ++++++
 4 files changed, 15 insertions(+), 2 deletions(-)

diff --git a/llvm/lib/Target/AMDGPU/AMDGPUGISel.td b/llvm/lib/Target/AMDGPU/AMDGPUGISel.td
index d1e23e1c3f44..7e62fdfeeedc 100644
--- a/llvm/lib/Target/AMDGPU/AMDGPUGISel.td
+++ b/llvm/lib/Target/AMDGPU/AMDGPUGISel.td
@@ -175,6 +175,7 @@ def : GINodeEquiv<G_AMDGPU_CVT_F32_UBYTE2, AMDGPUcvt_f32_ubyte2>;
 def : GINodeEquiv<G_AMDGPU_CVT_F32_UBYTE3, AMDGPUcvt_f32_ubyte3>;
 
 def : GINodeEquiv<G_AMDGPU_CVT_PK_I16_I32, AMDGPUpk_i16_i32_impl>;
+def : GINodeEquiv<G_AMDGPU_MED3_S32, AMDGPUsmed3>;
 
 def : GINodeEquiv<G_AMDGPU_ATOMIC_CMPXCHG, AMDGPUatomic_cmp_swap>;
 def : GINodeEquiv<G_AMDGPU_BUFFER_LOAD, SIbuffer_load>;
diff --git a/llvm/lib/Target/AMDGPU/AMDGPUPreLegalizerCombiner.cpp b/llvm/lib/Target/AMDGPU/AMDGPUPreLegalizerCombiner.cpp
index f70fadbcb5f3..7cd368b11273 100644
--- a/llvm/lib/Target/AMDGPU/AMDGPUPreLegalizerCombiner.cpp
+++ b/llvm/lib/Target/AMDGPU/AMDGPUPreLegalizerCombiner.cpp
@@ -152,9 +152,14 @@ void AMDGPUPreLegalizerCombinerHelper::applyClampI64ToI16(
   Register MedDst = MRI.createVirtualRegister(&AMDGPU::VGPR_32RegClass);
   MRI.setType(MedDst, S32);
 
-  B.buildInstr(AMDGPU::V_MED3_I32,
+  Register CvtDst32 = MRI.createVirtualRegister(&AMDGPU::VGPR_32RegClass);
+  MRI.setType(CvtDst32, S32);
+
+  B.buildBitcast(CvtDst32, CvtDst);
+
+  B.buildInstr(AMDGPU::G_AMDGPU_MED3_S32,
     {MedDst},
-    {MinBoundaryDst.getReg(0), CvtDst, MaxBoundaryDst.getReg(0)},
+    {MinBoundaryDst.getReg(0), CvtDst32, MaxBoundaryDst.getReg(0)},
     MI.getFlags());
   
   Register TruncDst = MRI.createGenericVirtualRegister(LLT::scalar(16));
diff --git a/llvm/lib/Target/AMDGPU/AMDGPURegisterBankInfo.cpp b/llvm/lib/Target/AMDGPU/AMDGPURegisterBankInfo.cpp
index d63090f36148..8c1cac6f15e2 100644
--- a/llvm/lib/Target/AMDGPU/AMDGPURegisterBankInfo.cpp
+++ b/llvm/lib/Target/AMDGPU/AMDGPURegisterBankInfo.cpp
@@ -3622,6 +3622,7 @@ AMDGPURegisterBankInfo::getInstrMapping(const MachineInstr &MI) const {
   case AMDGPU::G_AMDGPU_CVT_F32_UBYTE2:
   case AMDGPU::G_AMDGPU_CVT_F32_UBYTE3:
   case AMDGPU::G_AMDGPU_CVT_PK_I16_I32:
+  case AMDGPU::G_AMDGPU_MED3_S32:
     return getDefaultMappingVOP(MI);
   case AMDGPU::G_UMULH:
   case AMDGPU::G_SMULH: {
diff --git a/llvm/lib/Target/AMDGPU/SIInstructions.td b/llvm/lib/Target/AMDGPU/SIInstructions.td
index 59e3cad72fce..184f24d8908d 100644
--- a/llvm/lib/Target/AMDGPU/SIInstructions.td
+++ b/llvm/lib/Target/AMDGPU/SIInstructions.td
@@ -2581,6 +2581,12 @@ def G_AMDGPU_CVT_PK_I16_I32 : AMDGPUGenericInstruction {
   let hasSideEffects = 0;
 }
 
+def G_AMDGPU_MED3_S32 : AMDGPUGenericInstruction {
+  let OutOperandList = (outs type0:$dst);
+  let InOperandList = (ins type0:$src0, type0:$src1, type0:$src2);
+  let hasSideEffects = 0;
+}
+
 // Atomic cmpxchg. $cmpval ad $newval are packed in a single vector
 // operand Expects a MachineMemOperand in addition to explicit
 // operands.