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Add support for the isLoad and isStore flags, needed by the instruction scheduler 

llvm-svn: 16555
This commit is contained in:
Nate Begeman 2004-09-28 21:29:00 +00:00
parent 996ddbc98e
commit c762ab723b
1 changed files with 2 additions and 0 deletions
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2
llvm/lib/Target/Target.td
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@ -130,6 +130,8 @@ class Instruction {
bit isBranch = 0; // Is this instruction a branch instruction?
bit isBarrier = 0; // Can control flow fall through this instruction?
bit isCall = 0; // Is this instruction a call instruction?
bit isLoad = 0; // Is this instruction a load instruction?
bit isStore = 0; // Is this instruction a store instruction?
bit isTwoAddress = 0; // Is this a two address instruction?
bit isTerminator = 0; // Is this part of the terminator for a basic block?
bit hasDelaySlot = 0; // Does this instruction have an delay slot?