forked from OSchip/llvm-project
[AArch64] Precommit extending load tests for D104782. NFC.
This commit is contained in:
Sjoerd Meijer
parent
cc05418d98
commit
c74aea4663
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@ -0,0 +1,145 @@
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; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc < %s -verify-machineinstrs -mtriple=aarch64-none-linux-gnu -mattr=+neon | FileCheck %s --check-prefix=LE
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; RUN: llc < %s -verify-machineinstrs -mtriple=aarch64_be-none-linux-gnu -mattr=+neon | FileCheck %s --check-prefix=BE
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define <4 x i32> @fsext_v4i32(<4 x i8>* %a) {
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; LE-LABEL: fsext_v4i32:
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; LE: // %bb.0:
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; LE-NEXT: ldrsb w8, [x0]
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; LE-NEXT: ldrsb w9, [x0, #1]
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; LE-NEXT: ldrsb w10, [x0, #2]
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; LE-NEXT: ldrsb w11, [x0, #3]
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; LE-NEXT: fmov s0, w8
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; LE-NEXT: mov v0.s[1], w9
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; LE-NEXT: mov v0.s[2], w10
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; LE-NEXT: mov v0.s[3], w11
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; LE-NEXT: ret
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;
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; BE-LABEL: fsext_v4i32:
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; BE: // %bb.0:
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; BE-NEXT: ldrsb w8, [x0]
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; BE-NEXT: ldrsb w9, [x0, #1]
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; BE-NEXT: ldrsb w10, [x0, #2]
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; BE-NEXT: ldrsb w11, [x0, #3]
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; BE-NEXT: fmov s0, w8
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; BE-NEXT: mov v0.s[1], w9
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; BE-NEXT: mov v0.s[2], w10
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; BE-NEXT: mov v0.s[3], w11
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; BE-NEXT: rev64 v0.4s, v0.4s
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; BE-NEXT: ext v0.16b, v0.16b, v0.16b, #8
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; BE-NEXT: ret
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%x = load <4 x i8>, <4 x i8>* %a
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%y = sext <4 x i8> %x to <4 x i32>
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ret <4 x i32> %y
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}
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define <4 x i32> @fzext_v4i32(<4 x i8>* %a) {
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; LE-LABEL: fzext_v4i32:
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; LE: // %bb.0:
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; LE-NEXT: ldrb w8, [x0]
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; LE-NEXT: ldrb w9, [x0, #1]
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; LE-NEXT: ldrb w10, [x0, #2]
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; LE-NEXT: ldrb w11, [x0, #3]
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; LE-NEXT: fmov s0, w8
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; LE-NEXT: mov v0.s[1], w9
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; LE-NEXT: mov v0.s[2], w10
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; LE-NEXT: mov v0.s[3], w11
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; LE-NEXT: ret
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;
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; BE-LABEL: fzext_v4i32:
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; BE: // %bb.0:
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; BE-NEXT: ldrb w8, [x0]
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; BE-NEXT: ldrb w9, [x0, #1]
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; BE-NEXT: ldrb w10, [x0, #2]
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; BE-NEXT: ldrb w11, [x0, #3]
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; BE-NEXT: fmov s0, w8
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; BE-NEXT: mov v0.s[1], w9
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; BE-NEXT: mov v0.s[2], w10
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; BE-NEXT: mov v0.s[3], w11
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; BE-NEXT: rev64 v0.4s, v0.4s
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; BE-NEXT: ext v0.16b, v0.16b, v0.16b, #8
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; BE-NEXT: ret
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%x = load <4 x i8>, <4 x i8>* %a
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%y = zext <4 x i8> %x to <4 x i32>
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ret <4 x i32> %y
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}
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define i32 @loadExt.i32(<4 x i8>* %ref) {
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; CHECK-LABEL: loadExt.i32:
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; CHECK: ldrb
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; LE-LABEL: loadExt.i32:
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; LE: // %bb.0:
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; LE-NEXT: ldrb w0, [x0]
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; LE-NEXT: ret
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;
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; BE-LABEL: loadExt.i32:
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; BE: // %bb.0:
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; BE-NEXT: ldrb w0, [x0]
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; BE-NEXT: ret
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%a = load <4 x i8>, <4 x i8>* %ref
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%vecext = extractelement <4 x i8> %a, i32 0
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%conv = zext i8 %vecext to i32
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ret i32 %conv
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}
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define <4 x i16> @fsext_v4i16(<4 x i8>* %a) {
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; LE-LABEL: fsext_v4i16:
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; LE: // %bb.0:
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; LE-NEXT: ldrsb w8, [x0]
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; LE-NEXT: ldrsb w9, [x0, #1]
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; LE-NEXT: ldrsb w10, [x0, #2]
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; LE-NEXT: ldrsb w11, [x0, #3]
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; LE-NEXT: fmov s0, w8
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; LE-NEXT: mov v0.h[1], w9
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; LE-NEXT: mov v0.h[2], w10
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; LE-NEXT: mov v0.h[3], w11
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; LE-NEXT: // kill: def $d0 killed $d0 killed $q0
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; LE-NEXT: ret
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;
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; BE-LABEL: fsext_v4i16:
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; BE: // %bb.0:
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; BE-NEXT: ldrsb w8, [x0]
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; BE-NEXT: ldrsb w9, [x0, #1]
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; BE-NEXT: ldrsb w10, [x0, #2]
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; BE-NEXT: ldrsb w11, [x0, #3]
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; BE-NEXT: fmov s0, w8
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; BE-NEXT: mov v0.h[1], w9
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; BE-NEXT: mov v0.h[2], w10
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; BE-NEXT: mov v0.h[3], w11
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; BE-NEXT: rev64 v0.4h, v0.4h
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; BE-NEXT: ret
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%x = load <4 x i8>, <4 x i8>* %a
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%y = sext <4 x i8> %x to <4 x i16>
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ret <4 x i16> %y
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}
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define <4 x i16> @fzext_v4i16(<4 x i8>* %a) {
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; LE-LABEL: fzext_v4i16:
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; LE: // %bb.0:
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; LE-NEXT: ldrb w8, [x0]
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; LE-NEXT: ldrb w9, [x0, #1]
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; LE-NEXT: ldrb w10, [x0, #2]
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; LE-NEXT: ldrb w11, [x0, #3]
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; LE-NEXT: fmov s0, w8
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; LE-NEXT: mov v0.h[1], w9
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; LE-NEXT: mov v0.h[2], w10
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; LE-NEXT: mov v0.h[3], w11
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; LE-NEXT: // kill: def $d0 killed $d0 killed $q0
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; LE-NEXT: ret
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;
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; BE-LABEL: fzext_v4i16:
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; BE: // %bb.0:
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; BE-NEXT: ldrb w8, [x0]
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; BE-NEXT: ldrb w9, [x0, #1]
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; BE-NEXT: ldrb w10, [x0, #2]
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; BE-NEXT: ldrb w11, [x0, #3]
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; BE-NEXT: fmov s0, w8
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; BE-NEXT: mov v0.h[1], w9
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; BE-NEXT: mov v0.h[2], w10
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; BE-NEXT: mov v0.h[3], w11
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; BE-NEXT: rev64 v0.4h, v0.4h
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; BE-NEXT: ret
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%x = load <4 x i8>, <4 x i8>* %a
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%y = zext <4 x i8> %x to <4 x i16>
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ret <4 x i16> %y
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}
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@ -38,30 +38,3 @@ define void @truncStore.v8i16(<8 x i16> %a, <8 x i8>* %result) {
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store <8 x i8> %b, <8 x i8>* %result
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ret void
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}
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; A vector LoadExt can not be selected.
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; Test a vector load IR and a sext/zext IR can be selected correctly.
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define <4 x i32> @loadSExt.v4i8(<4 x i8>* %ref) {
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; CHECK-LABEL: loadSExt.v4i8:
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; CHECK: ldrsb
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%a = load <4 x i8>, <4 x i8>* %ref
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%conv = sext <4 x i8> %a to <4 x i32>
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ret <4 x i32> %conv
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}
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define <4 x i32> @loadZExt.v4i8(<4 x i8>* %ref) {
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; CHECK-LABEL: loadZExt.v4i8:
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; CHECK: ldrb
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%a = load <4 x i8>, <4 x i8>* %ref
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%conv = zext <4 x i8> %a to <4 x i32>
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ret <4 x i32> %conv
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}
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define i32 @loadExt.i32(<4 x i8>* %ref) {
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; CHECK-LABEL: loadExt.i32:
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; CHECK: ldrb
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%a = load <4 x i8>, <4 x i8>* %ref
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%vecext = extractelement <4 x i8> %a, i32 0
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%conv = zext i8 %vecext to i32
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ret i32 %conv
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}
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