[X86] Correct the implementation of ud1(a.k.a. ud2b) instruction.

We were missing the modrm byte this instruction has according
to current Intel SDM. Experiments with gcc indicate that different
modrm values are chosen based on 2 operands so I've added those
as well.

I think our previous implementation was based on an older behavior of
binutils that has since been changed.

llvm/lib/Target/X86/X86InstrInfo.td

@@ -3166,6 +3166,9 @@ def : MnemonicAlias<"smovl", "movsl", "att">;
 def : MnemonicAlias<"smovq", "movsq", "att">;
 
 def : MnemonicAlias<"ud2a",  "ud2",  "att">;
+def : MnemonicAlias<"ud2bw", "ud1w", "att">;
+def : MnemonicAlias<"ud2bl", "ud1l", "att">;
+def : MnemonicAlias<"ud2bq", "ud1q", "att">;
 def : MnemonicAlias<"verrw", "verr", "att">;
 
 // MS recognizes 'xacquire'/'xrelease' as 'acquire'/'release'

llvm/lib/Target/X86/X86InstrSystem.td

@@ -23,7 +23,20 @@ def RDTSCP : I<0x01, MRM_F9, (outs), (ins), "rdtscp", []>, TB;
 
 let mayLoad = 1, mayStore = 0, hasSideEffects = 1, isTrap = 1 in {
   def TRAP    : I<0x0B, RawFrm, (outs), (ins), "ud2", [(trap)]>, TB;
-  def UD2B    : I<0xB9, RawFrm, (outs), (ins), "ud2b", []>, TB;
+
+  def UD1Wm   : I<0xB9, MRMSrcMem, (outs), (ins GR16:$src1, i16mem:$src2),
+                  "ud1{w} {$src2, $src1|$src1, $src2}", []>, TB, OpSize16;
+  def UD1Lm   : I<0xB9, MRMSrcMem, (outs), (ins GR32:$src1, i32mem:$src2),
+                  "ud1{l} {$src2, $src1|$src1, $src2}", []>, TB, OpSize32;
+  def UD1Qm   : RI<0xB9, MRMSrcMem, (outs), (ins GR64:$src1, i64mem:$src2),
+                   "ud1{q} {$src2, $src1|$src1, $src2}", []>, TB;
+
+  def UD1Wr   : I<0xB9, MRMSrcReg, (outs), (ins GR16:$src1, GR16:$src2),
+                  "ud1{w} {$src2, $src1|$src1, $src2}", []>, TB, OpSize16;
+  def UD1Lr   : I<0xB9, MRMSrcReg, (outs), (ins GR32:$src1, GR32:$src2),
+                  "ud1{l} {$src2, $src1|$src1, $src2}", []>, TB, OpSize32;
+  def UD1Qr   : RI<0xB9, MRMSrcReg, (outs), (ins GR64:$src1, GR64:$src2),
+                   "ud1{q} {$src2, $src1|$src1, $src2}", []>, TB;
 }
 
 def HLT : I<0xF4, RawFrm, (outs), (ins), "hlt", []>;

llvm/test/MC/Disassembler/X86/x86-16.txt

@@ -699,8 +699,8 @@
 # CHECK: ud2
 0x0f 0x0b
 
-# CHECK: ud2b
-0x0f 0xb9
+# CHECK: ud1w %ax, %ax
+0x0f 0xb9 0xc0
 
 # CHECK: loope
 0xe1 0x00

llvm/test/MC/X86/x86-16.s

@@ -789,9 +789,13 @@ pshufw $90, %mm4, %mm0
 // CHECK:  encoding: [0x0f,0x0b]
         	ud2a
 
-// CHECK: ud2b
-// CHECK:  encoding: [0x0f,0xb9]
-        	ud2b
+// CHECK: ud1w %ax, %ax
+// CHECK:  encoding: [0x0f,0xb9,0xc0]
+        	ud1 %ax, %ax
+
+// CHECK: ud1w %ax, %ax
+// CHECK:  encoding: [0x0f,0xb9,0xc0]
+        	ud2b %ax, %ax
 
 // CHECK: loope 0
 // CHECK: encoding: [0xe1,A]

llvm/test/MC/X86/x86-32.s

@@ -918,9 +918,13 @@ pshufw $90, %mm4, %mm0
 // CHECK:  encoding: [0x0f,0x0b]
         	ud2a
 
-// CHECK: ud2b
-// CHECK:  encoding: [0x0f,0xb9]
-        	ud2b
+// CHECK: ud1l %edx, %edi
+// CHECK:  encoding: [0x0f,0xb9,0xfa]
+        	ud1 %edx, %edi
+
+// CHECK: ud1l (%ebx), %ecx
+// CHECK:  encoding: [0x0f,0xb9,0x0b]
+        	ud2b (%ebx), %ecx
 
 // CHECK: loope 0
 // CHECK: encoding: [0xe1,A]

llvm/test/MC/X86/x86-64.s

@@ -1892,3 +1892,11 @@ xsusldtrk
 // CHECK: xresldtrk
 // CHECK: encoding: [0xf2,0x0f,0x01,0xe9]
 xresldtrk
+
+// CHECK: ud1q %rdx, %rdi
+// CHECK:  encoding: [0x48,0x0f,0xb9,0xfa]
+ud1 %rdx, %rdi
+
+// CHECK: ud1q (%rbx), %rcx
+// CHECK:  encoding: [0x48,0x0f,0xb9,0x0b]
+ud2b (%rbx), %rcx