forked from OSchip/llvm-project
Rewrite fast-isel integer cast handling to handle more cases, and to be simpler and more consistent.
The practical effects here are that x86-64 fast-isel can now handle trunc from i8 to i1, and ARM fast-isel can handle many more constructs involving integers narrower than 32 bits (including loads, stores, and many integer casts). rdar://9437928 . llvm-svn: 132099
This commit is contained in:
Eli Friedman
parent
fa63d3096d
commit
c70355195c
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@ -111,8 +111,8 @@ unsigned FastISel::getRegForValue(const Value *V) {
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// of whether FastISel can handle them.
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MVT VT = RealVT.getSimpleVT();
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if (!TLI.isTypeLegal(VT)) {
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// Promote MVT::i1 to a legal type though, because it's common and easy.
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if (VT == MVT::i1)
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// Handle integer promotions, though, because they're common and easy.
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if (VT == MVT::i1 || VT == MVT::i8 || VT == MVT::i16)
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VT = TLI.getTypeToTransformTo(V->getContext(), VT).getSimpleVT();
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else
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return 0;
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@ -653,20 +653,12 @@ bool FastISel::SelectCast(const User *I, unsigned Opcode) {
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// Unhandled type. Halt "fast" selection and bail.
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return false;
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// Check if the destination type is legal. Or as a special case,
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// it may be i1 if we're doing a truncate because that's
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// easy and somewhat common.
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// Check if the destination type is legal.
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if (!TLI.isTypeLegal(DstVT))
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if (DstVT != MVT::i1 || Opcode != ISD::TRUNCATE)
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// Unhandled type. Halt "fast" selection and bail.
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return false;
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// Check if the source operand is legal. Or as a special case,
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// it may be i1 if we're doing zero-extension because that's
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// easy and somewhat common.
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// Check if the source operand is legal.
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if (!TLI.isTypeLegal(SrcVT))
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if (SrcVT != MVT::i1 || Opcode != ISD::ZERO_EXTEND)
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// Unhandled type. Halt "fast" selection and bail.
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return false;
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unsigned InputReg = getRegForValue(I->getOperand(0));
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@ -676,18 +668,6 @@ bool FastISel::SelectCast(const User *I, unsigned Opcode) {
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bool InputRegIsKill = hasTrivialKill(I->getOperand(0));
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// If the operand is i1, arrange for the high bits in the register to be zero.
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if (SrcVT == MVT::i1) {
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SrcVT = TLI.getTypeToTransformTo(I->getContext(), SrcVT);
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InputReg = FastEmitZExtFromI1(SrcVT.getSimpleVT(), InputReg, InputRegIsKill);
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if (!InputReg)
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return false;
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InputRegIsKill = true;
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}
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// If the result is i1, truncate to the target's type for i1 first.
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if (DstVT == MVT::i1)
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DstVT = TLI.getTypeToTransformTo(I->getContext(), DstVT);
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unsigned ResultReg = FastEmit_r(SrcVT.getSimpleVT(),
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DstVT.getSimpleVT(),
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Opcode,
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@ -167,6 +167,7 @@ class ARMFastISel : public FastISel {
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bool SelectCall(const Instruction *I);
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bool SelectSelect(const Instruction *I);
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bool SelectRet(const Instruction *I);
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bool SelectIntCast(const Instruction *I);
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// Utility routines.
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private:
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@ -1129,7 +1130,7 @@ bool ARMFastISel::SelectBranch(const Instruction *I) {
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} else if (TruncInst *TI = dyn_cast<TruncInst>(BI->getCondition())) {
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MVT SourceVT;
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if (TI->hasOneUse() && TI->getParent() == I->getParent() &&
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(isTypeLegal(TI->getOperand(0)->getType(), SourceVT))) {
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(isLoadTypeLegal(TI->getOperand(0)->getType(), SourceVT))) {
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unsigned TstOpc = isThumb ? ARM::t2TSTri : ARM::TSTri;
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unsigned OpReg = getRegForValue(TI->getOperand(0));
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AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL,
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@ -1948,6 +1949,77 @@ bool ARMFastISel::SelectCall(const Instruction *I) {
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}
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bool ARMFastISel::SelectIntCast(const Instruction *I) {
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// On ARM, in general, integer casts don't involve legal types; this code
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// handles promotable integers. The high bits for a type smaller than
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// the register size are assumed to be undefined.
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const Type *DestTy = I->getType();
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Value *Op = I->getOperand(0);
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const Type *SrcTy = Op->getType();
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EVT SrcVT, DestVT;
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SrcVT = TLI.getValueType(SrcTy, true);
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DestVT = TLI.getValueType(DestTy, true);
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if (isa<TruncInst>(I)) {
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if (SrcVT != MVT::i32 && SrcVT != MVT::i16 && SrcVT != MVT::i8)
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return false;
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if (DestVT != MVT::i16 && DestVT != MVT::i8 && DestVT != MVT::i1)
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return false;
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unsigned SrcReg = getRegForValue(Op);
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if (!SrcReg) return false;
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// Because the high bits are undefined, a truncate doesn't generate
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// any code.
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UpdateValueMap(I, SrcReg);
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return true;
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}
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if (DestVT != MVT::i32 && DestVT != MVT::i16 && DestVT != MVT::i8)
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return false;
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unsigned Opc;
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bool isZext = isa<ZExtInst>(I);
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bool isBoolZext = false;
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switch (SrcVT.getSimpleVT().SimpleTy) {
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default: return false;
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case MVT::i16:
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if (isZext)
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Opc = isThumb ? ARM::t2UXTHr : ARM::UXTHr;
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else
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Opc = isThumb ? ARM::t2SXTHr : ARM::SXTHr;
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break;
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case MVT::i8:
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if (isZext)
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Opc = isThumb ? ARM::t2UXTBr : ARM::UXTBr;
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else
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Opc = isThumb ? ARM::t2SXTBr : ARM::SXTBr;
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break;
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case MVT::i1:
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if (isZext) {
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Opc = isThumb ? ARM::t2ANDri : ARM::ANDri;
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isBoolZext = true;
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break;
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}
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return false;
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}
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// FIXME: We could save an instruction in many cases by special-casing
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// load instructions.
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unsigned SrcReg = getRegForValue(Op);
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if (!SrcReg) return false;
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unsigned DestReg = createResultReg(TLI.getRegClassFor(MVT::i32));
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MachineInstrBuilder MIB;
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MIB = BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(Opc), DestReg)
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.addReg(SrcReg);
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if (isBoolZext)
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MIB.addImm(1);
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AddOptionalDefs(MIB);
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UpdateValueMap(I, DestReg);
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return true;
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}
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// TODO: SoftFP support.
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bool ARMFastISel::TargetSelectInstruction(const Instruction *I) {
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@ -1985,6 +2057,10 @@ bool ARMFastISel::TargetSelectInstruction(const Instruction *I) {
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return SelectSelect(I);
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case Instruction::Ret:
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return SelectRet(I);
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case Instruction::Trunc:
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case Instruction::ZExt:
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case Instruction::SExt:
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return SelectIntCast(I);
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default: break;
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}
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return false;
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@ -936,18 +936,31 @@ bool X86FastISel::X86SelectCmp(const Instruction *I) {
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bool X86FastISel::X86SelectZExt(const Instruction *I) {
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// Handle zero-extension from i1 to i8, which is common.
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if (I->getType()->isIntegerTy(8) &&
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I->getOperand(0)->getType()->isIntegerTy(1)) {
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if (!I->getOperand(0)->getType()->isIntegerTy(1))
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return false;
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EVT DstVT = TLI.getValueType(I->getType());
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if (!TLI.isTypeLegal(DstVT))
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return false;
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unsigned ResultReg = getRegForValue(I->getOperand(0));
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if (ResultReg == 0) return false;
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if (ResultReg == 0)
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return false;
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// Set the high bits to zero.
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ResultReg = FastEmitZExtFromI1(MVT::i8, ResultReg, /*TODO: Kill=*/false);
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if (ResultReg == 0) return false;
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UpdateValueMap(I, ResultReg);
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return true;
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if (ResultReg == 0)
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return false;
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if (DstVT != MVT::i8) {
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ResultReg = FastEmit_r(MVT::i8, DstVT.getSimpleVT(), ISD::ZERO_EXTEND,
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ResultReg, /*Kill=*/true);
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if (ResultReg == 0)
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return false;
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}
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return false;
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UpdateValueMap(I, ResultReg);
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return true;
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}
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@ -1229,18 +1242,13 @@ bool X86FastISel::X86SelectFPTrunc(const Instruction *I) {
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}
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bool X86FastISel::X86SelectTrunc(const Instruction *I) {
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if (Subtarget->is64Bit())
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// All other cases should be handled by the tblgen generated code.
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return false;
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EVT SrcVT = TLI.getValueType(I->getOperand(0)->getType());
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EVT DstVT = TLI.getValueType(I->getType());
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// This code only handles truncation to byte right now.
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// This code only handles truncation to byte.
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if (DstVT != MVT::i8 && DstVT != MVT::i1)
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// All other cases should be handled by the tblgen generated code.
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return false;
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if (SrcVT != MVT::i16 && SrcVT != MVT::i32)
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// All other cases should be handled by the tblgen generated code.
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if (!TLI.isTypeLegal(SrcVT))
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return false;
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unsigned InputReg = getRegForValue(I->getOperand(0));
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@ -1248,16 +1256,26 @@ bool X86FastISel::X86SelectTrunc(const Instruction *I) {
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// Unhandled operand. Halt "fast" selection and bail.
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return false;
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if (SrcVT == MVT::i8) {
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// Truncate from i8 to i1; no code needed.
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UpdateValueMap(I, InputReg);
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return true;
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}
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if (!Subtarget->is64Bit()) {
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// If we're on x86-32; we can't extract an i8 from a general register.
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// First issue a copy to GR16_ABCD or GR32_ABCD.
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const TargetRegisterClass *CopyRC = (SrcVT == MVT::i16)
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? X86::GR16_ABCDRegisterClass : X86::GR32_ABCDRegisterClass;
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unsigned CopyReg = createResultReg(CopyRC);
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BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(TargetOpcode::COPY),
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CopyReg).addReg(InputReg);
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InputReg = CopyReg;
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}
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// Then issue an extract_subreg.
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// Issue an extract_subreg.
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unsigned ResultReg = FastEmitInst_extractsubreg(MVT::i8,
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CopyReg, /*Kill=*/true,
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InputReg, /*Kill=*/true,
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X86::sub_8bit);
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if (!ResultReg)
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return false;
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@ -61,3 +61,74 @@ b3:
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; THUMB: orr {{.*}} #4
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; ARM: orr {{.*}} #4
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}
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define void @test3(i32 %tmp, i32* %ptr1, i16* %ptr2, i8* %ptr3) nounwind {
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; THUMB: test3:
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; ARM: test3:
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bb1:
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%a1 = trunc i32 %tmp to i16
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%a2 = trunc i16 %a1 to i8
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%a3 = trunc i8 %a2 to i1
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%a4 = zext i1 %a3 to i8
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store i8 %a4, i8* %ptr3
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%a5 = zext i8 %a4 to i16
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store i16 %a5, i16* %ptr2
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%a6 = zext i16 %a5 to i32
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store i32 %a6, i32* %ptr1
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br label %bb2
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; THUMB: and
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; THUMB: strb
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; THUMB: uxtb
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; THUMB: strh
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; THUMB: uxth
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; ARM: and
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; ARM: strb
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; ARM: uxtb
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; ARM: strh
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; ARM: uxth
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bb2:
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%b1 = trunc i32 %tmp to i16
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%b2 = trunc i16 %b1 to i8
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store i8 %b2, i8* %ptr3
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%b3 = sext i8 %b2 to i16
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store i16 %b3, i16* %ptr2
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%b4 = sext i16 %b3 to i32
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store i32 %b4, i32* %ptr1
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br label %bb3
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; THUMB: strb
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; THUMB: sxtb
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; THUMB: strh
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; THUMB: sxth
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; ARM: strb
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; ARM: sxtb
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; ARM: strh
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; ARM: sxth
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bb3:
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%c1 = load i8* %ptr3
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%c2 = load i16* %ptr2
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%c3 = load i32* %ptr1
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%c4 = zext i8 %c1 to i32
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%c5 = sext i16 %c2 to i32
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%c6 = add i32 %c4, %c5
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%c7 = sub i32 %c3, %c6
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store i32 %c7, i32* %ptr1
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ret void
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; THUMB: ldrb
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; THUMB: ldrh
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; THUMB: uxtb
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; THUMB: sxth
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; THUMB: add
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; THUMB: sub
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; ARM: ldrb
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; ARM: ldrh
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; ARM: uxtb
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; ARM: sxth
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; ARM: add
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; ARM: sub
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}
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@ -1,14 +1,15 @@
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; RUN: llc < %s -march=x86 -fast-isel | FileCheck %s
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; RUN: llc < %s -march=x86 -fast-isel -fast-isel-abort | FileCheck %s
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; RUN: llc < %s -march=x86-64 -fast-isel -fast-isel-abort | FileCheck %s
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declare i64 @test1a(i64)
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declare i32 @test1a(i32)
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define i32 @test1(i64 %x) nounwind {
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define i32 @test1(i32 %x) nounwind {
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; CHECK: test1:
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; CHECK: andb $1, %
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%y = add i64 %x, -3
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%t = call i64 @test1a(i64 %y)
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%s = mul i64 %t, 77
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%z = trunc i64 %s to i1
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%y = add i32 %x, -3
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%t = call i32 @test1a(i32 %y)
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%s = mul i32 %t, 77
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%z = trunc i32 %s to i1
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br label %next
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next: ; preds = %0
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