forked from OSchip/llvm-project
Fix some style issues in PBQP. Patch by David Blaikie.
llvm-svn: 118883
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cabd1b71c7
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@ -238,11 +238,13 @@ std::auto_ptr<PBQPRAProblem> PBQPBuilder::build(MachineFunction *mf,
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unsigned preg = *pregItr;
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const LiveInterval *pregLI = &lis->getInterval(preg);
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if (pregLI->empty())
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if (pregLI->empty()) {
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continue;
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}
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if (!vregLI->overlaps(*pregLI))
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if (!vregLI->overlaps(*pregLI)) {
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continue;
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}
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// Remove the register from the allowed set.
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VRAllowed::iterator eraseItr =
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@ -318,10 +320,10 @@ void PBQPBuilder::addInterferenceCosts(
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assert(costMat.getRows() == vr1Allowed.size() + 1 && "Matrix height mismatch.");
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assert(costMat.getCols() == vr2Allowed.size() + 1 && "Matrix width mismatch.");
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for (unsigned i = 0; i < vr1Allowed.size(); ++i) {
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for (unsigned i = 0; i != vr1Allowed.size(); ++i) {
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unsigned preg1 = vr1Allowed[i];
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for (unsigned j = 0; j < vr2Allowed.size(); ++j) {
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for (unsigned j = 0; j != vr2Allowed.size(); ++j) {
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unsigned preg2 = vr2Allowed[j];
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if (tri->regsOverlap(preg1, preg2)) {
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@ -355,11 +357,13 @@ std::auto_ptr<PBQPRAProblem> PBQPBuilderWithCoalescing::build(
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miItr != miEnd; ++miItr) {
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const MachineInstr *mi = &*miItr;
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if (!cp.setRegisters(mi))
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if (!cp.setRegisters(mi)) {
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continue; // Not coalescable.
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}
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if (cp.getSrcReg() == cp.getDstReg())
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if (cp.getSrcReg() == cp.getDstReg()) {
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continue; // Already coalesced.
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}
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unsigned dst = cp.getDstReg(),
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src = cp.getSrcReg();
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@ -372,13 +376,15 @@ std::auto_ptr<PBQPRAProblem> PBQPBuilderWithCoalescing::build(
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loopInfo->getLoopDepth(mbb));
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if (cp.isPhys()) {
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if (!lis->isAllocatable(dst))
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if (!lis->isAllocatable(dst)) {
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continue;
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}
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const PBQPRAProblem::AllowedSet &allowed = p->getAllowedSet(src);
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unsigned pregOpt = 0;
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while (pregOpt < allowed.size() && allowed[pregOpt] != dst)
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while (pregOpt < allowed.size() && allowed[pregOpt] != dst) {
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++pregOpt;
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}
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if (pregOpt < allowed.size()) {
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++pregOpt; // +1 to account for spill option.
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PBQP::Graph::NodeItr node = p->getNodeForVReg(src);
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@ -425,9 +431,9 @@ void PBQPBuilderWithCoalescing::addVirtRegCoalesce(
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assert(costMat.getRows() == vr1Allowed.size() + 1 && "Size mismatch.");
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assert(costMat.getCols() == vr2Allowed.size() + 1 && "Size mismatch.");
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for (unsigned i = 0; i < vr1Allowed.size(); ++i) {
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for (unsigned i = 0; i != vr1Allowed.size(); ++i) {
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unsigned preg1 = vr1Allowed[i];
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for (unsigned j = 0; j < vr2Allowed.size(); ++j) {
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for (unsigned j = 0; j != vr2Allowed.size(); ++j) {
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unsigned preg2 = vr2Allowed[j];
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if (preg1 == preg2) {
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@ -473,8 +479,7 @@ void RegAllocPBQP::findVRegIntervalsToAlloc() {
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// finalizeAlloc.
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if (!li->empty()) {
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vregsToAlloc.insert(li->reg);
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}
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else {
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} else {
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emptyIntervalVRegs.insert(li->reg);
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}
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}
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@ -484,18 +489,20 @@ void RegAllocPBQP::addStackInterval(const LiveInterval *spilled,
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MachineRegisterInfo* mri) {
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int stackSlot = vrm->getStackSlot(spilled->reg);
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if (stackSlot == VirtRegMap::NO_STACK_SLOT)
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if (stackSlot == VirtRegMap::NO_STACK_SLOT) {
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return;
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}
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const TargetRegisterClass *RC = mri->getRegClass(spilled->reg);
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LiveInterval &stackInterval = lss->getOrCreateInterval(stackSlot, RC);
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VNInfo *vni;
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if (stackInterval.getNumValNums() != 0)
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if (stackInterval.getNumValNums() != 0) {
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vni = stackInterval.getValNumInfo(0);
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else
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} else {
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vni = stackInterval.getNextValue(
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SlotIndex(), 0, lss->getVNInfoAllocator());
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}
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LiveInterval &rhsInterval = lis->getInterval(spilled->reg);
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stackInterval.MergeRangesInAsValue(rhsInterval, vni);
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@ -594,11 +601,9 @@ void RegAllocPBQP::finalizeAlloc() const {
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// Get the physical register for this interval
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if (TargetRegisterInfo::isPhysicalRegister(li->reg)) {
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reg = li->reg;
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}
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else if (vrm->isAssignedReg(li->reg)) {
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} else if (vrm->isAssignedReg(li->reg)) {
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reg = vrm->getPhys(li->reg);
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}
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else {
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} else {
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// Ranges which are assigned a stack slot only are ignored.
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continue;
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}
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@ -615,7 +620,7 @@ void RegAllocPBQP::finalizeAlloc() const {
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// Find the set of basic blocks which this range is live into...
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if (lis->findLiveInMBBs(lrItr->start, lrItr->end, liveInMBBs)) {
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// And add the physreg for this interval to their live-in sets.
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for (unsigned i = 0; i < liveInMBBs.size(); ++i) {
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for (unsigned i = 0; i != liveInMBBs.size(); ++i) {
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if (liveInMBBs[i] != entryMBB) {
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if (!liveInMBBs[i]->isLiveIn(reg)) {
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liveInMBBs[i]->addLiveIn(reg);
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