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[AMDGPU] Fixed dpp combine of VOP1 

If original instruction did not have source modifiers they were
not added to the new DPP instruction as well, even if needed.

Differential Revision: https://reviews.llvm.org/D68729

llvm-svn: 374241
This commit is contained in:
Stanislav Mekhanoshin 2019-10-09 22:02:58 +00:00
parent 47363a148f
commit c6dec1d828
2 changed files with 31 additions and 0 deletions
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8
llvm/lib/Target/AMDGPU/GCNDPPCombine.cpp
View File

@ -195,6 +195,10 @@ MachineInstr *GCNDPPCombine::createDPPInst(MachineInstr &OrigMI,
assert(0LL == (Mod0->getImm() & ~(SISrcMods::ABS | SISrcMods::NEG)));
DPPInst.addImm(Mod0->getImm());
++NumOperands;
} else if (AMDGPU::getNamedOperandIdx(DPPOp,
AMDGPU::OpName::src0_modifiers) != -1) {
DPPInst.addImm(0);
++NumOperands;
}
auto *Src0 = TII->getNamedOperand(MovMI, AMDGPU::OpName::src0);
assert(Src0);
@ -214,6 +218,10 @@ MachineInstr *GCNDPPCombine::createDPPInst(MachineInstr &OrigMI,
assert(0LL == (Mod1->getImm() & ~(SISrcMods::ABS | SISrcMods::NEG)));
DPPInst.addImm(Mod1->getImm());
++NumOperands;
} else if (AMDGPU::getNamedOperandIdx(DPPOp,
AMDGPU::OpName::src1_modifiers) != -1) {
DPPInst.addImm(0);
++NumOperands;
}
if (auto *Src1 = TII->getNamedOperand(OrigMI, AMDGPU::OpName::src1)) {
if (!TII->isOperandLegal(*DPPInst.getInstr(), NumOperands, Src1)) {

23
llvm/test/CodeGen/AMDGPU/dpp_combine.mir
View File

@ -526,3 +526,26 @@ body: |
%3:vreg_64 = REG_SEQUENCE %2, %subreg.sub0 ; %3.sub1 is undef
%4:vgpr_32 = V_MOV_B32_dpp %3.sub1, %1, 1, 15, 15, 1, implicit $exec
%5:vgpr_32 = V_ADD_U32_e32 %4, %0.sub1, implicit $exec
...
# Test instruction which does not have modifiers in VOP1 form but does in DPP form.
# CHECK-LABEL: name: dpp_vop1
# CHECK: %3:vgpr_32 = V_CEIL_F32_dpp %1:vgpr_32, 0, undef %2:vgpr_32, 1, 15, 15, 1, implicit $exec
name: dpp_vop1
tracksRegLiveness: true
body: |
bb.0:
%2:vgpr_32 = V_MOV_B32_dpp undef %1:vgpr_32, undef %0:vgpr_32, 1, 15, 15, 1, implicit $exec
%3:vgpr_32 = V_CEIL_F32_e32 %2, implicit $exec
...
# Test instruction which does not have modifiers in VOP2 form but does in DPP form.
# CHECK-LABEL: name: dpp_min
# CHECK: %3:vgpr_32 = V_MIN_F32_dpp %1:vgpr_32, 0, undef %2:vgpr_32, 0, undef %4:vgpr_32, 1, 15, 15, 1, implicit $exec
name: dpp_min
tracksRegLiveness: true
body: |
bb.0:
%2:vgpr_32 = V_MOV_B32_dpp undef %1:vgpr_32, undef %0:vgpr_32, 1, 15, 15, 1, implicit $exec
%4:vgpr_32 = V_MIN_F32_e32 %2, undef %3:vgpr_32, implicit $exec
...