forked from OSchip/llvm-project
Allow unaligned byte/word selection watchpoints for arm- linux/android targets.
Differential revision: http://reviews.llvm.org/D21516 llvm-svn: 273863
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@ -614,6 +614,7 @@ NativeRegisterContextLinux_arm::SetHardwareWatchpoint (lldb::addr_t addr, size_t
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return LLDB_INVALID_INDEX32;
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uint32_t control_value = 0, wp_index = 0, addr_word_offset = 0, byte_mask = 0;
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lldb::addr_t real_addr = addr;
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// Check if we are setting watchpoint other than read/write/access
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// Also update watchpoint flag to match Arm write-read bit configuration.
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@ -637,7 +638,24 @@ NativeRegisterContextLinux_arm::SetHardwareWatchpoint (lldb::addr_t addr, size_t
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if (size == 0 || size > 4)
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return LLDB_INVALID_INDEX32;
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// We can only watch up to four bytes that follow a 4 byte aligned address
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// Check 4-byte alignment for hardware watchpoint target address.
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// Below is a hack to recalculate address and size in order to
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// make sure we can watch non 4-byte alligned addresses as well.
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if (addr & 0x03)
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{
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uint8_t watch_mask = (addr & 0x03) + size;
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if (watch_mask > 0x04)
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return LLDB_INVALID_INDEX32;
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else if (watch_mask <= 0x02)
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size = 2;
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else if (watch_mask <= 0x04)
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size = 4;
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addr = addr & (~0x03);
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}
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// We can only watch up to four bytes that follow a 4 byte aligned address
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// per watchpoint register pair, so make sure we can properly encode this.
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addr_word_offset = addr % 4;
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byte_mask = ((1u << size) - 1u) << addr_word_offset;
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@ -682,6 +700,7 @@ NativeRegisterContextLinux_arm::SetHardwareWatchpoint (lldb::addr_t addr, size_t
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if ((m_hwp_regs[wp_index].control & 1) == 0)
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{
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// Update watchpoint in local cache
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m_hwp_regs[wp_index].real_addr = real_addr;
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m_hwp_regs[wp_index].address = addr;
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m_hwp_regs[wp_index].control = control_value;
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m_hwp_regs[wp_index].refcount = 1;
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@ -864,6 +883,7 @@ NativeRegisterContextLinux_arm::GetWatchpointHitIndex(uint32_t &wp_index, lldb::
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if (m_hwp_regs[wp_index].refcount >= 1 && WatchpointIsEnabled(wp_index)
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&& trap_addr >= watch_addr && trap_addr < watch_addr + watch_size)
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{
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m_hwp_regs[wp_index].hit_addr = trap_addr;
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return Error();
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}
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}
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@ -884,7 +904,24 @@ NativeRegisterContextLinux_arm::GetWatchpointAddress (uint32_t wp_index)
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return LLDB_INVALID_ADDRESS;
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if (WatchpointIsEnabled(wp_index))
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return m_hwp_regs[wp_index].address;
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return m_hwp_regs[wp_index].real_addr;
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else
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return LLDB_INVALID_ADDRESS;
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}
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lldb::addr_t
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NativeRegisterContextLinux_arm::GetWatchpointHitAddress (uint32_t wp_index)
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{
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Log *log(lldb_private::GetLogIfAllCategoriesSet (LIBLLDB_LOG_WATCHPOINTS));
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if (log)
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log->Printf ("NativeRegisterContextLinux_arm::%s()", __FUNCTION__);
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if (wp_index >= m_max_hwp_supported)
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return LLDB_INVALID_ADDRESS;
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if (WatchpointIsEnabled(wp_index))
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return m_hwp_regs[wp_index].hit_addr;
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else
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return LLDB_INVALID_ADDRESS;
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}
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@ -73,6 +73,9 @@ namespace process_linux {
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Error
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GetWatchpointHitIndex(uint32_t &wp_index, lldb::addr_t trap_addr) override;
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lldb::addr_t
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GetWatchpointHitAddress (uint32_t wp_index) override;
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lldb::addr_t
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GetWatchpointAddress (uint32_t wp_index) override;
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@ -162,6 +165,8 @@ namespace process_linux {
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struct DREG
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{
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lldb::addr_t address; // Breakpoint/watchpoint address value.
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lldb::addr_t hit_addr; // Address at which last watchpoint trigger exception occurred.
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lldb::addr_t real_addr; // Address value that should cause target to stop.
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uint32_t control; // Breakpoint/watchpoint control value.
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uint32_t refcount; // Serves as enable/disable and refernce counter.
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};
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@ -2060,7 +2060,7 @@ ProcessGDBRemote::SetThreadStopInfo (lldb::tid_t tid,
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WatchpointSP wp_sp;
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ArchSpec::Core core = GetTarget().GetArchitecture().GetCore();
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if ((core >= ArchSpec::kCore_mips_first && core <= ArchSpec::kCore_mips_last) ||
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(core >= ArchSpec::eCore_arm_arm64 && core <= ArchSpec::eCore_arm_aarch64))
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(core >= ArchSpec::eCore_arm_generic && core <= ArchSpec::eCore_arm_aarch64))
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wp_sp = GetTarget().GetWatchpointList().FindByAddress(wp_hit_addr);
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if (!wp_sp)
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wp_sp = GetTarget().GetWatchpointList().FindByAddress(wp_addr);
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