forked from OSchip/llvm-project
Annotate SSE horizontal and integer instructions.
llvm-svn: 177591
This commit is contained in:
Jakob Stoklund Olesen
parent
43a729d165
commit
c6dc70d865
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@ -4969,14 +4969,15 @@ multiclass S3D_Int<bits<8> o, string OpcodeStr, ValueType vt, RegisterClass RC,
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!if(Is2Addr,
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!strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
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!strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
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[(set RC:$dst, (vt (OpNode RC:$src1, RC:$src2)))], IIC_SSE_HADDSUB_RR>;
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[(set RC:$dst, (vt (OpNode RC:$src1, RC:$src2)))], IIC_SSE_HADDSUB_RR>,
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Sched<[WriteFAdd]>;
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def rm : S3DI<o, MRMSrcMem, (outs RC:$dst), (ins RC:$src1, x86memop:$src2),
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!if(Is2Addr,
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!strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
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!strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
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[(set RC:$dst, (vt (OpNode RC:$src1, (memop addr:$src2))))],
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IIC_SSE_HADDSUB_RM>;
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IIC_SSE_HADDSUB_RM>, Sched<[WriteFAddLd, ReadAfterLd]>;
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}
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multiclass S3_Int<bits<8> o, string OpcodeStr, ValueType vt, RegisterClass RC,
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X86MemOperand x86memop, SDNode OpNode, bit Is2Addr = 1> {
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@ -4984,14 +4985,15 @@ multiclass S3_Int<bits<8> o, string OpcodeStr, ValueType vt, RegisterClass RC,
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!if(Is2Addr,
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!strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
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!strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
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[(set RC:$dst, (vt (OpNode RC:$src1, RC:$src2)))], IIC_SSE_HADDSUB_RR>;
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[(set RC:$dst, (vt (OpNode RC:$src1, RC:$src2)))], IIC_SSE_HADDSUB_RR>,
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Sched<[WriteFAdd]>;
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def rm : S3I<o, MRMSrcMem, (outs RC:$dst), (ins RC:$src1, x86memop:$src2),
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!if(Is2Addr,
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!strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
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!strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
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[(set RC:$dst, (vt (OpNode RC:$src1, (memop addr:$src2))))],
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IIC_SSE_HADDSUB_RM>;
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IIC_SSE_HADDSUB_RM>, Sched<[WriteFAddLd, ReadAfterLd]>;
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}
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let Predicates = [HasAVX] in {
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@ -5040,7 +5042,7 @@ multiclass SS3I_unop_rm_int<bits<8> opc, string OpcodeStr,
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(ins VR128:$src),
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!strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
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[(set VR128:$dst, (IntId128 VR128:$src))], IIC_SSE_PABS_RR>,
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OpSize;
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OpSize, Sched<[WriteVecALU]>;
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def rm128 : SS38I<opc, MRMSrcMem, (outs VR128:$dst),
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(ins i128mem:$src),
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@ -5048,7 +5050,7 @@ multiclass SS3I_unop_rm_int<bits<8> opc, string OpcodeStr,
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[(set VR128:$dst,
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(IntId128
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(bitconvert (memopv2i64 addr:$src))))], IIC_SSE_PABS_RM>,
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OpSize;
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OpSize, Sched<[WriteVecALULd]>;
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}
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/// SS3I_unop_rm_int_y - Simple SSSE3 unary op whose type can be v*{i8,i16,i32}.
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@ -5058,14 +5060,15 @@ multiclass SS3I_unop_rm_int_y<bits<8> opc, string OpcodeStr,
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(ins VR256:$src),
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!strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
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[(set VR256:$dst, (IntId256 VR256:$src))]>,
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OpSize;
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OpSize, Sched<[WriteVecALU]>;
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def rm256 : SS38I<opc, MRMSrcMem, (outs VR256:$dst),
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(ins i256mem:$src),
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!strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
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[(set VR256:$dst,
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(IntId256
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(bitconvert (memopv4i64 addr:$src))))]>, OpSize;
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(bitconvert (memopv4i64 addr:$src))))]>, OpSize,
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Sched<[WriteVecALULd]>;
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}
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let Predicates = [HasAVX] in {
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@ -5097,6 +5100,7 @@ defm PABSD : SS3I_unop_rm_int<0x1E, "pabsd",
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// SSSE3 - Packed Binary Operator Instructions
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//===---------------------------------------------------------------------===//
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let Sched = WriteVecALU in {
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def SSE_PHADDSUBD : OpndItins<
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IIC_SSE_PHADDSUBD_RR, IIC_SSE_PHADDSUBD_RM
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>;
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@ -5106,12 +5110,16 @@ def SSE_PHADDSUBSW : OpndItins<
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def SSE_PHADDSUBW : OpndItins<
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IIC_SSE_PHADDSUBW_RR, IIC_SSE_PHADDSUBW_RM
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>;
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}
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let Sched = WriteShuffle in
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def SSE_PSHUFB : OpndItins<
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IIC_SSE_PSHUFB_RR, IIC_SSE_PSHUFB_RM
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>;
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let Sched = WriteVecALU in
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def SSE_PSIGN : OpndItins<
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IIC_SSE_PSIGN_RR, IIC_SSE_PSIGN_RM
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>;
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let Sched = WriteVecIMul in
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def SSE_PMULHRSW : OpndItins<
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IIC_SSE_PMULHRSW, IIC_SSE_PMULHRSW
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>;
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@ -5128,7 +5136,7 @@ multiclass SS3I_binop_rm<bits<8> opc, string OpcodeStr, SDNode OpNode,
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!strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
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!strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
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[(set RC:$dst, (OpVT (OpNode RC:$src1, RC:$src2)))], itins.rr>,
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OpSize;
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OpSize, Sched<[itins.Sched]>;
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def rm : SS38I<opc, MRMSrcMem, (outs RC:$dst),
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(ins RC:$src1, x86memop:$src2),
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!if(Is2Addr,
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@ -5136,7 +5144,8 @@ multiclass SS3I_binop_rm<bits<8> opc, string OpcodeStr, SDNode OpNode,
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!strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
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[(set RC:$dst,
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(OpVT (OpNode RC:$src1,
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(bitconvert (memop_frag addr:$src2)))))], itins.rm>, OpSize;
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(bitconvert (memop_frag addr:$src2)))))], itins.rm>, OpSize,
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Sched<[itins.Sched.Folded, ReadAfterLd]>;
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}
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/// SS3I_binop_rm_int - Simple SSSE3 bin op whose type can be v*{i8,i16,i32}.
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@ -5150,7 +5159,7 @@ multiclass SS3I_binop_rm_int<bits<8> opc, string OpcodeStr,
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!strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
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!strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
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[(set VR128:$dst, (IntId128 VR128:$src1, VR128:$src2))]>,
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OpSize;
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OpSize, Sched<[itins.Sched]>;
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def rm128 : SS38I<opc, MRMSrcMem, (outs VR128:$dst),
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(ins VR128:$src1, i128mem:$src2),
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!if(Is2Addr,
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@ -5158,7 +5167,8 @@ multiclass SS3I_binop_rm_int<bits<8> opc, string OpcodeStr,
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!strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
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[(set VR128:$dst,
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(IntId128 VR128:$src1,
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(bitconvert (memopv2i64 addr:$src2))))]>, OpSize;
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(bitconvert (memopv2i64 addr:$src2))))]>, OpSize,
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Sched<[itins.Sched.Folded, ReadAfterLd]>;
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}
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multiclass SS3I_binop_rm_int_y<bits<8> opc, string OpcodeStr,
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@ -5300,7 +5310,7 @@ multiclass ssse3_palignr<string asm, bit Is2Addr = 1> {
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!strconcat(asm, "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
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!strconcat(asm,
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"\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}")),
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[], IIC_SSE_PALIGNR>, OpSize;
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[], IIC_SSE_PALIGNR>, OpSize, Sched<[WriteShuffle]>;
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let mayLoad = 1 in
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def R128rm : SS3AI<0x0F, MRMSrcMem, (outs VR128:$dst),
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(ins VR128:$src1, i128mem:$src2, i8imm:$src3),
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@ -5308,7 +5318,7 @@ multiclass ssse3_palignr<string asm, bit Is2Addr = 1> {
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!strconcat(asm, "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
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!strconcat(asm,
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"\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}")),
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[], IIC_SSE_PALIGNR>, OpSize;
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[], IIC_SSE_PALIGNR>, OpSize, Sched<[WriteShuffleLd, ReadAfterLd]>;
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}
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}
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@ -5318,13 +5328,13 @@ multiclass ssse3_palignr_y<string asm, bit Is2Addr = 1> {
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(ins VR256:$src1, VR256:$src2, i8imm:$src3),
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!strconcat(asm,
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"\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
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[]>, OpSize;
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[]>, OpSize, Sched<[WriteShuffle]>;
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let mayLoad = 1 in
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def R256rm : SS3AI<0x0F, MRMSrcMem, (outs VR256:$dst),
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(ins VR256:$src1, i256mem:$src2, i8imm:$src3),
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!strconcat(asm,
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"\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
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[]>, OpSize;
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[]>, OpSize, Sched<[WriteShuffleLd, ReadAfterLd]>;
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}
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}
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