forked from OSchip/llvm-project
[mips] Add runtime options to enable/disable madd.fmt and msub.fmt
Add options to clang: -mmadd4 and -mno-madd4, use it to enable or disable generation of madd.fmt and similar instructions respectively, as per GCC. Patch by Stefan Maksimovic. Differential Revision: https://reviews.llvm.org/D33401 llvm-svn: 304929
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@ -2001,6 +2001,10 @@ def mdspr2 : Flag<["-"], "mdspr2">, Group<m_Group>;
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def mno_dspr2 : Flag<["-"], "mno-dspr2">, Group<m_Group>;
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def msingle_float : Flag<["-"], "msingle-float">, Group<m_Group>;
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def mdouble_float : Flag<["-"], "mdouble-float">, Group<m_Group>;
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def mmadd4 : Flag<["-"], "mmadd4">, Group<m_Group>,
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HelpText<"Enable the generation of 4-operand madd.s, madd.d and related instructions.">;
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def mno_madd4 : Flag<["-"], "mno-madd4">, Group<m_Group>,
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HelpText<"Disable the generation of 4-operand madd.s, madd.d and related instructions.">;
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def mmsa : Flag<["-"], "mmsa">, Group<m_Group>,
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HelpText<"Enable MSA ASE (MIPS only)">;
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def mno_msa : Flag<["-"], "mno-msa">, Group<m_Group>,
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@ -7737,6 +7737,7 @@ class MipsTargetInfo : public TargetInfo {
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NoDSP, DSP1, DSP2
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} DspRev;
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bool HasMSA;
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bool DisableMadd4;
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protected:
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bool HasFP64;
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@ -7747,7 +7748,7 @@ public:
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: TargetInfo(Triple), IsMips16(false), IsMicromips(false),
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IsNan2008(false), IsSingleFloat(false), IsNoABICalls(false),
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CanUseBSDABICalls(false), FloatABI(HardFloat), DspRev(NoDSP),
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HasMSA(false), HasFP64(false) {
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HasMSA(false), DisableMadd4(false), HasFP64(false) {
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TheCXXABI.set(TargetCXXABI::GenericMIPS);
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setABI((getTriple().getArch() == llvm::Triple::mips ||
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@ -7993,6 +7994,9 @@ public:
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if (HasMSA)
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Builder.defineMacro("__mips_msa", Twine(1));
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if (DisableMadd4)
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Builder.defineMacro("__mips_no_madd4", Twine(1));
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Builder.defineMacro("_MIPS_SZPTR", Twine(getPointerWidth(0)));
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Builder.defineMacro("_MIPS_SZINT", Twine(getIntWidth()));
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Builder.defineMacro("_MIPS_SZLONG", Twine(getLongWidth()));
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@ -8155,6 +8159,8 @@ public:
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DspRev = std::max(DspRev, DSP2);
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else if (Feature == "+msa")
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HasMSA = true;
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else if (Feature == "+nomadd4")
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DisableMadd4 = true;
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else if (Feature == "+fp64")
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HasFP64 = true;
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else if (Feature == "-fp64")
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@ -298,6 +298,13 @@ void mips::getMIPSTargetFeatures(const Driver &D, const llvm::Triple &Triple,
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AddTargetFeature(Args, Features, options::OPT_mno_odd_spreg,
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options::OPT_modd_spreg, "nooddspreg");
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if (Arg *A = Args.getLastArg(options::OPT_mmadd4, options::OPT_mno_madd4)) {
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if (A->getOption().matches(options::OPT_mmadd4))
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Features.push_back("-nomadd4");
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else
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Features.push_back("+nomadd4");
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}
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}
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mips::NanEncoding mips::getSupportedNanEncoding(StringRef &CPU) {
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@ -0,0 +1,86 @@
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// RUN: %clang --target=mips64-unknown-linux -S -mmadd4 %s -o -| FileCheck %s -check-prefix=MADD4
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// RUN: %clang --target=mips64-unknown-linux -S -mno-madd4 %s -o -| FileCheck %s -check-prefix=NOMADD4
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// RUN: %clang --target=mips64-unknown-linux -S -mmadd4 -fno-honor-nans %s -o -| FileCheck %s -check-prefix=MADD4-NONAN
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// RUN: %clang --target=mips64-unknown-linux -S -mno-madd4 -fno-honor-nans %s -o -| FileCheck %s -check-prefix=NOMADD4-NONAN
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float madd_s (float f, float g, float h)
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{
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return (f * g) + h;
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}
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// MADD4: madd.s
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// NOMADD4: mul.s
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// NOMADD4: add.s
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float msub_s (float f, float g, float h)
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{
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return (f * g) - h;
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}
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// MADD4: msub.s
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// NOMADD4: mul.s
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// NOMADD4: sub.s
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double madd_d (double f, double g, double h)
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{
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return (f * g) + h;
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}
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// MADD4: madd.d
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// NOMADD4: mul.d
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// NOMADD4: add.d
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double msub_d (double f, double g, double h)
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{
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return (f * g) - h;
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}
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// MADD4: msub.d
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// NOMADD4: mul.d
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// NOMADD4: sub.d
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float nmadd_s (float f, float g, float h)
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{
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// FIXME: Zero has been explicitly placed to force generation of a positive
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// zero in IR until pattern used to match this instruction is changed to
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// comply with negative zero as well.
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return 0-((f * g) + h);
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}
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// MADD4-NONAN: nmadd.s
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// NOMADD4-NONAN: mul.s
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// NOMADD4-NONAN: add.s
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// NOMADD4-NONAN: sub.s
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float nmsub_s (float f, float g, float h)
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{
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// FIXME: Zero has been explicitly placed to force generation of a positive
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// zero in IR until pattern used to match this instruction is changed to
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// comply with negative zero as well.
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return 0-((f * g) - h);
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}
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// MADD4-NONAN: nmsub.s
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// NOMADD4-NONAN: mul.s
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// NOMADD4-NONAN: sub.s
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// NOMADD4-NONAN: sub.s
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double nmadd_d (double f, double g, double h)
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{
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// FIXME: Zero has been explicitly placed to force generation of a positive
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// zero in IR until pattern used to match this instruction is changed to
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// comply with negative zero as well.
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return 0-((f * g) + h);
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}
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// MADD4-NONAN: nmadd.d
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// NOMADD4-NONAN: mul.d
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// NOMADD4-NONAN: add.d
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// NOMADD4-NONAN: sub.d
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double nmsub_d (double f, double g, double h)
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{
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// FIXME: Zero has been explicitly placed to force generation of a positive
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// zero in IR until pattern used to match this instruction is changed to
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// comply with negative zero as well.
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return 0-((f * g) - h);
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}
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// MADD4-NONAN: nmsub.d
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// NOMADD4-NONAN: mul.d
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// NOMADD4-NONAN: sub.d
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// NOMADD4-NONAN: sub.d
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@ -4664,6 +4664,16 @@
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// RUN: | FileCheck -match-full-lines -check-prefix MIPS-MSA %s
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// MIPS-MSA:#define __mips_msa 1
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//
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// RUN: %clang_cc1 -target-feature +nomadd4 \
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// RUN: -E -dM -triple=mips-none-none < /dev/null \
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// RUN: | FileCheck -match-full-lines -check-prefix MIPS-NOMADD4 %s
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// MIPS-NOMADD4:#define __mips_no_madd4 1
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//
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// RUN: %clang_cc1 \
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// RUN: -E -dM -triple=mips-none-none < /dev/null \
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// RUN: | FileCheck -match-full-lines -check-prefix MIPS-MADD4 %s
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// MIPS-MADD4-NOT:#define __mips_no_madd4 1
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//
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// RUN: %clang_cc1 -target-cpu mips32r3 -target-feature +nan2008 \
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// RUN: -E -dM -triple=mips-none-none < /dev/null \
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// RUN: | FileCheck -match-full-lines -check-prefix MIPS-NAN2008 %s
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