forked from OSchip/llvm-project
[RISCV] Add missing hunk from r316188
r316188 didn't set guessInstructionProperties=1 as it should have done. llvm-svn: 316189
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@ -40,7 +40,9 @@ def : ProcessorModel<"generic-rv64", NoSchedModel, [Feature64Bit]>;
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//===----------------------------------------------------------------------===//
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def RISCVInstrInfo : InstrInfo {
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let guessInstructionProperties = 0;
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// TODO: disable guessInstructionProperties when
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// https://reviews.llvm.org/D37065 lands.
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let guessInstructionProperties = 1;
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}
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def RISCVAsmParser : AsmParser {
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