forked from OSchip/llvm-project
parent
13d7c252e5
commit
c6a0338c04
|
@ -143,7 +143,7 @@ class Instruction {
|
|||
bit isCommutable = 0; // Is this 3 operand instruction commutable?
|
||||
bit isTerminator = 0; // Is this part of the terminator for a basic block?
|
||||
bit hasDelaySlot = 0; // Does this instruction have an delay slot?
|
||||
bit usesCustomDAGSChedInserter = 0; // Pseudo instr needing special help.
|
||||
bit usesCustomDAGSchedInserter = 0; // Pseudo instr needing special help.
|
||||
}
|
||||
|
||||
|
||||
|
|
|
@ -250,7 +250,7 @@ CodeGenInstruction::CodeGenInstruction(Record *R, const std::string &AsmStr)
|
|||
isCommutable = R->getValueAsBit("isCommutable");
|
||||
isTerminator = R->getValueAsBit("isTerminator");
|
||||
hasDelaySlot = R->getValueAsBit("hasDelaySlot");
|
||||
usesCustomDAGSchedInserter = R->getValueAsBit("usesCustomDAGSChedInserter");
|
||||
usesCustomDAGSchedInserter = R->getValueAsBit("usesCustomDAGSchedInserter");
|
||||
hasVariableNumberOfOperands = false;
|
||||
|
||||
try {
|
||||
|
|
Loading…
Reference in New Issue