forked from OSchip/llvm-project
CellSPU:
(a) Fix bgs 3052, 3057 (b) Incorporate Duncan's suggestions re: i1 promotion (c) Indentation updates. llvm-svn: 59790
This commit is contained in:
Scott Michel
parent
4fc308bd3b
commit
c6918c1ffa
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@ -430,8 +430,8 @@ bool
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SPUDAGToDAGISel::SelectDFormAddr(SDValue Op, SDValue N, SDValue &Base,
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SDValue &Index) {
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return DFormAddressPredicate(Op, N, Base, Index,
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SPUFrameInfo::minFrameOffset(),
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SPUFrameInfo::maxFrameOffset());
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SPUFrameInfo::minFrameOffset(),
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SPUFrameInfo::maxFrameOffset());
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}
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bool
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@ -544,7 +544,35 @@ SPUDAGToDAGISel::DFormAddressPredicate(SDValue Op, SDValue N, SDValue &Base,
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Base = CurDAG->getTargetConstant(0, N.getValueType());
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Index = N;
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return true;
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} else if (Opc == ISD::Register || Opc == ISD::CopyFromReg) {
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unsigned OpOpc = Op.getOpcode();
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if (OpOpc == ISD::STORE || OpOpc == ISD::LOAD) {
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// Direct load/store without getelementptr
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SDValue Addr, Offs;
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// Get the register from CopyFromReg
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if (Opc == ISD::CopyFromReg)
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Addr = N.getOperand(1);
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else
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Addr = N; // Register
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if (OpOpc == ISD::STORE)
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Offs = Op.getOperand(3);
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else
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Offs = Op.getOperand(2); // LOAD
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if (Offs.getOpcode() == ISD::Constant || Offs.getOpcode() == ISD::UNDEF) {
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if (Offs.getOpcode() == ISD::UNDEF)
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Offs = CurDAG->getTargetConstant(0, Offs.getValueType());
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Base = Offs;
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Index = Addr;
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return true;
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}
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}
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}
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return false;
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}
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@ -554,21 +582,27 @@ SPUDAGToDAGISel::DFormAddressPredicate(SDValue Op, SDValue N, SDValue &Base,
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\arg Base The base pointer operand
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\arg Index The offset/index operand
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If the address \a N can be expressed as a [r + s10imm] address, returns false.
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Otherwise, creates two operands, Base and Index that will become the [r+r]
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address.
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If the address \a N can be expressed as an A-form or D-form address, returns
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false. Otherwise, creates two operands, Base and Index that will become the
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(r)(r) X-form address.
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*/
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bool
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SPUDAGToDAGISel::SelectXFormAddr(SDValue Op, SDValue N, SDValue &Base,
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SDValue &Index) {
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if (SelectAFormAddr(Op, N, Base, Index)
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|| SelectDFormAddr(Op, N, Base, Index))
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return false;
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if (!SelectAFormAddr(Op, N, Base, Index)
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&& !SelectDFormAddr(Op, N, Base, Index)) {
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// default form of a X-form address is r(r) in operands 0 and 1:
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SDValue Op0 = N.getOperand(0);
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SDValue Op1 = N.getOperand(1);
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// All else fails, punt and use an X-form address:
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Base = N.getOperand(0);
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Index = N.getOperand(1);
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return true;
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if (Op0.getOpcode() == ISD::Register && Op1.getOpcode() == ISD::Register) {
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Base = Op0;
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Index = Op1;
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return true;
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}
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}
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return false;
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}
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//! Convert the operand from a target-independent to a target-specific node
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@ -165,8 +165,7 @@ SPUTargetLowering::SPUTargetLowering(SPUTargetMachine &TM)
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setOperationAction(ISD::STORE, VT, Custom);
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}
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// Custom lower BRCOND for i1, i8 to "promote" the result to
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// i32 and i16, respectively.
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// Custom lower BRCOND for i8 to "promote" the result to i16
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setOperationAction(ISD::BRCOND, MVT::Other, Custom);
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// Expand the jumptable branches
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@ -215,7 +214,8 @@ SPUTargetLowering::SPUTargetLowering(SPUTargetMachine &TM)
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setOperationAction(ISD::SHL, MVT::i8, Custom);
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setOperationAction(ISD::SRL, MVT::i8, Custom);
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setOperationAction(ISD::SRA, MVT::i8, Custom);
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// And SPU needs custom lowering for shift left/right for i64
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// SPU needs custom lowering for shift left/right for i64
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setOperationAction(ISD::SHL, MVT::i64, Custom);
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setOperationAction(ISD::SRL, MVT::i64, Custom);
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setOperationAction(ISD::SRA, MVT::i64, Custom);
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@ -223,7 +223,13 @@ SPUTargetLowering::SPUTargetLowering(SPUTargetMachine &TM)
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// Custom lower i8, i32 and i64 multiplications
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setOperationAction(ISD::MUL, MVT::i8, Custom);
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setOperationAction(ISD::MUL, MVT::i32, Custom);
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setOperationAction(ISD::MUL, MVT::i64, Expand);
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setOperationAction(ISD::MUL, MVT::i64, Expand); // libcall
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// SMUL_LOHI, UMUL_LOHI
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setOperationAction(ISD::SMUL_LOHI, MVT::i32, Custom);
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setOperationAction(ISD::UMUL_LOHI, MVT::i32, Custom);
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setOperationAction(ISD::SMUL_LOHI, MVT::i64, Custom);
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setOperationAction(ISD::UMUL_LOHI, MVT::i64, Custom);
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// Need to custom handle (some) common i8, i64 math ops
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setOperationAction(ISD::ADD, MVT::i64, Custom);
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@ -247,13 +253,11 @@ SPUTargetLowering::SPUTargetLowering(SPUTargetMachine &TM)
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// SPU has a version of select that implements (a&~c)|(b&c), just like
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// select ought to work:
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setOperationAction(ISD::SELECT, MVT::i1, Promote);
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setOperationAction(ISD::SELECT, MVT::i8, Legal);
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setOperationAction(ISD::SELECT, MVT::i16, Legal);
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setOperationAction(ISD::SELECT, MVT::i32, Legal);
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setOperationAction(ISD::SELECT, MVT::i64, Expand);
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setOperationAction(ISD::SETCC, MVT::i1, Promote);
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setOperationAction(ISD::SETCC, MVT::i8, Legal);
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setOperationAction(ISD::SETCC, MVT::i16, Legal);
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setOperationAction(ISD::SETCC, MVT::i32, Legal);
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@ -299,7 +303,7 @@ SPUTargetLowering::SPUTargetLowering(SPUTargetMachine &TM)
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// We want to legalize GlobalAddress and ConstantPool nodes into the
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// appropriate instructions to materialize the address.
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for (unsigned sctype = (unsigned) MVT::i1; sctype < (unsigned) MVT::f128;
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for (unsigned sctype = (unsigned) MVT::i8; sctype < (unsigned) MVT::f128;
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++sctype) {
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MVT VT = (MVT::SimpleValueType)sctype;
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@ -699,8 +703,7 @@ LowerSTORE(SDValue Op, SelectionDAG &DAG, const SPUSubtarget *ST) {
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int chunk_offset, slot_offset;
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bool was16aligned;
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// The vector type we really want to load from the 16-byte chunk, except
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// in the case of MVT::i1, which has to be v16i8.
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// The vector type we really want to load from the 16-byte chunk.
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MVT vecVT = MVT::getVectorVT(VT, (128 / VT.getSizeInBits())),
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stVecVT = MVT::getVectorVT(StVT, (128 / StVT.getSizeInBits()));
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@ -908,7 +911,7 @@ LowerConstantFP(SDValue Op, SelectionDAG &DAG) {
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return SDValue();
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}
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//! Lower MVT::i1, MVT::i8 brcond to a promoted type (MVT::i32, MVT::i16)
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//! Lower MVT::i8 brcond to a promoted type (MVT::i32, MVT::i16)
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static SDValue
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LowerBRCOND(SDValue Op, SelectionDAG &DAG)
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{
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@ -916,8 +919,8 @@ LowerBRCOND(SDValue Op, SelectionDAG &DAG)
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MVT CondVT = Cond.getValueType();
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MVT CondNVT;
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if (CondVT == MVT::i1 || CondVT == MVT::i8) {
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CondNVT = (CondVT == MVT::i1 ? MVT::i32 : MVT::i16);
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if (CondVT == MVT::i8) {
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CondNVT = MVT::i16;
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return DAG.getNode(ISD::BRCOND, Op.getValueType(),
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Op.getOperand(0),
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DAG.getNode(ISD::ZERO_EXTEND, CondNVT, Op.getOperand(1)),
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@ -957,37 +960,37 @@ LowerFORMAL_ARGUMENTS(SDValue Op, SelectionDAG &DAG, int &VarArgsFrameIndex)
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switch (ObjectVT.getSimpleVT()) {
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default: {
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cerr << "LowerFORMAL_ARGUMENTS Unhandled argument type: "
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<< ObjectVT.getMVTString()
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<< "\n";
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abort();
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cerr << "LowerFORMAL_ARGUMENTS Unhandled argument type: "
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<< ObjectVT.getMVTString()
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<< "\n";
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abort();
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}
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case MVT::i8:
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ArgRegClass = &SPU::R8CRegClass;
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break;
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ArgRegClass = &SPU::R8CRegClass;
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break;
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case MVT::i16:
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ArgRegClass = &SPU::R16CRegClass;
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break;
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ArgRegClass = &SPU::R16CRegClass;
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break;
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case MVT::i32:
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ArgRegClass = &SPU::R32CRegClass;
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break;
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ArgRegClass = &SPU::R32CRegClass;
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break;
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case MVT::i64:
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ArgRegClass = &SPU::R64CRegClass;
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break;
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ArgRegClass = &SPU::R64CRegClass;
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break;
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case MVT::f32:
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ArgRegClass = &SPU::R32FPRegClass;
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break;
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ArgRegClass = &SPU::R32FPRegClass;
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break;
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case MVT::f64:
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ArgRegClass = &SPU::R64FPRegClass;
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break;
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ArgRegClass = &SPU::R64FPRegClass;
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break;
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case MVT::v2f64:
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case MVT::v4f32:
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case MVT::v2i64:
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case MVT::v4i32:
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case MVT::v8i16:
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case MVT::v16i8:
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ArgRegClass = &SPU::VECREGRegClass;
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break;
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ArgRegClass = &SPU::VECREGRegClass;
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break;
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}
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unsigned VReg = RegInfo.createVirtualRegister(ArgRegClass);
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@ -2103,7 +2106,6 @@ static SDValue LowerEXTRACT_VECTOR_ELT(SDValue Op, SelectionDAG &DAG) {
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// zero fill uppper part of preferred slot, don't care about the
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// other slots:
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unsigned int mask_val;
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if (i <= prefslot_end) {
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mask_val =
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((i < prefslot_begin)
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@ -2884,7 +2886,7 @@ SPUTargetLowering::PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const
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}
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}
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// Otherwise, return unchanged.
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#if 1
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#ifdef NDEBUG
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if (Result.getNode()) {
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DEBUG(cerr << "\nReplace.SPU: ");
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DEBUG(N->dump(&DAG));
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@ -161,7 +161,7 @@ SPUInstrInfo::isStoreToStackSlot(const MachineInstr *MI,
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case SPU::STQDr64:
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case SPU::STQDr32:
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case SPU::STQDr16:
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// case SPU::STQDr8:
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case SPU::STQDr8:
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case SPU::STQXv16i8:
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case SPU::STQXv8i16:
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case SPU::STQXv4i32:
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@ -171,7 +171,7 @@ SPUInstrInfo::isStoreToStackSlot(const MachineInstr *MI,
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case SPU::STQXr64:
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case SPU::STQXr32:
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case SPU::STQXr16:
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// case SPU::STQXr8:
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case SPU::STQXr8:
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if (MI->getOperand(1).isImm() && !MI->getOperand(1).getImm() &&
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MI->getOperand(2).isFI()) {
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FrameIndex = MI->getOperand(2).getIndex();
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@ -3494,26 +3494,62 @@ def FIf32 :
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"fi\t$rT, $rA, $rB", SPrecFP,
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[(set R32FP:$rT, (SPUinterpolate R32FP:$rA, R32FP:$rB))]>;
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// Floating Compare Equal
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//--------------------------------------------------------------------------
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// Basic single precision floating point comparisons:
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//
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// Note: There is no support on SPU for single precision NaN. Consequently,
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// ordered and unordered comparisons are the same.
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//--------------------------------------------------------------------------
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def FCEQf32 :
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RRForm<0b01000011110, (outs R32C:$rT), (ins R32FP:$rA, R32FP:$rB),
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"fceq\t$rT, $rA, $rB", SPrecFP,
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[(set R32C:$rT, (setoeq R32FP:$rA, R32FP:$rB))]>;
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[(set R32C:$rT, (setueq R32FP:$rA, R32FP:$rB))]>;
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def : Pat<(setoeq R32FP:$rA, R32FP:$rB),
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(FCEQf32 R32FP:$rA, R32FP:$rB)>;
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def FCMEQf32 :
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RRForm<0b01010011110, (outs R32C:$rT), (ins R32FP:$rA, R32FP:$rB),
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"fcmeq\t$rT, $rA, $rB", SPrecFP,
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[(set R32C:$rT, (setoeq (fabs R32FP:$rA), (fabs R32FP:$rB)))]>;
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[(set R32C:$rT, (setueq (fabs R32FP:$rA), (fabs R32FP:$rB)))]>;
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def : Pat<(setoeq (fabs R32FP:$rA), (fabs R32FP:$rB)),
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(FCMEQf32 R32FP:$rA, R32FP:$rB)>;
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def FCGTf32 :
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RRForm<0b01000011010, (outs R32C:$rT), (ins R32FP:$rA, R32FP:$rB),
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"fcgt\t$rT, $rA, $rB", SPrecFP,
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[(set R32C:$rT, (setogt R32FP:$rA, R32FP:$rB))]>;
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[(set R32C:$rT, (setugt R32FP:$rA, R32FP:$rB))]>;
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def : Pat<(setugt R32FP:$rA, R32FP:$rB),
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(FCGTf32 R32FP:$rA, R32FP:$rB)>;
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def FCMGTf32 :
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RRForm<0b01010011010, (outs R32C:$rT), (ins R32FP:$rA, R32FP:$rB),
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"fcmgt\t$rT, $rA, $rB", SPrecFP,
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[(set R32C:$rT, (setogt (fabs R32FP:$rA), (fabs R32FP:$rB)))]>;
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[(set R32C:$rT, (setugt (fabs R32FP:$rA), (fabs R32FP:$rB)))]>;
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def : Pat<(setugt (fabs R32FP:$rA), (fabs R32FP:$rB)),
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(FCMGTf32 R32FP:$rA, R32FP:$rB)>;
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//--------------------------------------------------------------------------
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// Single precision floating point comparisons and SETCC equivalents:
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//--------------------------------------------------------------------------
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def : SETCCNegCondReg<setune, R32FP, i32, XORIr32, FCEQf32>;
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def : SETCCNegCondReg<setone, R32FP, i32, XORIr32, FCEQf32>;
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def : SETCCBinOpReg<setuge, R32FP, ORr32, FCGTf32, FCEQf32>;
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def : SETCCBinOpReg<setoge, R32FP, ORr32, FCGTf32, FCEQf32>;
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def : SETCCBinOpReg<setult, R32FP, NORr32, FCGTf32, FCEQf32>;
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def : SETCCBinOpReg<setolt, R32FP, NORr32, FCGTf32, FCEQf32>;
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def : Pat<(setule R32FP:$rA, R32FP:$rB),
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(XORIr32 (FCGTf32 R32FP:$rA, R32FP:$rB), 0xffffffff)>;
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def : Pat<(setole R32FP:$rA, R32FP:$rB),
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(XORIr32 (FCGTf32 R32FP:$rA, R32FP:$rB), 0xffffffff)>;
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// FP Status and Control Register Write
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// Why isn't rT a don't care in the ISA?
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@ -0,0 +1,20 @@
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; RUN: llvm-as -o - %s | llc -march=cellspu > %t1.s
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; RUN: grep {lqd.*0(\$3)} %t1.s | count 1
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; RUN: grep {lqd.*16(\$3)} %t1.s | count 1
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; ModuleID = 'loads.bc'
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target datalayout = "E-p:32:32:128-f64:64:128-f32:32:128-i64:32:128-i32:32:128-i16:16:128-i8:8:128-i1:8:128-a0:0:128-v128:128:128-s0:128:128"
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target triple = "spu"
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define <4 x float> @load_v4f32_1(<4 x float>* %a) nounwind readonly {
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entry:
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%tmp1 = load <4 x float>* %a
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ret <4 x float> %tmp1
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}
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define <4 x float> @load_v4f32_2(<4 x float>* %a) nounwind readonly {
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entry:
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%arrayidx = getelementptr <4 x float>* %a, i32 1 ; <<4 x float>*> [#uses=1]
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%tmp1 = load <4 x float>* %arrayidx ; <<4 x float>> [#uses=1]
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ret <4 x float> %tmp1
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}
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@ -0,0 +1,22 @@
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; RUN: llvm-as -o - %s | llc -march=cellspu > %t1.s
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; RUN: grep {stqd.*0(\$3)} %t1.s | count 1
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; RUN: grep {stqd.*16(\$3)} %t1.s | count 1
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; RUN: grep 16256 %t1.s | count 1
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; RUN: grep 16384 %t1.s | count 1
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; ModuleID = 'stores.bc'
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target datalayout = "E-p:32:32:128-f64:64:128-f32:32:128-i64:32:128-i32:32:128-i16:16:128-i8:8:128-i1:8:128-a0:0:128-v128:128:128-s0:128:128"
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target triple = "spu"
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define void @store_v4f32_1(<4 x float>* %a) nounwind {
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entry:
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store <4 x float> < float 1.000000e+00, float 1.000000e+00, float 1.000000e+00, float 1.000000e+00 >, <4 x float>* %a
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ret void
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}
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||||
|
||||
define void @store_v4f32_2(<4 x float>* %a) nounwind {
|
||||
entry:
|
||||
%arrayidx = getelementptr <4 x float>* %a, i32 1
|
||||
store <4 x float> < float 2.000000e+00, float 2.000000e+00, float 2.000000e+00, float 2.000000e+00 >, <4 x float>* %arrayidx
|
||||
ret void
|
||||
}
|
||||
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Reference in New Issue