forked from OSchip/llvm-project
[DAGCombiner] Slightly improve readability of matchRotateSub
Slightly change the wording in the function comment. Originally, it can be misunderstood as we turned the input into two subsequent rotates. Better connect the comment which talks about Mask and the code which used LoBits. Renamed variable to MaskLoBits. llvm-svn: 203314
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@ -3414,9 +3414,9 @@ static bool MatchRotateHalf(SDValue Op, SDValue &Shift, SDValue &Mask) {
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//
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// (or (shift1 X, Neg), (shift2 X, Pos))
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//
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// reduces to a rotate in direction shift2 by Pos and a rotate in direction
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// shift1 by Neg. The range [0, OpSize) means that we only need to consider
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// shift amounts with defined behavior.
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// reduces to a rotate in direction shift2 by Pos or (equivalently) a rotate
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// in direction shift1 by Neg. The range [0, OpSize) means that we only need
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// to consider shift amounts with defined behavior.
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static bool matchRotateSub(SDValue Pos, SDValue Neg, unsigned OpSize) {
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// If OpSize is a power of 2 then:
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//
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@ -3449,13 +3449,13 @@ static bool matchRotateSub(SDValue Pos, SDValue Neg, unsigned OpSize) {
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// always invokes undefined behavior for 32-bit X.
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//
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// Below, Mask == OpSize - 1 when using [A] and is all-ones otherwise.
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unsigned LoBits = 0;
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unsigned MaskLoBits = 0;
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if (Neg.getOpcode() == ISD::AND &&
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isPowerOf2_64(OpSize) &&
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Neg.getOperand(1).getOpcode() == ISD::Constant &&
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cast<ConstantSDNode>(Neg.getOperand(1))->getAPIntValue() == OpSize - 1) {
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Neg = Neg.getOperand(0);
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LoBits = Log2_64(OpSize);
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MaskLoBits = Log2_64(OpSize);
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}
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// Check whether Neg has the form (sub NegC, NegOp1) for some NegC and NegOp1.
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@ -3496,8 +3496,9 @@ static bool matchRotateSub(SDValue Pos, SDValue Neg, unsigned OpSize) {
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return false;
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// Now we just need to check that OpSize & Mask == Width & Mask.
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if (LoBits)
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return Width.getLoBits(LoBits) == 0;
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if (MaskLoBits)
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// Opsize & Mask is 0 since Mask is Opsize - 1.
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return Width.getLoBits(MaskLoBits) == 0;
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return Width == OpSize;
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}
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