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[ARM] Refactor Exynos feature set (NFC) 

Since all Exynos processors share the same feature set, fold them in the
implied fatures list for the subtarget.

llvm-svn: 342583
This commit is contained in:
Evandro Menezes 2018-09-19 19:43:23 +00:00
parent e62fc3d0b6
commit c62ab61173
3 changed files with 23 additions and 71 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

90
llvm/lib/Target/ARM/ARM.td
View File

@ -494,8 +494,23 @@ def ProcKryo : SubtargetFeature<"kryo", "ARMProcFamily", "Kryo",
def ProcSwift : SubtargetFeature<"swift", "ARMProcFamily", "Swift",
"Swift ARM processors", []>;
def ProcExynosM1 : SubtargetFeature<"exynosm1", "ARMProcFamily", "ExynosM1",
"Samsung Exynos-Mx processors", []>;
def ProcExynos : SubtargetFeature<"exynos", "ARMProcFamily", "Exynos",
"Samsung Exynos processors",
[FeatureZCZeroing,
FeatureUseWideStrideVFP,
FeatureUseAA,
FeatureSplatVFPToNeon,
FeatureSlowVGETLNi32,
FeatureSlowVDUP32,
FeatureSlowFPBrcc,
FeatureProfUnpredicate,
FeatureHWDivThumb,
FeatureHWDivARM,
FeatureHasSlowFPVMLx,
FeatureHasRetAddrStack,
FeatureExpandMLx,
FeatureCrypto,
FeatureCRC]>;
def ProcR4 : SubtargetFeature<"r4", "ARMProcFamily", "CortexR4",
"Cortex-R4 ARM processors", []>;
@ -1033,73 +1048,10 @@ def : ProcessorModel<"cyclone", SwiftModel, [ARMv8a, ProcSwift,
FeatureZCZeroing,
FeatureNoPostRASched]>;
def : ProcNoItin<"exynos-m1", [ARMv8a, ProcExynosM1,
FeatureZCZeroing,
FeatureUseWideStrideVFP,
FeatureUseAA,
FeatureSplatVFPToNeon,
FeatureSlowVGETLNi32,
FeatureSlowVDUP32,
FeatureSlowFPBrcc,
FeatureProfUnpredicate,
FeatureHWDivThumb,
FeatureHWDivARM,
FeatureHasSlowFPVMLx,
FeatureHasRetAddrStack,
FeatureExpandMLx,
FeatureCrypto,
FeatureCRC]>;
def : ProcNoItin<"exynos-m2", [ARMv8a, ProcExynosM1,
FeatureZCZeroing,
FeatureUseWideStrideVFP,
FeatureUseAA,
FeatureSplatVFPToNeon,
FeatureSlowVGETLNi32,
FeatureSlowVDUP32,
FeatureSlowFPBrcc,
FeatureProfUnpredicate,
FeatureHWDivThumb,
FeatureHWDivARM,
FeatureHasSlowFPVMLx,
FeatureHasRetAddrStack,
FeatureExpandMLx,
FeatureCrypto,
FeatureCRC]>;
def : ProcNoItin<"exynos-m3", [ARMv8a, ProcExynosM1,
FeatureZCZeroing,
FeatureUseWideStrideVFP,
FeatureUseAA,
FeatureSplatVFPToNeon,
FeatureSlowVGETLNi32,
FeatureSlowVDUP32,
FeatureSlowFPBrcc,
FeatureProfUnpredicate,
FeatureHWDivThumb,
FeatureHWDivARM,
FeatureHasSlowFPVMLx,
FeatureHasRetAddrStack,
FeatureExpandMLx,
FeatureCrypto,
FeatureCRC]>;
def : ProcNoItin<"exynos-m4", [ARMv8a, ProcExynosM1,
FeatureZCZeroing,
FeatureUseWideStrideVFP,
FeatureUseAA,
FeatureSplatVFPToNeon,
FeatureSlowVGETLNi32,
FeatureSlowVDUP32,
FeatureSlowFPBrcc,
FeatureProfUnpredicate,
FeatureHWDivThumb,
FeatureHWDivARM,
FeatureHasSlowFPVMLx,
FeatureHasRetAddrStack,
FeatureExpandMLx,
FeatureCrypto,
FeatureCRC]>;
def : ProcNoItin<"exynos-m1", [ARMv8a, ProcExynos]>;
def : ProcNoItin<"exynos-m2", [ARMv8a, ProcExynos]>;
def : ProcNoItin<"exynos-m3", [ARMv8a, ProcExynos]>;
def : ProcNoItin<"exynos-m4", [ARMv8a, ProcExynos]>;
def : ProcNoItin<"kryo", [ARMv8a, ProcKryo,
FeatureHWDivThumb,

2
llvm/lib/Target/ARM/ARMSubtarget.cpp
View File

@ -287,7 +287,7 @@ void ARMSubtarget::initSubtargetFeatures(StringRef CPU, StringRef FS) {
case CortexR7:
case CortexM3:
case CortexR52:
case ExynosM1:
case Exynos:
case Kryo:
break;
case Krait:

2
llvm/lib/Target/ARM/ARMSubtarget.h
View File

@ -68,7 +68,7 @@ protected:
CortexR5,
CortexR52,
CortexR7,
ExynosM1,
Exynos,
Krait,
Kryo,
Swift