forked from OSchip/llvm-project
Fix the expansion for CONCAT_VECTORS so that it doesn't create illegal
types. llvm-svn: 72993
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@ -2460,23 +2460,7 @@ void SelectionDAGLegalize::ExpandNode(SDNode *Node,
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Results.push_back(ExpandExtractFromVectorThroughStack(SDValue(Node, 0)));
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break;
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case ISD::CONCAT_VECTORS: {
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// Use extract/insert/build vector for now. We might try to be
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// more clever later.
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SmallVector<SDValue, 8> Ops;
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unsigned NumOperands = Node->getNumOperands();
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for (unsigned i=0; i < NumOperands; ++i) {
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SDValue SubOp = Node->getOperand(i);
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MVT VVT = SubOp.getNode()->getValueType(0);
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MVT EltVT = VVT.getVectorElementType();
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unsigned NumSubElem = VVT.getVectorNumElements();
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for (unsigned j=0; j < NumSubElem; ++j) {
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Ops.push_back(DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, EltVT, SubOp,
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DAG.getIntPtrConstant(j)));
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}
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}
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Tmp1 = DAG.getNode(ISD::BUILD_VECTOR, dl, Node->getValueType(0),
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&Ops[0], Ops.size());
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Results.push_back(Tmp1);
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Results.push_back(ExpandVectorBuildThroughStack(Node));
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break;
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}
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case ISD::SCALAR_TO_VECTOR:
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@ -0,0 +1,8 @@
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; RUN: llvm-as < %s | llc
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define <2 x i64> @_mm_movpi64_pi64(<1 x i64> %a, <1 x i64> %b) nounwind readnone {
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entry:
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%0 = shufflevector <1 x i64> %a, <1 x i64> %b, <2 x i32> <i32 0, i32 1>
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ret <2 x i64> %0
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}
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