forked from OSchip/llvm-project
[FastISel][AArch64] Simplify mul to shift when possible.
This is related to rdar://problem/18369687. llvm-svn: 217980
This commit is contained in:
Juergen Ributzka
parent
7bddb0a56a
commit
c611d72754
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@ -3749,15 +3749,54 @@ bool AArch64FastISel::selectRem(const Instruction *I, unsigned ISDOpcode) {
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}
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bool AArch64FastISel::selectMul(const Instruction *I) {
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EVT SrcEVT = TLI.getValueType(I->getOperand(0)->getType(), true);
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if (!SrcEVT.isSimple())
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MVT VT;
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if (!isTypeSupported(I->getType(), VT, /*IsVectorAllowed=*/true))
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return false;
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MVT SrcVT = SrcEVT.getSimpleVT();
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// Must be simple value type. Don't handle vectors.
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if (SrcVT != MVT::i64 && SrcVT != MVT::i32 && SrcVT != MVT::i16 &&
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SrcVT != MVT::i8)
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return false;
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if (VT.isVector())
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return selectBinaryOp(I, ISD::MUL);
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const Value *Src0 = I->getOperand(0);
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const Value *Src1 = I->getOperand(1);
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if (const auto *C = dyn_cast<ConstantInt>(Src0))
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if (C->getValue().isPowerOf2())
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std::swap(Src0, Src1);
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// Try to simplify to a shift instruction.
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if (const auto *C = dyn_cast<ConstantInt>(Src1))
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if (C->getValue().isPowerOf2()) {
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uint64_t ShiftVal = C->getValue().logBase2();
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MVT SrcVT = VT;
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bool IsZExt = true;
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if (const auto *ZExt = dyn_cast<ZExtInst>(Src0)) {
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MVT VT;
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if (isValueAvailable(ZExt) && isTypeSupported(ZExt->getSrcTy(), VT)) {
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SrcVT = VT;
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IsZExt = true;
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Src0 = ZExt->getOperand(0);
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}
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} else if (const auto *SExt = dyn_cast<SExtInst>(Src0)) {
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MVT VT;
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if (isValueAvailable(SExt) && isTypeSupported(SExt->getSrcTy(), VT)) {
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SrcVT = VT;
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IsZExt = false;
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Src0 = SExt->getOperand(0);
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}
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}
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unsigned Src0Reg = getRegForValue(Src0);
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if (!Src0Reg)
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return false;
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bool Src0IsKill = hasTrivialKill(Src0);
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unsigned ResultReg =
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emitLSL_ri(VT, SrcVT, Src0Reg, Src0IsKill, ShiftVal, IsZExt);
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if (ResultReg) {
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updateValueMap(I, ResultReg);
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return true;
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}
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}
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unsigned Src0Reg = getRegForValue(I->getOperand(0));
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if (!Src0Reg)
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@ -3769,8 +3808,7 @@ bool AArch64FastISel::selectMul(const Instruction *I) {
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return false;
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bool Src1IsKill = hasTrivialKill(I->getOperand(1));
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unsigned ResultReg =
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emitMul_rr(SrcVT, Src0Reg, Src0IsKill, Src1Reg, Src1IsKill);
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unsigned ResultReg = emitMul_rr(VT, Src0Reg, Src0IsKill, Src1Reg, Src1IsKill);
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if (!ResultReg)
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return false;
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@ -3950,9 +3988,7 @@ bool AArch64FastISel::fastSelectInstruction(const Instruction *I) {
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case Instruction::Sub:
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return selectAddSub(I);
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case Instruction::Mul:
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if (!selectBinaryOp(I, ISD::MUL))
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return selectMul(I);
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return true;
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return selectMul(I);
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case Instruction::SRem:
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if (!selectBinaryOp(I, ISD::SREM))
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return selectRem(I, ISD::SREM);
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@ -1,40 +1,44 @@
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; RUN: llc -fast-isel -fast-isel-abort -verify-machineinstrs -mtriple=aarch64 < %s | FileCheck %s
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; RUN: llc -fast-isel -fast-isel-abort -verify-machineinstrs -mtriple=aarch64-apple-darwin < %s | FileCheck %s
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@var8 = global i8 0
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@var16 = global i16 0
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@var32 = global i32 0
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@var64 = global i64 0
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define void @test_mul8(i8 %lhs, i8 %rhs) {
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define zeroext i8 @test_mul8(i8 %lhs, i8 %rhs) {
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; CHECK-LABEL: test_mul8:
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; CHECK: mul {{w[0-9]+}}, w0, w1
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; %lhs = load i8* @var8
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; %rhs = load i8* @var8
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%prod = mul i8 %lhs, %rhs
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store i8 %prod, i8* @var8
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ret void
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; CHECK: mul {{w[0-9]+}}, w0, w1
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%1 = mul i8 %lhs, %rhs
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ret i8 %1
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}
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define void @test_mul16(i16 %lhs, i16 %rhs) {
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define zeroext i16 @test_mul16(i16 %lhs, i16 %rhs) {
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; CHECK-LABEL: test_mul16:
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; CHECK: mul {{w[0-9]+}}, w0, w1
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%prod = mul i16 %lhs, %rhs
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store i16 %prod, i16* @var16
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ret void
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; CHECK: mul {{w[0-9]+}}, w0, w1
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%1 = mul i16 %lhs, %rhs
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ret i16 %1
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}
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define void @test_mul32(i32 %lhs, i32 %rhs) {
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define i32 @test_mul32(i32 %lhs, i32 %rhs) {
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; CHECK-LABEL: test_mul32:
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; CHECK: mul {{w[0-9]+}}, w0, w1
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%prod = mul i32 %lhs, %rhs
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store i32 %prod, i32* @var32
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ret void
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; CHECK: mul {{w[0-9]+}}, w0, w1
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%1 = mul i32 %lhs, %rhs
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ret i32 %1
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}
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define void @test_mul64(i64 %lhs, i64 %rhs) {
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define i64 @test_mul64(i64 %lhs, i64 %rhs) {
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; CHECK-LABEL: test_mul64:
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; CHECK: mul {{x[0-9]+}}, x0, x1
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%prod = mul i64 %lhs, %rhs
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store i64 %prod, i64* @var64
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ret void
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; CHECK: mul {{x[0-9]+}}, x0, x1
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%1 = mul i64 %lhs, %rhs
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ret i64 %1
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}
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define i32 @test_mul2shift_i32(i32 %a) {
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; CHECK-LABEL: test_mul2shift_i32:
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; CHECK: lsl {{w[0-9]+}}, w0, #2
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%1 = mul i32 %a, 4
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ret i32 %1
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}
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define i64 @test_mul2shift_i64(i64 %a) {
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; CHECK-LABEL: test_mul2shift_i64:
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; CHECK: lsl {{x[0-9]+}}, x0, #3
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%1 = mul i64 %a, 8
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ret i64 %1
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}
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