forked from OSchip/llvm-project
GlobalISel: Add observer argument to legalizeIntrinsic
This is passed to legalizeCustom, but not intrinsic. Also remove the MRI argument, since you can get that from the MachineIRBuilder. I'm not sure why MachineIRBuilder has a private observer member, and this is passed separately.
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@ -1155,8 +1155,8 @@ public:
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/// Return true if MI is either legal or has been legalized and false
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/// if not legal.
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virtual bool legalizeIntrinsic(MachineInstr &MI, MachineRegisterInfo &MRI,
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MachineIRBuilder &MIRBuilder) const;
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virtual bool legalizeIntrinsic(MachineInstr &MI, MachineIRBuilder &MIRBuilder,
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GISelChangeObserver &Observer) const;
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/// Return the opcode (SEXT/ZEXT/ANYEXT) that should be performed while
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/// widening a constant of type SmallTy which targets can override.
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@ -114,8 +114,8 @@ LegalizerHelper::legalizeInstrStep(MachineInstr &MI) {
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if (MI.getOpcode() == TargetOpcode::G_INTRINSIC ||
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MI.getOpcode() == TargetOpcode::G_INTRINSIC_W_SIDE_EFFECTS)
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return LI.legalizeIntrinsic(MI, MRI, MIRBuilder) ? Legalized
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: UnableToLegalize;
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return LI.legalizeIntrinsic(MI, MIRBuilder, Observer) ? Legalized
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: UnableToLegalize;
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auto Step = LI.getAction(MI, MRI);
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switch (Step.Action) {
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case Legal:
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@ -682,8 +682,8 @@ LegalizerInfo::findVectorLegalAction(const InstrAspect &Aspect) const {
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}
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bool LegalizerInfo::legalizeIntrinsic(MachineInstr &MI,
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MachineRegisterInfo &MRI,
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MachineIRBuilder &MIRBuilder) const {
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MachineIRBuilder &MIRBuilder,
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GISelChangeObserver &Observer) const {
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return true;
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}
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@ -640,13 +640,13 @@ bool AArch64LegalizerInfo::legalizeCustom(MachineInstr &MI,
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}
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bool AArch64LegalizerInfo::legalizeIntrinsic(
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MachineInstr &MI, MachineRegisterInfo &MRI,
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MachineIRBuilder &MIRBuilder) const {
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MachineInstr &MI, MachineIRBuilder &MIRBuilder,
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GISelChangeObserver &Observer) const {
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switch (MI.getIntrinsicID()) {
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case Intrinsic::memcpy:
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case Intrinsic::memset:
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case Intrinsic::memmove:
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if (createMemLibcall(MIRBuilder, MRI, MI) ==
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if (createMemLibcall(MIRBuilder, *MIRBuilder.getMRI(), MI) ==
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LegalizerHelper::UnableToLegalize)
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return false;
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MI.eraseFromParent();
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@ -31,8 +31,8 @@ public:
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MachineIRBuilder &MIRBuilder,
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GISelChangeObserver &Observer) const override;
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bool legalizeIntrinsic(MachineInstr &MI, MachineRegisterInfo &MRI,
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MachineIRBuilder &MIRBuilder) const override;
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bool legalizeIntrinsic(MachineInstr &MI, MachineIRBuilder &MIRBuilder,
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GISelChangeObserver &Observer) const override;
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private:
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bool legalizeVaArg(MachineInstr &MI, MachineRegisterInfo &MRI,
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@ -2768,10 +2768,10 @@ bool AMDGPULegalizerInfo::legalizeBufferAtomic(MachineInstr &MI,
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return true;
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}
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// FIMXE: Needs observer like custom
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bool AMDGPULegalizerInfo::legalizeIntrinsic(MachineInstr &MI,
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MachineRegisterInfo &MRI,
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MachineIRBuilder &B) const {
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bool AMDGPULegalizerInfo::legalizeIntrinsic(
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MachineInstr &MI, MachineIRBuilder &B,
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GISelChangeObserver &Observer) const {
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MachineRegisterInfo &MRI = *B.getMRI();
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// Replace the use G_BRCOND with the exec manipulate and branch pseudos.
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auto IntrID = MI.getIntrinsicID();
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switch (IntrID) {
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@ -129,9 +129,8 @@ public:
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bool legalizeAtomicIncDec(MachineInstr &MI, MachineIRBuilder &B,
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bool IsInc) const;
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bool legalizeIntrinsic(MachineInstr &MI, MachineRegisterInfo &MRI,
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MachineIRBuilder &B) const override;
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bool legalizeIntrinsic(MachineInstr &MI, MachineIRBuilder &B,
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GISelChangeObserver &Observer) const override;
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};
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} // End llvm namespace.
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#endif
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@ -369,8 +369,9 @@ static bool MSA2OpIntrinsicToGeneric(MachineInstr &MI, unsigned Opcode,
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}
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bool MipsLegalizerInfo::legalizeIntrinsic(MachineInstr &MI,
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MachineRegisterInfo &MRI,
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MachineIRBuilder &MIRBuilder) const {
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MachineIRBuilder &MIRBuilder,
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GISelChangeObserver &Observer) const {
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MachineRegisterInfo &MRI = *MIRBuilder.getMRI();
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const MipsSubtarget &ST =
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static_cast<const MipsSubtarget &>(MI.getMF()->getSubtarget());
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const MipsInstrInfo &TII = *ST.getInstrInfo();
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@ -29,8 +29,8 @@ public:
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MachineIRBuilder &MIRBuilder,
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GISelChangeObserver &Observer) const override;
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bool legalizeIntrinsic(MachineInstr &MI, MachineRegisterInfo &MRI,
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MachineIRBuilder &MIRBuilder) const override;
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bool legalizeIntrinsic(MachineInstr &MI, MachineIRBuilder &MIRBuilder,
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GISelChangeObserver &Observer) const override;
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};
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} // end namespace llvm
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#endif
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@ -86,13 +86,13 @@ X86LegalizerInfo::X86LegalizerInfo(const X86Subtarget &STI,
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}
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bool X86LegalizerInfo::legalizeIntrinsic(MachineInstr &MI,
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MachineRegisterInfo &MRI,
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MachineIRBuilder &MIRBuilder) const {
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MachineIRBuilder &MIRBuilder,
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GISelChangeObserver &Observer) const {
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switch (MI.getIntrinsicID()) {
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case Intrinsic::memcpy:
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case Intrinsic::memset:
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case Intrinsic::memmove:
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if (createMemLibcall(MIRBuilder, MRI, MI) ==
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if (createMemLibcall(MIRBuilder, *MIRBuilder.getMRI(), MI) ==
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LegalizerHelper::UnableToLegalize)
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return false;
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MI.eraseFromParent();
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@ -32,8 +32,8 @@ private:
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public:
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X86LegalizerInfo(const X86Subtarget &STI, const X86TargetMachine &TM);
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bool legalizeIntrinsic(MachineInstr &MI, MachineRegisterInfo &MRI,
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MachineIRBuilder &MIRBuilder) const override;
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bool legalizeIntrinsic(MachineInstr &MI, MachineIRBuilder &MIRBuilder,
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GISelChangeObserver &Observer) const override;
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private:
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void setLegalizerInfo32bit();
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