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[X86] Add a non-ambiguous check prefix to lwp-intrinsics.ll for the case when only the feature is specified and not the CPUs. 

Not sure why the script doesn't notice this. We just weren't checking the +lwp command in 32-bit mode in 2 of the test cases.

llvm-svn: 360282
This commit is contained in:
Craig Topper 2019-05-08 19:20:53 +00:00
parent cdaf5a069c
commit c5db081f8d
1 changed files with 19 additions and 2 deletions
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21
llvm/test/CodeGen/X86/lwp-intrinsics.ll
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@ -1,10 +1,10 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc < %s -mtriple=i686-unknown -mattr=+lwp | FileCheck %s --check-prefixes=X86
; RUN: llc < %s -mtriple=i686-unknown -mattr=+lwp | FileCheck %s --check-prefixes=X86,X86_LWP
; RUN: llc < %s -mtriple=i686-unknown -mcpu=bdver1 | FileCheck %s --check-prefixes=X86,BDVER1,X86_BDVER1
; RUN: llc < %s -mtriple=i686-unknown -mcpu=bdver2 | FileCheck %s --check-prefixes=X86,BDVER2,X86_BDVER2
; RUN: llc < %s -mtriple=i686-unknown -mcpu=bdver3 | FileCheck %s --check-prefixes=X86,BDVER3,X86_BDVER3
; RUN: llc < %s -mtriple=i686-unknown -mcpu=bdver4 | FileCheck %s --check-prefixes=X86,BDVER4,X86_BDVER4
; RUN: llc < %s -mtriple=x86_64-unknown -mattr=+lwp | FileCheck %s --check-prefixes=X64
; RUN: llc < %s -mtriple=x86_64-unknown -mattr=+lwp | FileCheck %s --check-prefixes=X64,X64_LWP
; RUN: llc < %s -mtriple=x86_64-unknown -mcpu=bdver1 | FileCheck %s --check-prefixes=X64,BDVER1,X64_BDVER1
; RUN: llc < %s -mtriple=x86_64-unknown -mcpu=bdver2 | FileCheck %s --check-prefixes=X64,BDVER2,X64_BDVER2
; RUN: llc < %s -mtriple=x86_64-unknown -mcpu=bdver3 | FileCheck %s --check-prefixes=X64,BDVER3,X64_BDVER3
@ -40,6 +40,15 @@ define i8* @test_slwpcb(i8 *%a0) nounwind {
}
define i8 @test_lwpins32_rri(i32 %a0, i32 %a1) nounwind {
; X86_LWP-LABEL: test_lwpins32_rri:
; X86_LWP: # %bb.0:
; X86_LWP-NEXT: movl {{[0-9]+}}(%esp), %eax
; X86_LWP-NEXT: movl {{[0-9]+}}(%esp), %ecx
; X86_LWP-NEXT: addl %ecx, %ecx
; X86_LWP-NEXT: lwpins $-1985229329, %ecx, %eax # imm = 0x89ABCDEF
; X86_LWP-NEXT: setb %al
; X86_LWP-NEXT: retl
;
; X86_BDVER1-LABEL: test_lwpins32_rri:
; X86_BDVER1: # %bb.0:
; X86_BDVER1-NEXT: movl {{[0-9]+}}(%esp), %ecx
@ -107,6 +116,14 @@ define i8 @test_lwpins32_rmi(i32 %a0, i32 *%p1) nounwind {
}
define void @test_lwpval32_rri(i32 %a0, i32 %a1) nounwind {
; X86_LWP-LABEL: test_lwpval32_rri:
; X86_LWP: # %bb.0:
; X86_LWP-NEXT: movl {{[0-9]+}}(%esp), %eax
; X86_LWP-NEXT: movl {{[0-9]+}}(%esp), %ecx
; X86_LWP-NEXT: addl %ecx, %ecx
; X86_LWP-NEXT: lwpval $-19088744, %ecx, %eax # imm = 0xFEDCBA98
; X86_LWP-NEXT: retl
;
; X86_BDVER1-LABEL: test_lwpval32_rri:
; X86_BDVER1: # %bb.0:
; X86_BDVER1-NEXT: movl {{[0-9]+}}(%esp), %ecx