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GlobalISel: Lower G_WRITE_REGISTER

This commit is contained in:
Matt Arsenault 2020-01-12 13:29:44 -05:00
parent 2103e08b3f
commit c5c1bb3374
5 changed files with 31 additions and 12 deletions
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2
llvm/include/llvm/CodeGen/GlobalISel/LegalizerHelper.h
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@ -265,7 +265,7 @@ public:
LegalizeResult lowerSADDO_SSUBO(MachineInstr &MI); LegalizeResult lowerSADDO_SSUBO(MachineInstr &MI);
LegalizeResult lowerBswap(MachineInstr &MI); LegalizeResult lowerBswap(MachineInstr &MI);
LegalizeResult lowerBitreverse(MachineInstr &MI); LegalizeResult lowerBitreverse(MachineInstr &MI);
LegalizeResult lowerReadRegister(MachineInstr &MI); LegalizeResult lowerReadWriteRegister(MachineInstr &MI);
private: private:
MachineRegisterInfo &MRI; MachineRegisterInfo &MRI;

7
llvm/lib/CodeGen/GlobalISel/IRTranslator.cpp
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@ -1533,6 +1533,13 @@ bool IRTranslator::translateKnownIntrinsic(const CallInst &CI, Intrinsic::ID ID,
.addMetadata(cast<MDNode>(cast<MetadataAsValue>(Arg)->getMetadata())); .addMetadata(cast<MDNode>(cast<MetadataAsValue>(Arg)->getMetadata()));
return true; return true;
} }
case Intrinsic::write_register: {
Value *Arg = CI.getArgOperand(0);
MIRBuilder.buildInstr(TargetOpcode::G_WRITE_REGISTER)
.addMetadata(cast<MDNode>(cast<MetadataAsValue>(Arg)->getMetadata()))
.addUse(getOrCreateVReg(*CI.getArgOperand(1)));
return true;
}
} }
return false; return false;
} }

30
llvm/lib/CodeGen/GlobalISel/LegalizerHelper.cpp
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@ -2478,7 +2478,8 @@ LegalizerHelper::lower(MachineInstr &MI, unsigned TypeIdx, LLT Ty) {
case G_BITREVERSE: case G_BITREVERSE:
return lowerBitreverse(MI); return lowerBitreverse(MI);
case G_READ_REGISTER: case G_READ_REGISTER:
return lowerReadRegister(MI); case G_WRITE_REGISTER:
return lowerReadWriteRegister(MI);
} }
} }
@ -4774,20 +4775,29 @@ LegalizerHelper::lowerBitreverse(MachineInstr &MI) {
} }
LegalizerHelper::LegalizeResult LegalizerHelper::LegalizeResult
LegalizerHelper::lowerReadRegister(MachineInstr &MI) { LegalizerHelper::lowerReadWriteRegister(MachineInstr &MI) {
Register Dst = MI.getOperand(0).getReg();
const LLT Ty = MRI.getType(Dst);
const MDString *RegStr = cast<MDString>(
cast<MDNode>(MI.getOperand(1).getMetadata())->getOperand(0));
MachineFunction &MF = MIRBuilder.getMF(); MachineFunction &MF = MIRBuilder.getMF();
const TargetSubtargetInfo &STI = MF.getSubtarget(); const TargetSubtargetInfo &STI = MF.getSubtarget();
const TargetLowering *TLI = STI.getTargetLowering(); const TargetLowering *TLI = STI.getTargetLowering();
Register Reg = TLI->getRegisterByName(RegStr->getString().data(), Ty, MF);
if (!Reg.isValid()) bool IsRead = MI.getOpcode() == TargetOpcode::G_READ_REGISTER;
int NameOpIdx = IsRead ? 1 : 0;
int ValRegIndex = IsRead ? 0 : 1;
Register ValReg = MI.getOperand(ValRegIndex).getReg();
const LLT Ty = MRI.getType(ValReg);
const MDString *RegStr = cast<MDString>(
cast<MDNode>(MI.getOperand(NameOpIdx).getMetadata())->getOperand(0));
Register PhysReg = TLI->getRegisterByName(RegStr->getString().data(), Ty, MF);
if (!PhysReg.isValid())
return UnableToLegalize; return UnableToLegalize;
MIRBuilder.buildCopy(Dst, Reg); if (IsRead)
MIRBuilder.buildCopy(ValReg, PhysReg);
else
MIRBuilder.buildCopy(PhysReg, ValReg);
MI.eraseFromParent(); MI.eraseFromParent();
return Legalized; return Legalized;
} }

2
llvm/test/CodeGen/AArch64/GlobalISel/arm64-fallback.ll
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@ -85,7 +85,7 @@ define i64 @atomic_ops(i64* %addr) {
; Make sure we don't mess up metadata arguments. ; Make sure we don't mess up metadata arguments.
declare void @llvm.write_register.i64(metadata, i64) declare void @llvm.write_register.i64(metadata, i64)
; FALLBACK-WITH-REPORT-ERR: remark: <unknown>:0:0: unable to translate instruction: call: ' call void @llvm.write_register.i64(metadata !0, i64 0)' (in function: test_write_register_intrin) ; FALLBACK-WITH-REPORT-ERR: remark: <unknown>:0:0: unable to legalize instruction: G_WRITE_REGISTER !0, %0:_(s64) (in function: test_write_register_intrin)
; FALLBACK-WITH-REPORT-ERR: warning: Instruction selection used fallback path for test_write_register_intrin ; FALLBACK-WITH-REPORT-ERR: warning: Instruction selection used fallback path for test_write_register_intrin
; FALLBACK-WITH-REPORT-LABEL: test_write_register_intrin: ; FALLBACK-WITH-REPORT-LABEL: test_write_register_intrin:
define void @test_write_register_intrin() { define void @test_write_register_intrin() {

2
llvm/test/CodeGen/AMDGPU/GlobalISel/write_register.ll Normal file
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@ -0,0 +1,2 @@
; Runs original SDAG test with -global-isel
; RUN: llc -global-isel -march=amdgcn -mcpu=bonaire -enable-misched=0 -verify-machineinstrs < %S/../write_register.ll | FileCheck -enable-var-scope %S/../write_register.ll