maxjhandsome
/
llvm-project
forked from OSchip/llvm-project
1
0
Fork 0
Code Issues Pull Requests Packages Releases Wiki Activity

Modify LowerFCOPYSIGN to handle Mips64. 

llvm-svn: 146080
This commit is contained in:
Akira Hatanaka 2011-12-07 21:48:50 +00:00
parent dd4ffaec8f
commit c5b5a8d8b1
2 changed files with 68 additions and 52 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

36
llvm/lib/Target/Mips/MipsISelLowering.cpp
View File

@ -1683,21 +1683,29 @@ SDValue MipsTargetLowering::LowerVASTART(SDValue Op, SelectionDAG &DAG) const {
MachinePointerInfo(SV),
false, false, 0);
}
static SDValue LowerFCOPYSIGN32(SDValue Op, SelectionDAG &DAG) {
// Called if the size of integer registers is large enough to hold the whole
// floating point number.
static SDValue LowerFCOPYSIGNLargeIntReg(SDValue Op, SelectionDAG &DAG) {
// FIXME: Use ext/ins instructions if target architecture is Mips32r2.
EVT ValTy = Op.getValueType();
EVT IntValTy = MVT::getIntegerVT(ValTy.getSizeInBits());
uint64_t Mask = (uint64_t)1 << (ValTy.getSizeInBits() - 1);
DebugLoc dl = Op.getDebugLoc();
SDValue Op0 = DAG.getNode(ISD::BITCAST, dl, MVT::i32, Op.getOperand(0));
SDValue Op1 = DAG.getNode(ISD::BITCAST, dl, MVT::i32, Op.getOperand(1));
SDValue And0 = DAG.getNode(ISD::AND, dl, MVT::i32, Op0,
DAG.getConstant(0x7fffffff, MVT::i32));
SDValue And1 = DAG.getNode(ISD::AND, dl, MVT::i32, Op1,
DAG.getConstant(0x80000000, MVT::i32));
SDValue Result = DAG.getNode(ISD::OR, dl, MVT::i32, And0, And1);
return DAG.getNode(ISD::BITCAST, dl, MVT::f32, Result);
SDValue Op0 = DAG.getNode(ISD::BITCAST, dl, IntValTy, Op.getOperand(0));
SDValue Op1 = DAG.getNode(ISD::BITCAST, dl, IntValTy, Op.getOperand(1));
SDValue And0 = DAG.getNode(ISD::AND, dl, IntValTy, Op0,
DAG.getConstant(Mask - 1, IntValTy));
SDValue And1 = DAG.getNode(ISD::AND, dl, IntValTy, Op1,
DAG.getConstant(Mask, IntValTy));
SDValue Result = DAG.getNode(ISD::OR, dl, IntValTy, And0, And1);
return DAG.getNode(ISD::BITCAST, dl, ValTy, Result);
}
static SDValue LowerFCOPYSIGN64(SDValue Op, SelectionDAG &DAG, bool isLittle) {
// Called if the size of integer registers is not large enough to hold the whole
// floating point number (e.g. f64 & 32-bit integer register).
static SDValue
LowerFCOPYSIGNSmallIntReg(SDValue Op, SelectionDAG &DAG, bool isLittle) {
// FIXME:
// Use ext/ins instructions if target architecture is Mips32r2.
// Eliminate redundant mfc1 and mtc1 instructions.
@ -1732,10 +1740,10 @@ SDValue MipsTargetLowering::LowerFCOPYSIGN(SDValue Op, SelectionDAG &DAG)
assert(Ty == MVT::f32 || Ty == MVT::f64);
if (Ty == MVT::f32)
return LowerFCOPYSIGN32(Op, DAG);
if (Ty == MVT::f32 || HasMips64)
return LowerFCOPYSIGNLargeIntReg(Op, DAG);
else
return LowerFCOPYSIGN64(Op, DAG, Subtarget->isLittle());
return LowerFCOPYSIGNSmallIntReg(Op, DAG, Subtarget->isLittle());
}
SDValue MipsTargetLowering::

84
llvm/test/CodeGen/Mips/fcopysign.ll
View File

@ -1,34 +1,42 @@
; RUN: llc < %s -march=mipsel | FileCheck %s -check-prefix=CHECK-EL
; RUN: llc < %s -march=mips | FileCheck %s -check-prefix=CHECK-EB
; RUN: llc < %s -march=mipsel | FileCheck %s -check-prefix=MIPS32-EL
; RUN: llc < %s -march=mips | FileCheck %s -check-prefix=MIPS32-EB
; RUN: llc < %s -march=mips64el -mcpu=mips64 -mattr=n64 | FileCheck %s -check-prefix=MIPS64
define double @func0(double %d0, double %d1) nounwind readnone {
entry:
; CHECK-EL: func0:
; CHECK-EL: lui $[[T1:[0-9]+]], 32768
; CHECK-EL: ori $[[MSK1:[0-9]+]], $[[T1]], 0
; CHECK-EL: mfc1 $[[HI0:[0-9]+]], $f15
; CHECK-EL: and $[[AND1:[0-9]+]], $[[HI0]], $[[MSK1]]
; CHECK-EL: lui $[[T0:[0-9]+]], 32767
; CHECK-EL: ori $[[MSK0:[0-9]+]], $[[T0]], 65535
; CHECK-EL: mfc1 $[[HI1:[0-9]+]], $f13
; CHECK-EL: and $[[AND0:[0-9]+]], $[[HI1]], $[[MSK0]]
; CHECK-EL: or $[[OR:[0-9]+]], $[[AND0]], $[[AND1]]
; CHECK-EL: mfc1 $[[LO0:[0-9]+]], $f12
; CHECK-EL: mtc1 $[[LO0]], $f0
; CHECK-EL: mtc1 $[[OR]], $f1
; MIPS32-EL: func0:
; MIPS32-EL: lui $[[T1:[0-9]+]], 32768
; MIPS32-EL: ori $[[MSK1:[0-9]+]], $[[T1]], 0
; MIPS32-EL: mfc1 $[[HI0:[0-9]+]], $f15
; MIPS32-EL: and $[[AND1:[0-9]+]], $[[HI0]], $[[MSK1]]
; MIPS32-EL: lui $[[T0:[0-9]+]], 32767
; MIPS32-EL: ori $[[MSK0:[0-9]+]], $[[T0]], 65535
; MIPS32-EL: mfc1 $[[HI1:[0-9]+]], $f13
; MIPS32-EL: and $[[AND0:[0-9]+]], $[[HI1]], $[[MSK0]]
; MIPS32-EL: or $[[OR:[0-9]+]], $[[AND0]], $[[AND1]]
; MIPS32-EL: mfc1 $[[LO0:[0-9]+]], $f12
; MIPS32-EL: mtc1 $[[LO0]], $f0
; MIPS32-EL: mtc1 $[[OR]], $f1
;
; CHECK-EB: lui $[[T1:[0-9]+]], 32768
; CHECK-EB: ori $[[MSK1:[0-9]+]], $[[T1]], 0
; CHECK-EB: mfc1 $[[HI1:[0-9]+]], $f14
; CHECK-EB: and $[[AND1:[0-9]+]], $[[HI1]], $[[MSK1]]
; CHECK-EB: lui $[[T0:[0-9]+]], 32767
; CHECK-EB: ori $[[MSK0:[0-9]+]], $[[T0]], 65535
; CHECK-EB: mfc1 $[[HI0:[0-9]+]], $f12
; CHECK-EB: and $[[AND0:[0-9]+]], $[[HI0]], $[[MSK0]]
; CHECK-EB: or $[[OR:[0-9]+]], $[[AND0]], $[[AND1]]
; CHECK-EB: mfc1 $[[LO0:[0-9]+]], $f13
; CHECK-EB: mtc1 $[[OR]], $f0
; CHECK-EB: mtc1 $[[LO0]], $f1
; MIPS32-EB: lui $[[T1:[0-9]+]], 32768
; MIPS32-EB: ori $[[MSK1:[0-9]+]], $[[T1]], 0
; MIPS32-EB: mfc1 $[[HI1:[0-9]+]], $f14
; MIPS32-EB: and $[[AND1:[0-9]+]], $[[HI1]], $[[MSK1]]
; MIPS32-EB: lui $[[T0:[0-9]+]], 32767
; MIPS32-EB: ori $[[MSK0:[0-9]+]], $[[T0]], 65535
; MIPS32-EB: mfc1 $[[HI0:[0-9]+]], $f12
; MIPS32-EB: and $[[AND0:[0-9]+]], $[[HI0]], $[[MSK0]]
; MIPS32-EB: or $[[OR:[0-9]+]], $[[AND0]], $[[AND1]]
; MIPS32-EB: mfc1 $[[LO0:[0-9]+]], $f13
; MIPS32-EB: mtc1 $[[OR]], $f0
; MIPS32-EB: mtc1 $[[LO0]], $f1
; MIPS64: dmfc1 $[[R0:[0-9]+]], $f13
; MIPS64: and $[[R1:[0-9]+]], $[[R0]], ${{[0-9]+}}
; MIPS64: dmfc1 $[[R2:[0-9]+]], $f12
; MIPS64: and $[[R3:[0-9]+]], $[[R2]], ${{[0-9]+}}
; MIPS64: or $[[R4:[0-9]+]], $[[R3]], $[[R1]]
; MIPS64: dmtc1 $[[R4]], $f0
%call = tail call double @copysign(double %d0, double %d1) nounwind readnone
ret double %call
}
@ -37,17 +45,17 @@ declare double @copysign(double, double) nounwind readnone
define float @func1(float %f0, float %f1) nounwind readnone {
entry:
; CHECK-EL: func1:
; CHECK-EL: lui $[[T1:[0-9]+]], 32768
; CHECK-EL: ori $[[MSK1:[0-9]+]], $[[T1]], 0
; CHECK-EL: mfc1 $[[ARG1:[0-9]+]], $f14
; CHECK-EL: and $[[T3:[0-9]+]], $[[ARG1]], $[[MSK1]]
; CHECK-EL: lui $[[T0:[0-9]+]], 32767
; CHECK-EL: ori $[[MSK0:[0-9]+]], $[[T0]], 65535
; CHECK-EL: mfc1 $[[ARG0:[0-9]+]], $f12
; CHECK-EL: and $[[T2:[0-9]+]], $[[ARG0]], $[[MSK0]]
; CHECK-EL: or $[[T4:[0-9]+]], $[[T2]], $[[T3]]
; CHECK-EL: mtc1 $[[T4]], $f0
; MIPS32-EL: func1:
; MIPS32-EL: lui $[[T1:[0-9]+]], 32768
; MIPS32-EL: ori $[[MSK1:[0-9]+]], $[[T1]], 0
; MIPS32-EL: mfc1 $[[ARG1:[0-9]+]], $f14
; MIPS32-EL: and $[[T3:[0-9]+]], $[[ARG1]], $[[MSK1]]
; MIPS32-EL: lui $[[T0:[0-9]+]], 32767
; MIPS32-EL: ori $[[MSK0:[0-9]+]], $[[T0]], 65535
; MIPS32-EL: mfc1 $[[ARG0:[0-9]+]], $f12
; MIPS32-EL: and $[[T2:[0-9]+]], $[[ARG0]], $[[MSK0]]
; MIPS32-EL: or $[[T4:[0-9]+]], $[[T2]], $[[T3]]
; MIPS32-EL: mtc1 $[[T4]], $f0
%call = tail call float @copysignf(float %f0, float %f1) nounwind readnone
ret float %call
}