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[AVX512] Add aliases for vcvttss2si{l|q}, vcvttsd2si{l|q}, vcvttss2usi{l|q}, vcvttsd2usi{l|q} instructions. 

Differential Revision: http://reviews.llvm.org/D23111

llvm-svn: 277586
This commit is contained in:
Igor Breger 2016-08-03 10:58:05 +00:00
parent 7b80ff3c7e
commit c59b3a2236
2 changed files with 170 additions and 34 deletions
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76
llvm/lib/Target/X86/X86InstrAVX512.td
View File

@ -5399,64 +5399,72 @@ let isCodeGenOnly = 1 , Predicates = [HasAVX512] in {
// Convert float/double to signed/unsigned int 32/64 with truncation // Convert float/double to signed/unsigned int 32/64 with truncation
multiclass avx512_cvt_s_all<bits<8> opc, string asm, X86VectorVTInfo _SrcRC, multiclass avx512_cvt_s_all<bits<8> opc, string asm, X86VectorVTInfo _SrcRC,
X86VectorVTInfo _DstRC, SDNode OpNode, X86VectorVTInfo _DstRC, SDNode OpNode,
SDNode OpNodeRnd>{ SDNode OpNodeRnd, string aliasStr>{
let Predicates = [HasAVX512] in { let Predicates = [HasAVX512] in {
def rr : SI<opc, MRMSrcReg, (outs _DstRC.RC:$dst), (ins _SrcRC.FRC:$src), def rr : AVX512<opc, MRMSrcReg, (outs _DstRC.RC:$dst), (ins _SrcRC.FRC:$src),
!strconcat(asm,"\t{$src, $dst|$dst, $src}"), !strconcat(asm,"\t{$src, $dst|$dst, $src}"),
[(set _DstRC.RC:$dst, (OpNode _SrcRC.FRC:$src))]>, EVEX; [(set _DstRC.RC:$dst, (OpNode _SrcRC.FRC:$src))]>, EVEX;
def rb : SI<opc, MRMSrcReg, (outs _DstRC.RC:$dst), (ins _SrcRC.FRC:$src), def rb : AVX512<opc, MRMSrcReg, (outs _DstRC.RC:$dst), (ins _SrcRC.FRC:$src),
!strconcat(asm,"\t{{sae}, $src, $dst|$dst, $src, {sae}}"), !strconcat(asm,"\t{{sae}, $src, $dst|$dst, $src, {sae}}"),
[]>, EVEX, EVEX_B; []>, EVEX, EVEX_B;
def rm : SI<opc, MRMSrcMem, (outs _DstRC.RC:$dst), (ins _SrcRC.ScalarMemOp:$src), def rm : AVX512<opc, MRMSrcMem, (outs _DstRC.RC:$dst), (ins _SrcRC.ScalarMemOp:$src),
!strconcat(asm,"\t{$src, $dst|$dst, $src}"), !strconcat(asm,"\t{$src, $dst|$dst, $src}"),
[(set _DstRC.RC:$dst, (OpNode (_SrcRC.ScalarLdFrag addr:$src)))]>, [(set _DstRC.RC:$dst, (OpNode (_SrcRC.ScalarLdFrag addr:$src)))]>,
EVEX; EVEX;
def : InstAlias<asm # aliasStr # "\t{$src, $dst|$dst, $src}",
(!cast<Instruction>(NAME # "rr") _DstRC.RC:$dst, _SrcRC.FRC:$src), 0>;
def : InstAlias<asm # aliasStr # "\t\t{{sae}, $src, $dst|$dst, $src, {sae}}",
(!cast<Instruction>(NAME # "rb") _DstRC.RC:$dst, _SrcRC.FRC:$src), 0>;
def : InstAlias<asm # aliasStr # "\t{$src, $dst|$dst, $src}",
(!cast<Instruction>(NAME # "rm") _DstRC.RC:$dst,
_SrcRC.ScalarMemOp:$src), 0>;
let isCodeGenOnly = 1 in { let isCodeGenOnly = 1 in {
def rr_Int : SI<opc, MRMSrcReg, (outs _DstRC.RC:$dst), (ins _SrcRC.RC:$src), def rr_Int : AVX512<opc, MRMSrcReg, (outs _DstRC.RC:$dst), (ins _SrcRC.RC:$src),
!strconcat(asm,"\t{$src, $dst|$dst, $src}"), !strconcat(asm,"\t{$src, $dst|$dst, $src}"),
[(set _DstRC.RC:$dst, (OpNodeRnd (_SrcRC.VT _SrcRC.RC:$src), [(set _DstRC.RC:$dst, (OpNodeRnd (_SrcRC.VT _SrcRC.RC:$src),
(i32 FROUND_CURRENT)))]>, EVEX, VEX_LIG; (i32 FROUND_CURRENT)))]>, EVEX, VEX_LIG;
def rb_Int : SI<opc, MRMSrcReg, (outs _DstRC.RC:$dst), (ins _SrcRC.RC:$src), def rb_Int : AVX512<opc, MRMSrcReg, (outs _DstRC.RC:$dst), (ins _SrcRC.RC:$src),
!strconcat(asm,"\t{{sae}, $src, $dst|$dst, $src, {sae}}"), !strconcat(asm,"\t{{sae}, $src, $dst|$dst, $src, {sae}}"),
[(set _DstRC.RC:$dst, (OpNodeRnd (_SrcRC.VT _SrcRC.RC:$src), [(set _DstRC.RC:$dst, (OpNodeRnd (_SrcRC.VT _SrcRC.RC:$src),
(i32 FROUND_NO_EXC)))]>, (i32 FROUND_NO_EXC)))]>,
EVEX,VEX_LIG , EVEX_B; EVEX,VEX_LIG , EVEX_B;
let mayLoad = 1, hasSideEffects = 0 in let mayLoad = 1, hasSideEffects = 0 in
def rm_Int : SI<opc, MRMSrcMem, (outs _DstRC.RC:$dst), def rm_Int : AVX512<opc, MRMSrcMem, (outs _DstRC.RC:$dst),
(ins _SrcRC.MemOp:$src), (ins _SrcRC.MemOp:$src),
!strconcat(asm,"\t{$src, $dst|$dst, $src}"), !strconcat(asm,"\t{$src, $dst|$dst, $src}"),
[]>, EVEX, VEX_LIG; []>, EVEX, VEX_LIG;
} // isCodeGenOnly = 1 } // isCodeGenOnly = 1
} //HasAVX512 } //HasAVX512
} }
defm VCVTTSS2SIZ: avx512_cvt_s_all<0x2C, "cvttss2si", f32x_info, i32x_info, defm VCVTTSS2SIZ: avx512_cvt_s_all<0x2C, "vcvttss2si", f32x_info, i32x_info,
fp_to_sint,X86cvtts2IntRnd>, fp_to_sint, X86cvtts2IntRnd, "{l}">,
XS, EVEX_CD8<32, CD8VT1>; XS, EVEX_CD8<32, CD8VT1>;
defm VCVTTSS2SI64Z: avx512_cvt_s_all<0x2C, "cvttss2si", f32x_info, i64x_info, defm VCVTTSS2SI64Z: avx512_cvt_s_all<0x2C, "vcvttss2si", f32x_info, i64x_info,
fp_to_sint,X86cvtts2IntRnd>, fp_to_sint, X86cvtts2IntRnd, "{q}">,
VEX_W, XS, EVEX_CD8<32, CD8VT1>; VEX_W, XS, EVEX_CD8<32, CD8VT1>;
defm VCVTTSD2SIZ: avx512_cvt_s_all<0x2C, "cvttsd2si", f64x_info, i32x_info, defm VCVTTSD2SIZ: avx512_cvt_s_all<0x2C, "vcvttsd2si", f64x_info, i32x_info,
fp_to_sint,X86cvtts2IntRnd>, fp_to_sint, X86cvtts2IntRnd, "{l}">,
XD, EVEX_CD8<64, CD8VT1>; XD, EVEX_CD8<64, CD8VT1>;
defm VCVTTSD2SI64Z: avx512_cvt_s_all<0x2C, "cvttsd2si", f64x_info, i64x_info, defm VCVTTSD2SI64Z: avx512_cvt_s_all<0x2C, "vcvttsd2si", f64x_info, i64x_info,
fp_to_sint,X86cvtts2IntRnd>, fp_to_sint, X86cvtts2IntRnd, "{q}">,
VEX_W, XD, EVEX_CD8<64, CD8VT1>; VEX_W, XD, EVEX_CD8<64, CD8VT1>;
defm VCVTTSS2USIZ: avx512_cvt_s_all<0x78, "cvttss2usi", f32x_info, i32x_info, defm VCVTTSS2USIZ: avx512_cvt_s_all<0x78, "vcvttss2usi", f32x_info, i32x_info,
fp_to_uint,X86cvtts2UIntRnd>, fp_to_uint, X86cvtts2UIntRnd, "{l}">,
XS, EVEX_CD8<32, CD8VT1>; XS, EVEX_CD8<32, CD8VT1>;
defm VCVTTSS2USI64Z: avx512_cvt_s_all<0x78, "cvttss2usi", f32x_info, i64x_info, defm VCVTTSS2USI64Z: avx512_cvt_s_all<0x78, "vcvttss2usi", f32x_info, i64x_info,
fp_to_uint,X86cvtts2UIntRnd>, fp_to_uint, X86cvtts2UIntRnd, "{q}">,
XS,VEX_W, EVEX_CD8<32, CD8VT1>; XS,VEX_W, EVEX_CD8<32, CD8VT1>;
defm VCVTTSD2USIZ: avx512_cvt_s_all<0x78, "cvttsd2usi", f64x_info, i32x_info, defm VCVTTSD2USIZ: avx512_cvt_s_all<0x78, "vcvttsd2usi", f64x_info, i32x_info,
fp_to_uint,X86cvtts2UIntRnd>, fp_to_uint, X86cvtts2UIntRnd, "{l}">,
XD, EVEX_CD8<64, CD8VT1>; XD, EVEX_CD8<64, CD8VT1>;
defm VCVTTSD2USI64Z: avx512_cvt_s_all<0x78, "cvttsd2usi", f64x_info, i64x_info, defm VCVTTSD2USI64Z: avx512_cvt_s_all<0x78, "vcvttsd2usi", f64x_info, i64x_info,
fp_to_uint,X86cvtts2UIntRnd>, fp_to_uint, X86cvtts2UIntRnd, "{q}">,
XD, VEX_W, EVEX_CD8<64, CD8VT1>; XD, VEX_W, EVEX_CD8<64, CD8VT1>;
let Predicates = [HasAVX512] in { let Predicates = [HasAVX512] in {
def : Pat<(i32 (int_x86_sse_cvttss2si (v4f32 VR128X:$src))), def : Pat<(i32 (int_x86_sse_cvttss2si (v4f32 VR128X:$src))),

128
llvm/test/MC/X86/avx512-encodings.s
View File

@ -19483,3 +19483,131 @@ vpermilpd $0x23, 0x400(%rbx), %zmm2
//CHECK: vcmptruepd -1024(%rdx){1to8}, %zmm30, %k5 //CHECK: vcmptruepd -1024(%rdx){1to8}, %zmm30, %k5
//CHECK: encoding: [0x62,0xf1,0x8d,0x50,0xc2,0x6a,0x80,0x0f] //CHECK: encoding: [0x62,0xf1,0x8d,0x50,0xc2,0x6a,0x80,0x0f]
vcmptrue_uqpd -1024(%rdx){1to8}, %zmm30, %k5 vcmptrue_uqpd -1024(%rdx){1to8}, %zmm30, %k5
// CHECK: vcvttss2si %xmm20, %rax
// CHECK: encoding: [0x62,0xb1,0xfe,0x08,0x2c,0xc4]
vcvttss2si %xmm20, %rax
// CHECK: vcvttss2si %xmm20, %eax
// CHECK: encoding: [0x62,0xb1,0x7e,0x08,0x2c,0xc4]
vcvttss2si %xmm20, %eax
// CHECK: vcvttsd2si %xmm20, %rax
// CHECK: encoding: [0x62,0xb1,0xff,0x08,0x2c,0xc4]
vcvttsd2si %xmm20, %rax
// CHECK: vcvttsd2si %xmm20, %eax
// CHECK: encoding: [0x62,0xb1,0x7f,0x08,0x2c,0xc4]
vcvttsd2si %xmm20, %eax
// CHECK: vcvttss2usi %xmm20, %rax
// CHECK: encoding: [0x62,0xb1,0xfe,0x08,0x78,0xc4]
vcvttss2usi %xmm20, %rax
// CHECK: vcvttss2usi %xmm20, %eax
// CHECK: encoding: [0x62,0xb1,0x7e,0x08,0x78,0xc4]
vcvttss2usi %xmm20, %eax
// CHECK: vcvttsd2usi %xmm20, %rax
// CHECK: encoding: [0x62,0xb1,0xff,0x08,0x78,0xc4]
vcvttsd2usi %xmm20, %rax
// CHECK: vcvttsd2usi %xmm20, %eax
// CHECK: encoding: [0x62,0xb1,0x7f,0x08,0x78,0xc4]
vcvttsd2usi %xmm20, %eax
// CHECK: vcvttss2si (%rcx), %rax
// CHECK: encoding: [0x62,0xf1,0xfe,0x08,0x2c,0x01]
vcvttss2si (%rcx), %rax
// CHECK: vcvttss2si (%rcx), %eax
// CHECK: encoding: [0x62,0xf1,0x7e,0x08,0x2c,0x01]
vcvttss2si (%rcx), %eax
// CHECK: vcvttsd2si (%rcx), %rax
// CHECK: encoding: [0x62,0xf1,0xff,0x08,0x2c,0x01]
vcvttsd2si (%rcx), %rax
// CHECK: vcvttsd2si (%rcx), %eax
// CHECK: encoding: [0x62,0xf1,0x7f,0x08,0x2c,0x01]
vcvttsd2si (%rcx), %eax
// CHECK: vcvttss2usi (%rcx), %rax
// CHECK: encoding: [0x62,0xf1,0xfe,0x08,0x78,0x01]
vcvttss2usi (%rcx), %rax
// CHECK: vcvttss2usi (%rcx), %eax
// CHECK: encoding: [0x62,0xf1,0x7e,0x08,0x78,0x01]
vcvttss2usi (%rcx), %eax
// CHECK: vcvttsd2usi (%rcx), %rax
// CHECK: encoding: [0x62,0xf1,0xff,0x08,0x78,0x01]
vcvttsd2usi (%rcx), %rax
// CHECK: vcvttsd2usi (%rcx), %eax
// CHECK: encoding: [0x62,0xf1,0x7f,0x08,0x78,0x01]
vcvttsd2usi (%rcx), %eax
// CHECK: vcvttss2si %xmm20, %rax
// CHECK: encoding: [0x62,0xb1,0xfe,0x08,0x2c,0xc4]
vcvttss2siq %xmm20, %rax
// CHECK: vcvttss2si %xmm20, %eax
// CHECK: encoding: [0x62,0xb1,0x7e,0x08,0x2c,0xc4]
vcvttss2sil %xmm20, %eax
// CHECK: vcvttsd2si %xmm20, %rax
// CHECK: encoding: [0x62,0xb1,0xff,0x08,0x2c,0xc4]
vcvttsd2siq %xmm20, %rax
// CHECK: vcvttsd2si %xmm20, %eax
// CHECK: encoding: [0x62,0xb1,0x7f,0x08,0x2c,0xc4]
vcvttsd2sil %xmm20, %eax
// CHECK: vcvttss2usi %xmm20, %rax
// CHECK: encoding: [0x62,0xb1,0xfe,0x08,0x78,0xc4]
vcvttss2usiq %xmm20, %rax
// CHECK: vcvttss2usi %xmm20, %eax
// CHECK: encoding: [0x62,0xb1,0x7e,0x08,0x78,0xc4]
vcvttss2usil %xmm20, %eax
// CHECK: vcvttsd2usi %xmm20, %rax
// CHECK: encoding: [0x62,0xb1,0xff,0x08,0x78,0xc4]
vcvttsd2usiq %xmm20, %rax
// CHECK: vcvttsd2usi %xmm20, %eax
// CHECK: encoding: [0x62,0xb1,0x7f,0x08,0x78,0xc4]
vcvttsd2usil %xmm20, %eax
// CHECK: vcvttss2si (%rcx), %rax
// CHECK: encoding: [0x62,0xf1,0xfe,0x08,0x2c,0x01]
vcvttss2siq (%rcx), %rax
// CHECK: vcvttss2si (%rcx), %eax
// CHECK: encoding: [0x62,0xf1,0x7e,0x08,0x2c,0x01]
vcvttss2sil (%rcx), %eax
// CHECK: vcvttsd2si (%rcx), %rax
// CHECK: encoding: [0x62,0xf1,0xff,0x08,0x2c,0x01]
vcvttsd2siq (%rcx), %rax
// CHECK: vcvttsd2si (%rcx), %eax
// CHECK: encoding: [0x62,0xf1,0x7f,0x08,0x2c,0x01]
vcvttsd2sil (%rcx), %eax
// CHECK: vcvttss2usi (%rcx), %rax
// CHECK: encoding: [0x62,0xf1,0xfe,0x08,0x78,0x01]
vcvttss2usiq (%rcx), %rax
// CHECK: vcvttss2usi (%rcx), %eax
// CHECK: encoding: [0x62,0xf1,0x7e,0x08,0x78,0x01]
vcvttss2usil (%rcx), %eax
// CHECK: vcvttsd2usi (%rcx), %rax
// CHECK: encoding: [0x62,0xf1,0xff,0x08,0x78,0x01]
vcvttsd2usiq (%rcx), %rax
// CHECK: vcvttsd2usi (%rcx), %eax
// CHECK: encoding: [0x62,0xf1,0x7f,0x08,0x78,0x01]
vcvttsd2usil (%rcx), %eax