forked from OSchip/llvm-project
Fix encoding of 32-bit integer instructions. Change names of operands and nodes.
Remove unused classes. llvm-svn: 141757
This commit is contained in:
Akira Hatanaka
parent
d4e2552c73
commit
c57febff4a
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@ -286,56 +286,59 @@ class MArithR<bits<6> func, string instr_asm, SDNode op, bit isComm = 0> :
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FR<0x1c, func, (outs), (ins CPURegs:$rs, CPURegs:$rt),
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!strconcat(instr_asm, "\t$rs, $rt"),
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[(op CPURegs:$rs, CPURegs:$rt, LO, HI)], IIImul> {
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let rd = 0;
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let shamt = 0;
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let isCommutable = isComm;
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}
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// Logical
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let isCommutable = 1 in
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class LogicNOR<bits<6> op, bits<6> func, string instr_asm>:
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FR<op, func, (outs CPURegs:$dst), (ins CPURegs:$b, CPURegs:$c),
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!strconcat(instr_asm, "\t$dst, $b, $c"),
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[(set CPURegs:$dst, (not (or CPURegs:$b, CPURegs:$c)))], IIAlu>;
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FR<op, func, (outs CPURegs:$rd), (ins CPURegs:$rs, CPURegs:$rt),
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!strconcat(instr_asm, "\t$rd, $rs, $rt"),
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[(set CPURegs:$rd, (not (or CPURegs:$rs, CPURegs:$rt)))], IIAlu> {
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let shamt = 0;
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let isCommutable = 1;
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}
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// Shifts
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class LogicR_shift_rotate_imm<bits<6> func, bits<5> _rs, string instr_asm,
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SDNode OpNode>:
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FR<0x00, func, (outs CPURegs:$dst), (ins CPURegs:$b, shamt:$c),
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!strconcat(instr_asm, "\t$dst, $b, $c"),
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[(set CPURegs:$dst, (OpNode CPURegs:$b, (i32 immZExt5:$c)))], IIAlu> {
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FR<0x00, func, (outs CPURegs:$rd), (ins CPURegs:$rt, shamt:$shamt),
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!strconcat(instr_asm, "\t$rd, $rt, $shamt"),
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[(set CPURegs:$rd, (OpNode CPURegs:$rt, (i32 immZExt5:$shamt)))], IIAlu> {
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let rs = _rs;
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}
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class LogicR_shift_rotate_reg<bits<6> func, bits<5> _shamt, string instr_asm,
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class LogicR_shift_rotate_reg<bits<6> func, bits<5> isRotate, string instr_asm,
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SDNode OpNode>:
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FR<0x00, func, (outs CPURegs:$dst), (ins CPURegs:$c, CPURegs:$b),
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!strconcat(instr_asm, "\t$dst, $b, $c"),
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[(set CPURegs:$dst, (OpNode CPURegs:$b, CPURegs:$c))], IIAlu> {
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let shamt = _shamt;
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FR<0x00, func, (outs CPURegs:$rd), (ins CPURegs:$rs, CPURegs:$rt),
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!strconcat(instr_asm, "\t$rd, $rt, $rs"),
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[(set CPURegs:$rd, (OpNode CPURegs:$rt, CPURegs:$rs))], IIAlu> {
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let shamt = isRotate;
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}
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// Load Upper Imediate
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class LoadUpper<bits<6> op, string instr_asm>:
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FI< op,
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(outs CPURegs:$dst),
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(ins uimm16:$imm),
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!strconcat(instr_asm, "\t$dst, $imm"),
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[], IIAlu>;
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FI<op, (outs CPURegs:$rt), (ins uimm16:$imm),
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!strconcat(instr_asm, "\t$rt, $imm"), [], IIAlu> {
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let rs = 0;
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}
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// Memory Load/Store
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let canFoldAsLoad = 1 in
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class LoadM<bits<6> op, string instr_asm, PatFrag OpNode, RegisterClass RC,
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Operand MemOpnd, bit Pseudo>:
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FI<op, (outs RC:$dst), (ins MemOpnd:$addr),
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!strconcat(instr_asm, "\t$dst, $addr"),
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[(set RC:$dst, (OpNode addr:$addr))], IILoad> {
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FI<op, (outs RC:$rt), (ins MemOpnd:$addr),
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!strconcat(instr_asm, "\t$rt, $addr"),
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[(set RC:$rt, (OpNode addr:$addr))], IILoad> {
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let isPseudo = Pseudo;
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}
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class StoreM<bits<6> op, string instr_asm, PatFrag OpNode, RegisterClass RC,
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Operand MemOpnd, bit Pseudo>:
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FI<op, (outs), (ins RC:$dst, MemOpnd:$addr),
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!strconcat(instr_asm, "\t$dst, $addr"),
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[(OpNode RC:$dst, addr:$addr)], IIStore> {
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FI<op, (outs), (ins RC:$rt, MemOpnd:$addr),
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!strconcat(instr_asm, "\t$rt, $addr"),
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[(OpNode RC:$rt, addr:$addr)], IIStore> {
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let isPseudo = Pseudo;
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}
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@ -402,7 +405,9 @@ class SetCC_R<bits<6> op, bits<6> func, string instr_asm, PatFrag cond_op,
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FR<op, func, (outs CPURegs:$rd), (ins RC:$rs, RC:$rt),
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!strconcat(instr_asm, "\t$rd, $rs, $rt"),
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[(set CPURegs:$rd, (cond_op RC:$rs, RC:$rt))],
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IIAlu>;
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IIAlu> {
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let shamt = 0;
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}
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class SetCC_I<bits<6> op, string instr_asm, PatFrag cond_op, Operand Od,
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PatLeaf imm_type, RegisterClass RC>:
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@ -419,8 +424,12 @@ class JumpFJ<bits<6> op, string instr_asm>:
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let isBranch=1, isTerminator=1, isBarrier=1, rd=0, hasDelaySlot = 1 in
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class JumpFR<bits<6> op, bits<6> func, string instr_asm>:
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FR<op, func, (outs), (ins CPURegs:$target),
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!strconcat(instr_asm, "\t$target"), [(brind CPURegs:$target)], IIBranch>;
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FR<op, func, (outs), (ins CPURegs:$rs),
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!strconcat(instr_asm, "\t$rs"), [(brind CPURegs:$rs)], IIBranch> {
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let rt = 0;
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let rd = 0;
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let shamt = 0;
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}
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// Jump and Link (Call)
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let isCall=1, hasDelaySlot=1,
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@ -432,76 +441,93 @@ let isCall=1, hasDelaySlot=1,
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!strconcat(instr_asm, "\t$target"), [(MipsJmpLink imm:$target)],
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IIBranch>;
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let rd=31 in
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class JumpLinkReg<bits<6> op, bits<6> func, string instr_asm>:
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FR<op, func, (outs), (ins CPURegs:$rs, variable_ops),
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!strconcat(instr_asm, "\t$rs"), [(MipsJmpLink CPURegs:$rs)], IIBranch>;
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!strconcat(instr_asm, "\t$rs"), [(MipsJmpLink CPURegs:$rs)], IIBranch> {
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let rt = 0;
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let rd = 31;
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let shamt = 0;
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}
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class BranchLink<string instr_asm>:
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FI<0x1, (outs), (ins CPURegs:$rs, brtarget:$target, variable_ops),
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!strconcat(instr_asm, "\t$rs, $target"), [], IIBranch>;
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!strconcat(instr_asm, "\t$rs, $target"), [], IIBranch> {
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let rt = 0;
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}
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}
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// Mul, Div
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let Defs = [HI, LO] in {
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let isCommutable = 1 in
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class Mul<bits<6> func, string instr_asm, InstrItinClass itin>:
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FR<0x00, func, (outs), (ins CPURegs:$a, CPURegs:$b),
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!strconcat(instr_asm, "\t$a, $b"), [], itin>;
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class Mul<bits<6> func, string instr_asm, InstrItinClass itin>:
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FR<0x00, func, (outs), (ins CPURegs:$rs, CPURegs:$rt),
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!strconcat(instr_asm, "\t$rs, $rt"), [], itin> {
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let rd = 0;
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let shamt = 0;
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let isCommutable = 1;
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let Defs = [HI, LO];
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}
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class Div<SDNode op, bits<6> func, string instr_asm, InstrItinClass itin>:
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FR<0x00, func, (outs), (ins CPURegs:$a, CPURegs:$b),
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!strconcat(instr_asm, "\t$$zero, $a, $b"),
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[(op CPURegs:$a, CPURegs:$b)], itin>;
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class Div<SDNode op, bits<6> func, string instr_asm, InstrItinClass itin>:
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FR<0x00, func, (outs), (ins CPURegs:$rs, CPURegs:$rt),
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!strconcat(instr_asm, "\t$$zero, $rs, $rt"),
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[(op CPURegs:$rs, CPURegs:$rt)], itin> {
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let rd = 0;
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let shamt = 0;
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let Defs = [HI, LO];
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}
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// Move from Hi/Lo
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let shamt = 0 in {
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let rs = 0, rt = 0 in
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class MoveFromLOHI<bits<6> func, string instr_asm>:
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FR<0x00, func, (outs CPURegs:$dst), (ins),
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!strconcat(instr_asm, "\t$dst"), [], IIHiLo>;
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FR<0x00, func, (outs CPURegs:$rd), (ins),
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!strconcat(instr_asm, "\t$rd"), [], IIHiLo> {
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let rs = 0;
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let rt = 0;
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let shamt = 0;
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}
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let rt = 0, rd = 0 in
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class MoveToLOHI<bits<6> func, string instr_asm>:
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FR<0x00, func, (outs), (ins CPURegs:$src),
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!strconcat(instr_asm, "\t$src"), [], IIHiLo>;
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FR<0x00, func, (outs), (ins CPURegs:$rs),
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!strconcat(instr_asm, "\t$rs"), [], IIHiLo> {
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let rt = 0;
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let rd = 0;
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let shamt = 0;
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}
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class EffectiveAddress<string instr_asm> :
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FI<0x09, (outs CPURegs:$dst), (ins mem_ea:$addr),
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instr_asm, [(set CPURegs:$dst, addr:$addr)], IIAlu>;
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FI<0x09, (outs CPURegs:$rt), (ins mem_ea:$addr),
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instr_asm, [(set CPURegs:$rt, addr:$addr)], IIAlu>;
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// Count Leading Ones/Zeros in Word
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class CountLeading<bits<6> func, string instr_asm, list<dag> pattern>:
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FR<0x1c, func, (outs CPURegs:$dst), (ins CPURegs:$src),
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!strconcat(instr_asm, "\t$dst, $src"), pattern, IIAlu>,
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FR<0x1c, func, (outs CPURegs:$rd), (ins CPURegs:$rs),
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!strconcat(instr_asm, "\t$rd, $rs"), pattern, IIAlu>,
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Requires<[HasBitCount]> {
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let shamt = 0;
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let rt = rd;
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}
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// Sign Extend in Register.
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class SignExtInReg<bits<6> func, string instr_asm, ValueType vt>:
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FR<0x3f, func, (outs CPURegs:$dst), (ins CPURegs:$src),
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!strconcat(instr_asm, "\t$dst, $src"),
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[(set CPURegs:$dst, (sext_inreg CPURegs:$src, vt))], NoItinerary>;
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class SignExtInReg<bits<5> sa, string instr_asm, ValueType vt>:
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FR<0x3f, 0x20, (outs CPURegs:$rd), (ins CPURegs:$rt),
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!strconcat(instr_asm, "\t$rd, $rt"),
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[(set CPURegs:$rd, (sext_inreg CPURegs:$rt, vt))], NoItinerary> {
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let rs = 0;
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let shamt = sa;
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let Predicates = [HasSEInReg];
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}
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// Byte Swap
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class ByteSwap<bits<6> func, string instr_asm>:
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FR<0x1f, func, (outs CPURegs:$dst), (ins CPURegs:$src),
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!strconcat(instr_asm, "\t$dst, $src"),
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[(set CPURegs:$dst, (bswap CPURegs:$src))], NoItinerary>;
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// Conditional Move
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class CondMov<bits<6> func, string instr_asm, PatLeaf MovCode>:
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FR<0x00, func, (outs CPURegs:$dst), (ins CPURegs:$F, CPURegs:$T,
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CPURegs:$cond), !strconcat(instr_asm, "\t$dst, $T, $cond"),
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[], NoItinerary>;
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class ByteSwap<bits<6> func, bits<5> sa, string instr_asm>:
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FR<0x1f, func, (outs CPURegs:$rd), (ins CPURegs:$rt),
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!strconcat(instr_asm, "\t$rd, $rt"),
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[(set CPURegs:$rd, (bswap CPURegs:$rt))], NoItinerary> {
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let rs = 0;
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let shamt = sa;
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let Predicates = [HasSwap];
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}
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// Read Hardware
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class ReadHardware: FR<0x1f, 0x3b, (outs CPURegs:$dst), (ins HWRegs:$src),
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"rdhwr\t$dst, $src", [], IIAlu> {
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class ReadHardware: FR<0x1f, 0x3b, (outs CPURegs:$rt), (ins HWRegs:$rd),
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"rdhwr\t$rt, $rd", [], IIAlu> {
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let rs = 0;
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let shamt = 0;
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}
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@ -712,36 +738,31 @@ let Uses = [LO] in
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def MFLO : MoveFromLOHI<0x12, "mflo">;
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/// Sign Ext In Register Instructions.
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let Predicates = [HasSEInReg] in {
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let shamt = 0x10, rs = 0 in
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def SEB : SignExtInReg<0x21, "seb", i8>;
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let shamt = 0x18, rs = 0 in
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def SEH : SignExtInReg<0x20, "seh", i16>;
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}
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def SEB : SignExtInReg<0x10, "seb", i8>;
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def SEH : SignExtInReg<0x18, "seh", i16>;
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/// Count Leading
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def CLZ : CountLeading<0b100000, "clz",
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[(set CPURegs:$dst, (ctlz CPURegs:$src))]>;
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def CLO : CountLeading<0b100001, "clo",
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[(set CPURegs:$dst, (ctlz (not CPURegs:$src)))]>;
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def CLZ : CountLeading<0x20, "clz",
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[(set CPURegs:$rd, (ctlz CPURegs:$rs))]>;
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def CLO : CountLeading<0x21, "clo",
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[(set CPURegs:$rd, (ctlz (not CPURegs:$rs)))]>;
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/// Byte Swap
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let Predicates = [HasSwap] in {
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let shamt = 0x3, rs = 0 in
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def WSBW : ByteSwap<0x20, "wsbw">;
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}
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def WSBW : ByteSwap<0x20, 0x2, "wsbw">;
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// Conditional moves:
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// These instructions are expanded in
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// MipsISelLowering::EmitInstrWithCustomInserter if target does not have
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// conditional move instructions.
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// flag:int, data:int
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let usesCustomInserter = 1, shamt = 0, Constraints = "$F = $dst" in
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class CondMovIntInt<bits<6> funct, string instr_asm> :
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FR<0, funct, (outs CPURegs:$dst),
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(ins CPURegs:$T, CPURegs:$cond, CPURegs:$F),
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!strconcat(instr_asm, "\t$dst, $T, $cond"), [], NoItinerary>;
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class CondMovIntInt<bits<6> funct, string instr_asm> :
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FR<0, funct, (outs CPURegs:$rd),
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(ins CPURegs:$rs, CPURegs:$rt, CPURegs:$F),
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!strconcat(instr_asm, "\t$rd, $rs, $rt"), [], NoItinerary> {
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let shamt = 0;
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let usesCustomInserter = 1;
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let Constraints = "$F = $rd";
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}
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def MOVZ_I : CondMovIntInt<0x0a, "movz">;
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def MOVN_I : CondMovIntInt<0x0b, "movn">;
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@ -754,13 +775,13 @@ let addr=0 in
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// instructions. The same not happens for stack address copies, so an
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// add op with mem ComplexPattern is used and the stack address copy
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// can be matched. It's similar to Sparc LEA_ADDRi
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def LEA_ADDiu : EffectiveAddress<"addiu\t$dst, $addr">;
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def LEA_ADDiu : EffectiveAddress<"addiu\t$rt, $addr">;
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// DynAlloc node points to dynamically allocated stack space.
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// $sp is added to the list of implicitly used registers to prevent dead code
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// elimination from removing instructions that modify $sp.
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let Uses = [SP] in
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def DynAlloc : EffectiveAddress<"addiu\t$dst, $addr">;
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def DynAlloc : EffectiveAddress<"addiu\t$rt, $addr">;
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// MADD*/MSUB*
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def MADD : MArithR<0, "madd", MipsMAdd, 1>;
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