forked from OSchip/llvm-project
parent
aae8fb801e
commit
c573599137
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@ -869,25 +869,24 @@ void SelectionDAGLegalize::LegalizeLoadOps(SDNode *Node) {
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switch (TLI.getOperationAction(Node->getOpcode(), VT)) {
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default: llvm_unreachable("This action is not supported yet!");
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case TargetLowering::Legal:
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// If this is an unaligned load and the target doesn't support it,
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// expand it.
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if (!TLI.allowsUnalignedMemoryAccesses(LD->getMemoryVT())) {
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Type *Ty = LD->getMemoryVT().getTypeForEVT(*DAG.getContext());
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unsigned ABIAlignment =
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TLI.getTargetData()->getABITypeAlignment(Ty);
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if (LD->getAlignment() < ABIAlignment){
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ExpandUnalignedLoad(cast<LoadSDNode>(Node),
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DAG, TLI, RVal, RChain);
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}
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}
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break;
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// If this is an unaligned load and the target doesn't support it,
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// expand it.
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if (!TLI.allowsUnalignedMemoryAccesses(LD->getMemoryVT())) {
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Type *Ty = LD->getMemoryVT().getTypeForEVT(*DAG.getContext());
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unsigned ABIAlignment =
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TLI.getTargetData()->getABITypeAlignment(Ty);
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if (LD->getAlignment() < ABIAlignment){
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ExpandUnalignedLoad(cast<LoadSDNode>(Node), DAG, TLI, RVal, RChain);
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}
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}
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break;
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case TargetLowering::Custom: {
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SDValue Res = TLI.LowerOperation(RVal, DAG);
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if (Res.getNode()) {
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RVal = Res;
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RChain = Res.getValue(1);
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}
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break;
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SDValue Res = TLI.LowerOperation(RVal, DAG);
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if (Res.getNode()) {
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RVal = Res;
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RChain = Res.getValue(1);
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}
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break;
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}
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case TargetLowering::Promote: {
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// Only promote a load of vector type to another.
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