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[SVE][VLS] Don't combine logical AND. 

Testing is performed when targeting 128, 256 and 512-bit wide vectors.

For 128-bit vectors, the original behavior of using NEON instructions is
preserved.

Differential Revision: https://reviews.llvm.org/D85479
This commit is contained in:
Francesco Petrogalli 2020-07-31 21:19:23 +01:00
parent 2b8ad6b604
commit c561f4d2ec
2 changed files with 42 additions and 0 deletions
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5
llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
View File

@ -11156,6 +11156,11 @@ static SDValue performANDCombine(SDNode *N,
if (VT.isScalableVector())
return performSVEAndCombine(N, DCI);
// The combining code below works only for NEON vectors. In particular, it
// does not work for SVE when dealing with vectors wider than 128 bits.
if (!(VT.is64BitVector() || VT.is128BitVector()))
return SDValue();
BuildVectorSDNode *BVN =
dyn_cast<BuildVectorSDNode>(N->getOperand(1).getNode());
if (!BVN)

37
llvm/test/CodeGen/AArch64/sve-fix-length-and-combine-512.ll Normal file
View File

@ -0,0 +1,37 @@
; RUN: llc -mtriple=aarch64-linux-gnu -mattr=+sve -aarch64-sve-vector-bits-min=512 -o - -asm-verbose=0 < %s | FileCheck %s
; CHECK-LABEL: vls_sve_and_64xi8:
; CHECK-NEXT: adrp x[[ONE:[0-9]+]], .LCPI0_0
; CHECK-NEXT: ptrue p0.b, vl64
; CHECK-NEXT: add x[[TWO:[0-9]+]], x[[ONE]], :lo12:.LCPI0_0
; CHECK-NEXT: ld1b { z0.b }, p0/z, [x0]
; CHECK-NEXT: ld1b { z1.b }, p0/z, [x[[TWO]]]
; CHECK-NEXT: and z0.d, z0.d, z1.d
; CHECK-NEXT: st1b { z0.b }, p0, [x1]
; CHECK-NEXT: ret
define void @vls_sve_and_64xi8(<64 x i8>* %ap, <64 x i8>* %out) nounwind {
%a = load <64 x i8>, <64 x i8>* %ap
%b = and <64 x i8> %a, <i8 0, i8 255, i8 0, i8 255, i8 0, i8 255, i8 0, i8 255, i8 0, i8 255, i8 0, i8 255, i8 0, i8 255, i8 0, i8 255,
i8 0, i8 255, i8 0, i8 255, i8 0, i8 255, i8 0, i8 255, i8 0, i8 255, i8 0, i8 255, i8 0, i8 255, i8 0, i8 255,
i8 0, i8 255, i8 0, i8 255, i8 0, i8 255, i8 0, i8 255, i8 0, i8 255, i8 0, i8 255, i8 0, i8 255, i8 0, i8 255,
i8 0, i8 255, i8 0, i8 255, i8 0, i8 255, i8 0, i8 255, i8 0, i8 255, i8 0, i8 255, i8 0, i8 255, i8 0, i8 255>
store <64 x i8> %b, <64 x i8>* %out
ret void
}
; CHECK-LABEL: vls_sve_and_16xi8:
; CHECK-NEXT: bic v0.8h, #255
; CHECK-NEXT: ret
define <16 x i8> @vls_sve_and_16xi8(<16 x i8> %b, <16 x i8>* %out) nounwind {
%c = and <16 x i8> %b, <i8 0, i8 255, i8 0, i8 255, i8 0, i8 255, i8 0, i8 255, i8 0, i8 255, i8 0, i8 255, i8 0, i8 255, i8 0, i8 255>
ret <16 x i8> %c
}
; CHECK-LABEL: vls_sve_and_8xi8:
; CHECK-NEXT: bic v0.4h, #255
; CHECK-NEXT: ret
define <8 x i8> @vls_sve_and_8xi8(<8 x i8> %b, <8 x i8>* %out) nounwind {
%c = and <8 x i8> %b, <i8 0, i8 255, i8 0, i8 255, i8 0, i8 255, i8 0, i8 255>
ret <8 x i8> %c
}